Re: [PATCH] RISC-V: vsetvl: Refine REG_EQUAL equality.

On 11/13/23 07:47, Robin Dapp wrote: As per Jeff's remark I'm going to push the attached. Regards Robin Subject: [PATCH v4] RISC-V: vsetvl: Refine REG_EQUAL equality. This patch enhances the equality check for REG_EQUAL notes in the vsetvl pass by using the == operator instead of

Re: [PATCH] RISC-V: vsetvl: Refine REG_EQUAL equality.

As per Jeff's remark I'm going to push the attached. Regards Robin Subject: [PATCH v4] RISC-V: vsetvl: Refine REG_EQUAL equality. This patch enhances the equality check for REG_EQUAL notes in the vsetvl pass by using the == operator instead of rtx_equal_p. With that, in situations like the

Re: [PATCH] RISC-V: vsetvl: Refine REG_EQUAL equality.

On 11/13/23 01:15, juzhe.zh...@rivai.ai wrote: I know the root cause is: (reg:DI 15 a5 [orig:175 _103 ] [175]) (reg:DI 15 a5 [orig:174 _100 ] [174]) is considered as true on rtx_equal_p. I think return note1 == note2; will simplify your codes and fix this issue. NOTEs are not shared

Re: Re: [PATCH] RISC-V: vsetvl: Refine REG_EQUAL equality.

, LGTM. juzhe.zh...@rivai.ai From: Robin Dapp Date: 2023-11-13 21:28 To: juzhe.zh...@rivai.ai; gcc-patches; palmer; kito.cheng; jeffreyalaw CC: rdapp.gcc Subject: Re: [PATCH] RISC-V: vsetvl: Refine REG_EQUAL equality. On 11/13/23 11:36, juzhe.zh...@rivai.ai wrote: > --- /dev/null > +++ &

Re: [PATCH] RISC-V: vsetvl: Refine REG_EQUAL equality.

On 11/13/23 11:36, juzhe.zh...@rivai.ai wrote: > --- /dev/null > +++ > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_zbb_run-2.c > @@ -0,0 +1,19 @@ > +/* { dg-do run { target { riscv_v } } } */ > +/* { dg-additional-options "-march=rv64gcv_zbb --param >

Re: Re: [PATCH] RISC-V: vsetvl: Refine REG_EQUAL equality.

gcc-patches; palmer; kito.cheng; jeffreyalaw CC: rdapp.gcc Subject: Re: [PATCH] RISC-V: vsetvl: Refine REG_EQUAL equality. On 11/13/23 10:38, juzhe.zh...@rivai.ai wrote: > For @code{REG_EQUIV}, the register is equivalent to @var{op} throughout > the entire function, and could validly be replace

Re: [PATCH] RISC-V: vsetvl: Refine REG_EQUAL equality.

On 11/13/23 10:38, juzhe.zh...@rivai.ai wrote: > For @code{REG_EQUIV}, the register is equivalent to @var{op} throughout > the entire function, and could validly be replaced in all its > occurrences by @var{op}.  (``Validly'' here refers to the data flow of > the program; simple replacement may

Re: Re: [PATCH] RISC-V: vsetvl: Refine REG_EQUAL equality.

-patches; palmer; kito.cheng; jeffreyalaw CC: rdapp.gcc Subject: Re: [PATCH] RISC-V: vsetvl: Refine REG_EQUAL equality. On 11/13/23 10:30, juzhe.zh...@rivai.ai wrote: > I just checked definition of REG_EQUAL and REG_EQUIV. > > As you said, REG_EQUIV is more reasonable. Agree with use rt

Re: [PATCH] RISC-V: vsetvl: Refine REG_EQUAL equality.

On 11/13/23 10:30, juzhe.zh...@rivai.ai wrote: > I just checked definition of REG_EQUAL and REG_EQUIV. > > As you said, REG_EQUIV is more reasonable. Agree with use rtx_equal_p on > REG_EQUIV and skip REG_EQUAL. > Could you check whether it does fix your issues ? Yes it would fix the issues. I

Re: Re: [PATCH] RISC-V: vsetvl: Refine REG_EQUAL equality.

...@rivai.ai; gcc-patches; palmer; kito.cheng; jeffreyalaw CC: rdapp.gcc Subject: Re: [PATCH] RISC-V: vsetvl: Refine REG_EQUAL equality. On 11/13/23 09:25, juzhe.zh...@rivai.ai wrote: > Also, like kito previous remind me: > https://gcc.gnu.org/pipermail/gcc-patches/2023-November/635326.html &g

Re: [PATCH] RISC-V: vsetvl: Refine REG_EQUAL equality.

On 11/13/23 09:25, juzhe.zh...@rivai.ai wrote: > Also, like kito previous remind me: > https://gcc.gnu.org/pipermail/gcc-patches/2023-November/635326.html >   > > I think you should add a dedicated test which with specifying >

Re: Re: [PATCH] RISC-V: vsetvl: Refine REG_EQUAL equality.

regression of such issue even if I didn't build toolchain with "zbb". juzhe.zh...@rivai.ai From: Robin Dapp Date: 2023-11-13 16:12 To: juzhe.zh...@rivai.ai; gcc-patches; palmer; kito.cheng; jeffreyalaw CC: rdapp.gcc Subject: Re: [PATCH] RISC-V: vsetvl: Refine REG_EQUAL equality. > Do

Re: Re: [PATCH] RISC-V: vsetvl: Refine REG_EQUAL equality.

Sorry. It should be return note1 && note2 && note1 == note2; juzhe.zh...@rivai.ai From: Robin Dapp Date: 2023-11-13 16:12 To: juzhe.zh...@rivai.ai; gcc-patches; palmer; kito.cheng; jeffreyalaw CC: rdapp.gcc Subject: Re: [PATCH] RISC-V: vsetvl: Refine REG_EQUAL equality. &

Re: Re: [PATCH] RISC-V: vsetvl: Refine REG_EQUAL equality.

...@rivai.ai; gcc-patches; palmer; kito.cheng; jeffreyalaw CC: rdapp.gcc Subject: Re: [PATCH] RISC-V: vsetvl: Refine REG_EQUAL equality. > Does this patch fixes exposed bugs in current tests? > Or could you add test for it ? Ah, yes forgot to mention. This fixes several tests when t

Re: [PATCH] RISC-V: vsetvl: Refine REG_EQUAL equality.

> Does this patch fixes exposed bugs in current tests? > Or could you add test for it ? Ah, yes forgot to mention. This fixes several tests when testing with -march=rv64gcv_zbb. Regards Robin

Re: [PATCH] RISC-V: vsetvl: Refine REG_EQUAL equality.

Does this patch fixes exposed bugs in current tests? Or could you add test for it ? juzhe.zh...@rivai.ai From: Robin Dapp Date: 2023-11-13 16:06 To: gcc-patches; palmer; Kito Cheng; jeffreyalaw; juzhe.zh...@rivai.ai CC: rdapp.gcc Subject: [PATCH] RISC-V: vsetvl: Refine REG_EQUAL equality. Hi

[PATCH] RISC-V: vsetvl: Refine REG_EQUAL equality.

Hi, this patch enhances the equality check for REG_EQUAL notes in the vsetvl pass. Currently, we assume that two such notes describe the same value when they have the same rtx representation. This is not true when either of the note's source operands is modified by an insn between the two