On 04/11/2019 08:02 pm, Dimitar Dimitrov wrote:
On Sat, 2 Nov 2019, 19:28:38 EET Kwok Cheung Yeung wrote:
diff --git a/gcc/ira.c b/gcc/ira.c
index 9f8da67..25e9359 100644
--- a/gcc/ira.c
+++ b/gcc/ira.c
@@ -515,7 +515,13 @@ setup_alloc_regs (bool use_hard_frame_p)
#endif
no_unit_alloc_re
Hello
On 04/11/2019 04:22 pm, Georg-Johann Lay wrote:
> The avr port already uses 2 hard-reg frame pointer ever since...
>
> Does this patch has an impact on the avr port and its handling of
> the frame pointer?
I am not familiar with the AVR port, but looking at the source, it looks
like it pr
Dimitar Dimitrov writes:
> On Sat, 2 Nov 2019, 19:28:38 EET Kwok Cheung Yeung wrote:
>> The AMD GCN architecture uses 64-bit pointers, but the scalar registers
>> are 32-bit wide, so pointers must reside in a pair of registers.
> ...
>> Bootstrapped on x86_64 and tested with no regressions, which
Kwok Cheung Yeung schrieb:
The AMD GCN architecture uses 64-bit pointers, but the scalar registers
are 32-bit wide, so pointers must reside in a pair of registers.
The two hard registers holding the frame pointer are currently fixed,
but if they are changed to unfixed (so that the FP can be el
On Sat, 2 Nov 2019, 19:28:38 EET Kwok Cheung Yeung wrote:
> The AMD GCN architecture uses 64-bit pointers, but the scalar registers
> are 32-bit wide, so pointers must reside in a pair of registers.
...
> Bootstrapped on x86_64 and tested with no regressions, which is not
> surprising as nothing di
Am 04.11.19 um 16:22 schrieb Vladimir Makarov:
On 2019-11-02 1:28 p.m., Kwok Cheung Yeung wrote:
The AMD GCN architecture uses 64-bit pointers, but the scalar
registers are 32-bit wide, so pointers must reside in a pair of
registers.
The two hard registers holding the frame pointer are curre
On 2019-11-02 1:28 p.m., Kwok Cheung Yeung wrote:
The AMD GCN architecture uses 64-bit pointers, but the scalar
registers are 32-bit wide, so pointers must reside in a pair of
registers.
The two hard registers holding the frame pointer are currently fixed,
but if they are changed to unfixed
The AMD GCN architecture uses 64-bit pointers, but the scalar registers
are 32-bit wide, so pointers must reside in a pair of registers.
The two hard registers holding the frame pointer are currently fixed,
but if they are changed to unfixed (so that the FP can be eliminated),
GCC would someti
