> -Original Message-
> From: Tamar Christina
> Sent: Thursday, February 15, 2024 8:27 AM
> To: Richard Sandiford ; Andrew Pinski (QUIC)
>
> Cc: gcc-patches@gcc.gnu.org
> Subject: RE: [PATCH] aarch64: Improve PERM<{0}, a, ...> (64bit) by adding
> whol
> -Original Message-
> From: Richard Sandiford
> Sent: Thursday, February 15, 2024 2:56 PM
> To: Andrew Pinski
> Cc: gcc-patches@gcc.gnu.org; Tamar Christina
> Subject: Re: [PATCH] aarch64: Improve PERM<{0}, a, ...> (64bit) by adding
> whole
> vector shif
Andrew Pinski writes:
> The backend currently defines a whole vector shift left for 64bit vectors,
> adding the
> shift right can also improve code for some PERMs too. So this adds that
> pattern.
Is this reversed? It looks like we have the shift right and the patch is
adding the shift left
The backend currently defines a whole vector shift left for 64bit vectors,
adding the
shift right can also improve code for some PERMs too. So this adds that pattern.
I added a testcase for the shift left also. I also fixed the instruction
template
there which was using a space instead of a tab
