Re: [PATCH] dwarf: Multi-register CFI address support.

2021-12-01 Thread Jakub Jelinek via Gcc-patches
On Thu, Nov 11, 2021 at 06:12:50PM +, Hafiz Abid Qadeer wrote: > * dwarf2cfi.c (dw_stack_pointer_regnum): Change type to struct cfa_reg. > (dw_frame_pointer_regnum): Likewise. > (new_cfi_row): Use set_by_dwreg. > (get_cfa_from_loc_descr): Use set_by_dwreg. Support

Re: [PATCH] dwarf: Multi-register CFI address support.

2021-11-11 Thread Hafiz Abid Qadeer
ge it, but doing it just in case seems unnecessary > complication... Done in the attached patch. Is it ok? Thanks, -- Hafiz Abid Qadeer Mentor, a Siemens Business >From dd25eccd2458c6b6d38a922d9b2c9107c4c0ba2d Mon Sep 17 00:00:00 2001 From: Hafiz Abid Qadeer Date: Thu, 11 Nov 2021 13:43:04 +

Re: [PATCH] dwarf: Multi-register CFI address support.

2021-11-09 Thread Jakub Jelinek via Gcc-patches
On Sun, Jun 13, 2021 at 02:27:38PM +0100, Hafiz Abid Qadeer wrote: > *** with this patch (edited for brevity)*** > > 0024 CIE > > DW_CFA_def_cfa_expression: DW_OP_bregx SGPR49+0, DW_OP_const1u 0x20, > DW_OP_shl, DW_OP_bregx SGPR48+0, DW_OP_plus > DW_CFA_expression:

Re: [PATCH] dwarf: Multi-register CFI address support.

2021-11-02 Thread Hafiz Abid Qadeer
Ping. On 24/08/2021 16:55, Hafiz Abid Qadeer wrote: > Ping. > > On 22/07/2021 11:58, Hafiz Abid Qadeer wrote: >> Ping. >> >> On 13/06/2021 14:27, Hafiz Abid Qadeer wrote: >>> Add support for architectures such as AMD GCN, in which the pointer size is >>> larger than the register size. This

Re: [PATCH] dwarf: Multi-register CFI address support.

2021-08-24 Thread Hafiz Abid Qadeer
Ping. On 22/07/2021 11:58, Hafiz Abid Qadeer wrote: > Ping. > > On 13/06/2021 14:27, Hafiz Abid Qadeer wrote: >> Add support for architectures such as AMD GCN, in which the pointer size is >> larger than the register size. This allows the CFI information to include >> multi-register locations

Re: [PATCH] dwarf: Multi-register CFI address support.

2021-07-22 Thread Hafiz Abid Qadeer
Ping. On 13/06/2021 14:27, Hafiz Abid Qadeer wrote: > Add support for architectures such as AMD GCN, in which the pointer size is > larger than the register size. This allows the CFI information to include > multi-register locations for the stack pointer, frame pointer, and return > address. >

[PATCH] dwarf: Multi-register CFI address support.

2021-06-13 Thread Hafiz Abid Qadeer
Add support for architectures such as AMD GCN, in which the pointer size is larger than the register size. This allows the CFI information to include multi-register locations for the stack pointer, frame pointer, and return address. This patch was originally posted by Andrew Stubbs in

Re: [PATCH] dwarf: Multi-register CFI address support

2020-10-19 Thread Jakub Jelinek via Gcc-patches
On Fri, Aug 28, 2020 at 01:04:51PM +0100, Andrew Stubbs wrote: > This patch introduces DWARF CFI support for architectures that require > multiple registers to hold pointers, such as the stack pointer, frame > pointer, and return address. The motivating case is the AMD GCN architecture > which has

Re: [PATCH] dwarf: Multi-register CFI address support

2020-10-05 Thread Andrew Stubbs
Ping. On 21/09/2020 14:51, Andrew Stubbs wrote: Ping. On 03/09/2020 16:29, Andrew Stubbs wrote: On 28/08/2020 13:04, Andrew Stubbs wrote: Hi all, This patch introduces DWARF CFI support for architectures that require multiple registers to hold pointers, such as the stack pointer, frame

Re: [PATCH] dwarf: Multi-register CFI address support

2020-09-21 Thread Andrew Stubbs
Ping. On 03/09/2020 16:29, Andrew Stubbs wrote: On 28/08/2020 13:04, Andrew Stubbs wrote: Hi all, This patch introduces DWARF CFI support for architectures that require multiple registers to hold pointers, such as the stack pointer, frame pointer, and return address. The motivating case is

Re: [PATCH] dwarf: Multi-register CFI address support

2020-09-03 Thread Andrew Stubbs
On 28/08/2020 13:04, Andrew Stubbs wrote: Hi all, This patch introduces DWARF CFI support for architectures that require multiple registers to hold pointers, such as the stack pointer, frame pointer, and return address. The motivating case is the AMD GCN architecture which has 64-bit address

Re: [PATCH] dwarf: Multi-register CFI address support

2020-09-02 Thread Tom Tromey
> "Andrew" == Andrew Stubbs writes: Andrew> http://llvm.org/docs/AMDGPUDwarfExtensionsForHeterogeneousDebugging.html#composite-location-description-operations Thanks. Adding that to the appropriate spot in the patch would be great. Tom

Re: [PATCH] dwarf: Multi-register CFI address support

2020-09-02 Thread Andrew Stubbs
On 02/09/2020 18:49, Tom Tromey wrote: "Andrew" == Andrew Stubbs writes: Andrew> To be fair, the DWARF standard makes a similar assumption; the Andrew> engineers working on LLVM and GDB, at AMD, have therefore invented Andrew> some new DWARF operators that they plan to propose for a future

Re: [PATCH] dwarf: Multi-register CFI address support

2020-09-02 Thread Tom Tromey
> "Andrew" == Andrew Stubbs writes: Andrew> To be fair, the DWARF standard makes a similar assumption; the Andrew> engineers working on LLVM and GDB, at AMD, have therefore invented Andrew> some new DWARF operators that they plan to propose for a future Andrew> standard. Only one is relevant

[PATCH] dwarf: Multi-register CFI address support

2020-08-28 Thread Andrew Stubbs
Hi all, This patch introduces DWARF CFI support for architectures that require multiple registers to hold pointers, such as the stack pointer, frame pointer, and return address. The motivating case is the AMD GCN architecture which has 64-bit address pointers, but 32-bit registers. The