On 11/12/23 07:01, Lehua Ding wrote:
Thanks for the specint performance data. I'll do my best to get the
compile time and memory issues fixed. I'm very curious to know if the
way used to solve the subreg coalesce problem makes sense to you?
If it works, it is ok for me. There is always a
On 2023/11/13 9:11, juzhe.zh...@rivai.ai wrote:
Ah, nice! How configurable are the bit ranges?
I think Lehua's patch is configurable for bit ranges.
Since his patch allow target flexible tracking subreg livenesss
according to REGMODE_NATURAL_SIZE
+/* Return true if REGNO is a pseudo and
v
Subject: Re: [PATCH 0/7] ira/lra: Support subreg coalesce
钟居哲 writes:
> Hi, Richard.
>
>>> Maybe dead lanes are better tracked at the gimple level though, not sure.
>>> (But AArch64 might need to lower lane operations more than it does now if
>>> we want gimp
Hi Vladimir,
While you're starting your review, please review v3 version that fixes
some ICE issues, thanks.
https://gcc.gnu.org/pipermail/gcc-patches/2023-November/636178.html
On 2023/11/12 20:01, Lehua Ding wrote:
Hi Vladimir,
On 2023/11/10 4:24, Vladimir Makarov wrote:
On 11/7/23
Hi Vladimir,
On 2023/11/10 4:24, Vladimir Makarov wrote:
On 11/7/23 22:47, Lehua Ding wrote:
Lehua Ding (7):
ira: Refactor the handling of register conflicts to make it more
general
ira: Add live_subreg problem and apply to ira pass
ira: Support subreg live range track
ira:
钟居哲 writes:
> Hi, Richard.
>
>>> Maybe dead lanes are better tracked at the gimple level though, not sure.
>>> (But AArch64 might need to lower lane operations more than it does now if
>>> we want gimple to handle it.)
>
> We were trying to address such issue at GIMPLE leve at the beginning.
>
Hi Dimitar,
I solved the problem you reported in V2 patch
(https://gcc.gnu.org/pipermail/gcc-patches/2023-November/636166.html),
is it possible for you to help confirm this? Thank you very much.
On 2023/11/9 0:56, Dimitar Dimitrov wrote:
On Wed, Nov 08, 2023 at 11:47:33AM +0800, Lehua Ding
Hi Dimitar,
On 2023/11/11 0:00, Dimitar Dimitrov wrote:
On Fri, Nov 10, 2023 at 04:53:57PM +0800, Lehua Ding wrote:
The divide by zero error above is interesting. I'm not sure why
ira_reg_class_max_nregs[] yields 0 for the pseudo register 168 in
the following rtx:
(debug_insn 168 167 169 19
generic problems.
Thanks.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-11-11 23:33
To: Jeff Law
CC: Lehua Ding; gcc-patches; vmakarov; juzhe.zhong
Subject: Re: [PATCH 0/7] ira/lra: Support subreg coalesce
Jeff Law writes:
> On 11/8/23 02:40, Richard Sandiford wrote:
&g
On 11/11/23 08:33, Richard Sandiford wrote:
Joern's code is a bit of a mess, but Jivan and I are slowly untangling
it from a correctness standpoint. It'll also need the usual cleanups.
Ah, nice! How configurable are the bit ranges? We might be able to use
something similar to track
Jeff Law writes:
> On 11/8/23 02:40, Richard Sandiford wrote:
>> Lehua Ding writes:
>>> Hi,
>>>
>>> These patchs try to support subreg coalesce feature in
>>> register allocation passes (ira and lra).
>>
>> Thanks a lot for the series. This is definitely something we've
>> needed for a while.
On Fri, Nov 10, 2023 at 04:53:57PM +0800, Lehua Ding wrote:
> > > The divide by zero error above is interesting. I'm not sure why
> > > ira_reg_class_max_nregs[] yields 0 for the pseudo register 168 in
> > > the following rtx:
> > > (debug_insn 168 167 169 19 (var_location:SI encoding (reg/v:SI
On 11/10/23 03:39, Richard Sandiford wrote:
Lehua Ding writes:
On 2023/11/10 18:16, Richard Sandiford wrote:
Lehua Ding writes:
Hi Richard,
On 2023/11/8 17:40, Richard Sandiford wrote:
Tracking subreg liveness will sometimes expose dead code that
wasn't obvious without it. PR89606 has
Lehua Ding writes:
> On 2023/11/10 18:16, Richard Sandiford wrote:
>> Lehua Ding writes:
>>> Hi Richard,
>>>
>>> On 2023/11/8 17:40, Richard Sandiford wrote:
Tracking subreg liveness will sometimes expose dead code that
wasn't obvious without it. PR89606 has an example of this.
On 2023/11/10 18:16, Richard Sandiford wrote:
Lehua Ding writes:
Hi Richard,
On 2023/11/8 17:40, Richard Sandiford wrote:
Tracking subreg liveness will sometimes expose dead code that
wasn't obvious without it. PR89606 has an example of this.
There the dead code was introduced by init-regs,
Lehua Ding writes:
> Hi Richard,
>
> On 2023/11/8 17:40, Richard Sandiford wrote:
>> Tracking subreg liveness will sometimes expose dead code that
>> wasn't obvious without it. PR89606 has an example of this.
>> There the dead code was introduced by init-regs, and there's a
>> debate about (a)
Hi Jeff,
On 2023/11/9 3:13, Jeff Law wrote:
The other thing to ponder. Jivan and I have been banging on Joern's
sub-object tracking bits for a totally different problem in the RISC-V
space. But there may be some overlap.
Essentially Joern's code tracks liveness for a few chunks in
On 2023/11/8 11:55, juzhe.zh...@rivai.ai wrote:
Thanks Lehua.
Appreciate for supporting subreg liveness tracking with tons of work.
A nit comments, I think you should mention these following PRs:
106694
89967
106146
99161
No need send V2 now. You can send V2 after Richard and Vlad
Hi Richard,
On 2023/11/8 17:40, Richard Sandiford wrote:
Tracking subreg liveness will sometimes expose dead code that
wasn't obvious without it. PR89606 has an example of this.
There the dead code was introduced by init-regs, and there's a
debate about (a) whether init-regs should still be
The divide by zero error above is interesting. I'm not sure why
ira_reg_class_max_nregs[] yields 0 for the pseudo register 168 in the
following rtx:
(debug_insn 168 167 169 19 (var_location:SI encoding (reg/v:SI 168 [
encoding ])) -1
(nil))
I just cross compiled an arm-none-eabi
Hi Dimitar,
Thanks for the tests.
This patch set breaks the build for at least three embedded targets. See
below.
For avr the GCC build fails with:
/mnt/nvme/dinux/local-workspace/gcc/gcc/ira-lives.cc:149:39: error: call of overloaded
‘set_subreg_conflict_hard_regs(ira_allocno*&, int&)’ is
On Thu, Nov 9, 2023 at 9:25 PM Vladimir Makarov wrote:
>
>
> On 11/7/23 22:47, Lehua Ding wrote:
> >
> > Lehua Ding (7):
> >ira: Refactor the handling of register conflicts to make it more
> > general
> >ira: Add live_subreg problem and apply to ira pass
> >ira: Support subreg
On 11/7/23 22:47, Lehua Ding wrote:
Lehua Ding (7):
ira: Refactor the handling of register conflicts to make it more
general
ira: Add live_subreg problem and apply to ira pass
ira: Support subreg live range track
ira: Support subreg copy
ira: Add all nregs >= 2 pseudos to
On 11/8/23 02:40, Richard Sandiford wrote:
Lehua Ding writes:
Hi,
These patchs try to support subreg coalesce feature in
register allocation passes (ira and lra).
Thanks a lot for the series. This is definitely something we've
needed for a while.
I probably won't be able to look at it
On Wed, Nov 08, 2023 at 11:47:33AM +0800, Lehua Ding wrote:
> Hi,
>
> These patchs try to support subreg coalesce feature in
> register allocation passes (ira and lra).
Hi Lehua,
This patch set breaks the build for at least three embedded targets. See
below.
For avr the GCC build fails with:
Lehua Ding writes:
> Hi,
>
> These patchs try to support subreg coalesce feature in
> register allocation passes (ira and lra).
Thanks a lot for the series. This is definitely something we've
needed for a while.
I probably won't be able to look at it in detail for a couple of weeks
(and the
: 2023-11-08 11:47
To: gcc-patches
CC: vmakarov; richard.sandiford; juzhe.zhong; lehua.ding
Subject: [PATCH 0/7] ira/lra: Support subreg coalesce
Hi,
These patchs try to support subreg coalesce feature in
register allocation passes (ira and lra).
Let's consider a RISC-V program (https
Hi,
These patchs try to support subreg coalesce feature in
register allocation passes (ira and lra).
Let's consider a RISC-V program (https://godbolt.org/z/ec51d91aT):
```
#include
void
foo (int32_t *in, int32_t *out, size_t m)
{
vint32m2_t result = __riscv_vle32_v_i32m2 (in, 32);
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