Factorize vrmlaldavhaq, vrmlaldavhaxq, vrmlsldavhaq, vrmlsldavhaxq
builtins so that they use the same parameterized names.
2022-12-12 Christophe Lyon <christophe.l...@arm.com>
gcc/
* config/arm/iterators.md (MVE_VRMLxLDAVHAxQ)
(MVE_VRMLxLDAVHAxQ_P): New.
(mve_insn): Add vrmlaldavha, vrmlaldavhax, vrmlsldavha,
vrmlsldavhax.
(supf): Add VRMLALDAVHAXQ_P_S, VRMLALDAVHAXQ_S, VRMLSLDAVHAQ_P_S,
VRMLSLDAVHAQ_S, VRMLSLDAVHAXQ_P_S, VRMLSLDAVHAXQ_S,
VRMLALDAVHAQ_P_S.
* config/arm/mve.md (mve_vrmlaldavhaq_<supf>v4si)
(mve_vrmlaldavhaxq_sv4si, mve_vrmlsldavhaxq_sv4si)
(mve_vrmlsldavhaq_sv4si): Merge into ...
(@mve_<mve_insn>q_<supf>v4si): ... this.
(mve_vrmlaldavhaq_p_sv4si, mve_vrmlaldavhaq_p_uv4si)
(mve_vrmlaldavhaxq_p_sv4si, mve_vrmlsldavhaq_p_sv4si)
(mve_vrmlsldavhaxq_p_sv4si): Merge into ...
(@mve_<mve_insn>q_p_<supf>v4si): ... this.
---
gcc/config/arm/iterators.md | 29 ++++++++
gcc/config/arm/mve.md | 140 ++++--------------------------------
2 files changed, 44 insertions(+), 125 deletions(-)
diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index f88da604c19..116dd95fd88 100644
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -809,6 +809,20 @@ (define_int_iterator MVE_VRMLxLDAVHxQ_P [
VRMLSLDAVHXQ_P_S
])
+(define_int_iterator MVE_VRMLxLDAVHAxQ [
+ VRMLALDAVHAQ_S VRMLALDAVHAQ_U
+ VRMLALDAVHAXQ_S
+ VRMLSLDAVHAQ_S
+ VRMLSLDAVHAXQ_S
+ ])
+
+(define_int_iterator MVE_VRMLxLDAVHAxQ_P [
+ VRMLALDAVHAQ_P_S VRMLALDAVHAQ_P_U
+ VRMLALDAVHAXQ_P_S
+ VRMLSLDAVHAQ_P_S
+ VRMLSLDAVHAXQ_P_S
+ ])
+
(define_int_iterator MVE_MOVN [
VMOVNBQ_S VMOVNBQ_U
VMOVNTQ_S VMOVNTQ_U
@@ -1077,10 +1091,18 @@ (define_int_attr mve_insn [
(VREV64Q_S "vrev64") (VREV64Q_U "vrev64") (VREV64Q_F "vrev64")
(VRHADDQ_M_S "vrhadd") (VRHADDQ_M_U "vrhadd")
(VRHADDQ_S "vrhadd") (VRHADDQ_U "vrhadd")
+ (VRMLALDAVHAQ_P_S "vrmlaldavha") (VRMLALDAVHAQ_P_U
"vrmlaldavha")
+ (VRMLALDAVHAQ_S "vrmlaldavha") (VRMLALDAVHAQ_U "vrmlaldavha")
+ (VRMLALDAVHAXQ_P_S "vrmlaldavhax")
+ (VRMLALDAVHAXQ_S "vrmlaldavhax")
(VRMLALDAVHQ_P_S "vrmlaldavh") (VRMLALDAVHQ_P_U "vrmlaldavh")
(VRMLALDAVHQ_S "vrmlaldavh") (VRMLALDAVHQ_U "vrmlaldavh")
(VRMLALDAVHXQ_P_S "vrmlaldavhx")
(VRMLALDAVHXQ_S "vrmlaldavhx")
+ (VRMLSLDAVHAQ_P_S "vrmlsldavha")
+ (VRMLSLDAVHAQ_S "vrmlsldavha")
+ (VRMLSLDAVHAXQ_P_S "vrmlsldavhax")
+ (VRMLSLDAVHAXQ_S "vrmlsldavhax")
(VRMLSLDAVHQ_P_S "vrmlsldavh")
(VRMLSLDAVHQ_S "vrmlsldavh")
(VRMLSLDAVHXQ_P_S "vrmlsldavhx")
@@ -2461,6 +2483,13 @@ (define_int_attr supf [(VCVTQ_TO_F_S "s") (VCVTQ_TO_F_U
"u") (VREV16Q_S "s")
(VQDMULLTQ_M_S "s")
(VQDMULLTQ_M_N_S "s")
(VQDMULLTQ_N_S "s")
+ (VRMLALDAVHAXQ_P_S "s")
+ (VRMLALDAVHAXQ_S "s")
+ (VRMLSLDAVHAQ_P_S "s")
+ (VRMLSLDAVHAQ_S "s")
+ (VRMLSLDAVHAXQ_P_S "s")
+ (VRMLSLDAVHAXQ_S "s")
+ (VRMLALDAVHAQ_P_S "s") (VRMLALDAVHAQ_P_U "u")
])
;; Both kinds of return insn.
diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index e75a30b7ed4..b4faf7a4b18 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -1677,18 +1677,21 @@ (define_insn "@mve_<mve_insn>q_n_<supf><mode>"
])
;;
-;; [vrmlaldavhaq_s vrmlaldavhaq_u])
+;; [vrmlaldavhaq_s vrmlaldavhaq_u]
+;; [vrmlaldavhaxq_s]
+;; [vrmlsldavhaq_s]
+;; [vrmlsldavhaxq_s]
;;
-(define_insn "mve_vrmlaldavhaq_<supf>v4si"
+(define_insn "@mve_<mve_insn>q_<supf>v4si"
[
(set (match_operand:DI 0 "s_register_operand" "=r")
(unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
(match_operand:V4SI 2 "s_register_operand" "w")
(match_operand:V4SI 3 "s_register_operand" "w")]
- VRMLALDAVHAQ))
+ MVE_VRMLxLDAVHAxQ))
]
"TARGET_HAVE_MVE"
- "vrmlaldavha.<supf>32\t%Q0, %R0, %q2, %q3"
+ "<mve_insn>.<supf>32\t%Q0, %R0, %q2, %q3"
[(set_attr "type" "mve_move")
])
@@ -2514,22 +2517,6 @@ (define_insn "@mve_<mve_insn>q_m_f<mode>"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
-;;
-;; [vrmlaldavhaxq_s])
-;;
-(define_insn "mve_vrmlaldavhaxq_sv4si"
- [
- (set (match_operand:DI 0 "s_register_operand" "=r")
- (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
- (match_operand:V4SI 2 "s_register_operand" "w")
- (match_operand:V4SI 3 "s_register_operand" "w")]
- VRMLALDAVHAXQ_S))
- ]
- "TARGET_HAVE_MVE"
- "vrmlaldavhax.s32 %Q0, %R0, %q2, %q3"
- [(set_attr "type" "mve_move")
-])
-
;;
;; [vrmlaldavhq_p_u vrmlaldavhq_p_s]
;; [vrmlaldavhxq_p_s]
@@ -2549,22 +2536,6 @@ (define_insn "@mve_<mve_insn>q_p_<supf>v4si"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
-;;
-;; [vrmlsldavhaxq_s])
-;;
-(define_insn "mve_vrmlsldavhaxq_sv4si"
- [
- (set (match_operand:DI 0 "s_register_operand" "=r")
- (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
- (match_operand:V4SI 2 "s_register_operand" "w")
- (match_operand:V4SI 3 "s_register_operand" "w")]
- VRMLSLDAVHAXQ_S))
- ]
- "TARGET_HAVE_MVE"
- "vrmlsldavhax.s32 %Q0, %R0, %q2, %q3"
- [(set_attr "type" "mve_move")
-])
-
;;
;; [vcvtmq_m_s, vcvtmq_m_u])
;;
@@ -2662,22 +2633,6 @@ (define_insn "mve_vcvtq_m_from_f_<supf><mode>"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
-;;
-;; [vrmlsldavhaq_s])
-;;
-(define_insn "mve_vrmlsldavhaq_sv4si"
- [
- (set (match_operand:DI 0 "s_register_operand" "=r")
- (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
- (match_operand:V4SI 2 "s_register_operand" "w")
- (match_operand:V4SI 3 "s_register_operand" "w")]
- VRMLSLDAVHAQ_S))
- ]
- "TARGET_HAVE_MVE"
- "vrmlsldavha.s32 %Q0, %R0, %q2, %q3"
- [(set_attr "type" "mve_move")
-])
-
;;
;; [vabavq_p_s, vabavq_p_u])
;;
@@ -3131,19 +3086,22 @@ (define_insn "@mve_<mve_insn>q_m_n_<supf><mode>"
(set_attr "length""8")])
;;
-;; [vrmlaldavhaq_p_s])
+;; [vrmlaldavhaq_p_s, vrmlaldavhaq_p_u]
+;; [vrmlaldavhaxq_p_s]
+;; [vrmlsldavhaq_p_s]
+;; [vrmlsldavhaxq_p_s]
;;
-(define_insn "mve_vrmlaldavhaq_p_sv4si"
+(define_insn "@mve_<mve_insn>q_p_<supf>v4si"
[
(set (match_operand:DI 0 "s_register_operand" "=r")
(unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
(match_operand:V4SI 2 "s_register_operand" "w")
(match_operand:V4SI 3 "s_register_operand" "w")
- (match_operand:<MVE_VPRED> 4 "vpr_register_operand"
"Up")]
- VRMLALDAVHAQ_P_S))
+ (match_operand:V4BI 4 "vpr_register_operand" "Up")]
+ MVE_VRMLxLDAVHAxQ_P))
]
"TARGET_HAVE_MVE"
- "vpst\;vrmlaldavhat.s32\t%Q0, %R0, %q2, %q3"
+ "vpst\;<mve_insn>t.<supf>32\t%Q0, %R0, %q2, %q3"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
@@ -3235,74 +3193,6 @@ (define_insn "@mve_<mve_insn>q_m_<supf><mode>"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
-;;
-;; [vrmlaldavhaq_p_u])
-;;
-(define_insn "mve_vrmlaldavhaq_p_uv4si"
- [
- (set (match_operand:DI 0 "s_register_operand" "=r")
- (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
- (match_operand:V4SI 2 "s_register_operand" "w")
- (match_operand:V4SI 3 "s_register_operand" "w")
- (match_operand:<MVE_VPRED> 4 "vpr_register_operand"
"Up")]
- VRMLALDAVHAQ_P_U))
- ]
- "TARGET_HAVE_MVE"
- "vpst\;vrmlaldavhat.u32\t%Q0, %R0, %q2, %q3"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
-;;
-;; [vrmlaldavhaxq_p_s])
-;;
-(define_insn "mve_vrmlaldavhaxq_p_sv4si"
- [
- (set (match_operand:DI 0 "s_register_operand" "=r")
- (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
- (match_operand:V4SI 2 "s_register_operand" "w")
- (match_operand:V4SI 3 "s_register_operand" "w")
- (match_operand:<MVE_VPRED> 4 "vpr_register_operand"
"Up")]
- VRMLALDAVHAXQ_P_S))
- ]
- "TARGET_HAVE_MVE"
- "vpst\;vrmlaldavhaxt.s32\t%Q0, %R0, %q2, %q3"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
-;;
-;; [vrmlsldavhaq_p_s])
-;;
-(define_insn "mve_vrmlsldavhaq_p_sv4si"
- [
- (set (match_operand:DI 0 "s_register_operand" "=r")
- (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
- (match_operand:V4SI 2 "s_register_operand" "w")
- (match_operand:V4SI 3 "s_register_operand" "w")
- (match_operand:<MVE_VPRED> 4 "vpr_register_operand"
"Up")]
- VRMLSLDAVHAQ_P_S))
- ]
- "TARGET_HAVE_MVE"
- "vpst\;vrmlsldavhat.s32\t%Q0, %R0, %q2, %q3"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
-;;
-;; [vrmlsldavhaxq_p_s])
-;;
-(define_insn "mve_vrmlsldavhaxq_p_sv4si"
- [
- (set (match_operand:DI 0 "s_register_operand" "=r")
- (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
- (match_operand:V4SI 2 "s_register_operand" "w")
- (match_operand:V4SI 3 "s_register_operand" "w")
- (match_operand:<MVE_VPRED> 4 "vpr_register_operand"
"Up")]
- VRMLSLDAVHAXQ_P_S))
- ]
- "TARGET_HAVE_MVE"
- "vpst\;vrmlsldavhaxt.s32\t%Q0, %R0, %q2, %q3"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
;;
;; [vabdq_m_f]
;; [vaddq_m_f]
--
2.34.1
