Factorize vqshluq builtins so that they use parameterized names.
2022-12-12 Christophe Lyon <christophe.l...@arm.com>
gcc/
* config/arm/iterators.md (mve_insn): Add vqshlu.
(supf): Add VQSHLUQ_M_N_S, VQSHLUQ_N_S.
(VQSHLUQ_M_N, VQSHLUQ_N): New.
* config/arm/mve.md (mve_vqshluq_n_s<mode>): Change name into ...
(@mve_<mve_insn>q_n_<supf><mode>): ... this.
(mve_vqshluq_m_n_s<mode>): Change name into ...
(@mve_<mve_insn>q_m_n_<supf><mode>): ... this.
---
gcc/config/arm/iterators.md | 6 ++++++
gcc/config/arm/mve.md | 12 ++++++------
2 files changed, 12 insertions(+), 6 deletions(-)
diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index 116dd95fd88..d1d14488b56 100644
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -1071,6 +1071,8 @@ (define_int_attr mve_insn [
(VQSHLQ_N_S "vqshl") (VQSHLQ_N_U "vqshl")
(VQSHLQ_R_S "vqshl") (VQSHLQ_R_U "vqshl")
(VQSHLQ_S "vqshl") (VQSHLQ_U "vqshl")
+ (VQSHLUQ_M_N_S "vqshlu")
+ (VQSHLUQ_N_S "vqshlu")
(VQSHRNBQ_M_N_S "vqshrnb") (VQSHRNBQ_M_N_U "vqshrnb")
(VQSHRNBQ_N_S "vqshrnb") (VQSHRNBQ_N_U "vqshrnb")
(VQSHRNTQ_M_N_S "vqshrnt") (VQSHRNTQ_M_N_U "vqshrnt")
@@ -2490,6 +2492,8 @@ (define_int_attr supf [(VCVTQ_TO_F_S "s") (VCVTQ_TO_F_U
"u") (VREV16Q_S "s")
(VRMLSLDAVHAXQ_P_S "s")
(VRMLSLDAVHAXQ_S "s")
(VRMLALDAVHAQ_P_S "s") (VRMLALDAVHAQ_P_U "u")
+ (VQSHLUQ_M_N_S "s")
+ (VQSHLUQ_N_S "s")
])
;; Both kinds of return insn.
@@ -2793,6 +2797,8 @@ (define_int_iterator VADCQ_M [VADCQ_M_U VADCQ_M_S])
(define_int_iterator UQRSHLLQ [UQRSHLL_64 UQRSHLL_48])
(define_int_iterator SQRSHRLQ [SQRSHRL_64 SQRSHRL_48])
(define_int_iterator VSHLCQ_M [VSHLCQ_M_S VSHLCQ_M_U])
+(define_int_iterator VQSHLUQ_M_N [VQSHLUQ_M_N_S])
+(define_int_iterator VQSHLUQ_N [VQSHLUQ_N_S])
;; Define iterators for VCMLA operations
(define_int_iterator VCMLA_OP [UNSPEC_VCMLA
diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index b4faf7a4b18..7898361b859 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -1150,15 +1150,15 @@ (define_insn "@mve_<mve_insn>q_r_<supf><mode>"
;;
;; [vqshluq_n_s])
;;
-(define_insn "mve_vqshluq_n_s<mode>"
+(define_insn "@mve_<mve_insn>q_n_<supf><mode>"
[
(set (match_operand:MVE_2 0 "s_register_operand" "=w")
(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
(match_operand:SI 2 "<MVE_pred>" "<MVE_constraint>")]
- VQSHLUQ_N_S))
+ VQSHLUQ_N))
]
"TARGET_HAVE_MVE"
- "vqshlu.s%#<V_sz_elem>\t%q0, %q1, %2"
+ "<mve_insn>.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
[(set_attr "type" "mve_move")
])
@@ -2653,17 +2653,17 @@ (define_insn "@mve_<mve_insn>q_p_<supf><mode>"
;;
;; [vqshluq_m_n_s])
;;
-(define_insn "mve_vqshluq_m_n_s<mode>"
+(define_insn "@mve_<mve_insn>q_m_n_<supf><mode>"
[
(set (match_operand:MVE_2 0 "s_register_operand" "=w")
(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
(match_operand:MVE_2 2 "s_register_operand" "w")
(match_operand:SI 3 "<MVE_pred>" "<MVE_constraint>")
(match_operand:<MVE_VPRED> 4 "vpr_register_operand"
"Up")]
- VQSHLUQ_M_N_S))
+ VQSHLUQ_M_N))
]
"TARGET_HAVE_MVE"
- "vpst\n\tvqshlut.s%#<V_sz_elem>\t%q0, %q2, %3"
+ "vpst\n\t<mve_insn>t.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
[(set_attr "type" "mve_move")
(set_attr "length" "8")])
--
2.34.1
