Re: [PATCH 2/2, RISC-V] Optimize switch with sign-extended index.

On Wed, May 2, 2018 at 3:05 PM, Jim Wilson wrote:> > * config/riscv/riscv.c (riscv_extend_comparands): In unsigned QImode > test, check for sign extended subreg and/or constant operands, and > do a sign extend in that case. > > gcc/testsuite/ >

[PATCH 2/2, RISC-V] Optimize switch with sign-extended index.

In the RISC-V backend, there is code that does a zero-extend by default for QImode compare arguments. This is because zero-extend is a single and insn, whereas sign-extend is two shifts. However, if we have two values that are already sign extended, or a sign extended value and a CONST_INT, then