Re: [PATCH 2/2] aarch64: Support `{1.0f, 1.0f, 0.0, 0.0}` CST forming with fmov with a smaller vector type.

Andrew Pinski writes: > This enables construction of V4SF CST like `{1.0f, 1.0f, 0.0f, 0.0f}` > (and other fp enabled CSTs) by using `fmov v0.2s, 1.0` as the instruction > is designed to zero out the other bits. > This is a small extension on top of the code that creates fmov for the case > where

[PATCH 2/2] aarch64: Support `{1.0f, 1.0f, 0.0, 0.0}` CST forming with fmov with a smaller vector type.

This enables construction of V4SF CST like `{1.0f, 1.0f, 0.0f, 0.0f}` (and other fp enabled CSTs) by using `fmov v0.2s, 1.0` as the instruction is designed to zero out the other bits. This is a small extension on top of the code that creates fmov for the case where the all but the first element is