Factorize vcmlaq builtins so that they use parameterized names.
2023-17-13 Christophe Lyon <christophe.l...@linaro.org>
gcc/
* config/arm/arm_mve_builtins.def (vcmlaq_rot90_f)
(vcmlaq_rot270_f, vcmlaq_rot180_f, vcmlaq_f): Add "_f" suffix.
* config/arm/iterators.md (MVE_VCMLAQ_M): New.
(mve_insn): Add vcmla.
(rot): Add VCMLAQ_M_F, VCMLAQ_ROT90_M_F, VCMLAQ_ROT180_M_F,
VCMLAQ_ROT270_M_F.
(mve_rot): Add VCMLAQ_M_F, VCMLAQ_ROT90_M_F, VCMLAQ_ROT180_M_F,
VCMLAQ_ROT270_M_F.
* config/arm/mve.md (mve_vcmlaq<mve_rot><mode>): Rename into ...
(@mve_<mve_insn>q<mve_rot>_f<mode>): ... this.
(mve_vcmlaq_m_f<mode>, mve_vcmlaq_rot180_m_f<mode>)
(mve_vcmlaq_rot270_m_f<mode>, mve_vcmlaq_rot90_m_f<mode>): Merge
into ...
(@mve_<mve_insn>q<mve_rot>_m_f<mode>): ... this.
---
gcc/config/arm/arm_mve_builtins.def | 10 ++---
gcc/config/arm/iterators.md | 19 ++++++++-
gcc/config/arm/mve.md | 64 ++++-------------------------
3 files changed, 29 insertions(+), 64 deletions(-)
diff --git a/gcc/config/arm/arm_mve_builtins.def
b/gcc/config/arm/arm_mve_builtins.def
index 56358c0bd02..43dacc3dda1 100644
--- a/gcc/config/arm/arm_mve_builtins.def
+++ b/gcc/config/arm/arm_mve_builtins.def
@@ -378,6 +378,10 @@ VAR3 (TERNOP_NONE_NONE_NONE_NONE, vmlasq_n_s, v16qi, v8hi,
v4si)
VAR3 (TERNOP_NONE_NONE_NONE_NONE, vmlaq_n_s, v16qi, v8hi, v4si)
VAR3 (TERNOP_NONE_NONE_NONE_NONE, vmladavaxq_s, v16qi, v8hi, v4si)
VAR3 (TERNOP_NONE_NONE_NONE_NONE, vmladavaq_s, v16qi, v8hi, v4si)
+VAR2 (TERNOP_NONE_NONE_NONE_NONE, vcmlaq_rot90_f, v8hf, v4sf)
+VAR2 (TERNOP_NONE_NONE_NONE_NONE, vcmlaq_rot270_f, v8hf, v4sf)
+VAR2 (TERNOP_NONE_NONE_NONE_NONE, vcmlaq_rot180_f, v8hf, v4sf)
+VAR2 (TERNOP_NONE_NONE_NONE_NONE, vcmlaq_f, v8hf, v4sf)
VAR3 (TERNOP_NONE_NONE_NONE_IMM, vsriq_n_s, v16qi, v8hi, v4si)
VAR3 (TERNOP_NONE_NONE_NONE_IMM, vsliq_n_s, v16qi, v8hi, v4si)
VAR2 (TERNOP_UNONE_UNONE_UNONE_PRED, vrev32q_m_u, v16qi, v8hi)
@@ -876,9 +880,3 @@ VAR3 (QUADOP_NONE_NONE_UNONE_IMM_PRED, vshlcq_m_vec_s,
v16qi, v8hi, v4si)
VAR3 (QUADOP_NONE_NONE_UNONE_IMM_PRED, vshlcq_m_carry_s, v16qi, v8hi, v4si)
VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_PRED, vshlcq_m_vec_u, v16qi, v8hi, v4si)
VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_PRED, vshlcq_m_carry_u, v16qi, v8hi, v4si)
-
-/* optabs without any suffixes. */
-VAR2 (TERNOP_NONE_NONE_NONE_NONE, vcmlaq_rot90, v8hf, v4sf)
-VAR2 (TERNOP_NONE_NONE_NONE_NONE, vcmlaq_rot270, v8hf, v4sf)
-VAR2 (TERNOP_NONE_NONE_NONE_NONE, vcmlaq_rot180, v8hf, v4sf)
-VAR2 (TERNOP_NONE_NONE_NONE_NONE, vcmlaq, v8hf, v4sf)
diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index 9f71404e26c..b13ff53d36f 100644
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -911,6 +911,10 @@
VCMULQ_M_F VCMULQ_ROT90_M_F VCMULQ_ROT180_M_F
VCMULQ_ROT270_M_F
])
+(define_int_iterator MVE_VCMLAQ_M [
+ VCMLAQ_M_F VCMLAQ_ROT90_M_F VCMLAQ_ROT180_M_F
VCMLAQ_ROT270_M_F
+ ])
+
(define_int_attr mve_insn [
(UNSPEC_VCADD90 "vcadd") (UNSPEC_VCADD270 "vcadd")
(UNSPEC_VCMUL "vcmul") (UNSPEC_VCMUL90 "vcmul")
(UNSPEC_VCMUL180 "vcmul") (UNSPEC_VCMUL270 "vcmul")
@@ -942,6 +946,7 @@
(VCLSQ_M_S "vcls")
(VCLSQ_S "vcls")
(VCLZQ_M_S "vclz") (VCLZQ_M_U "vclz")
+ (VCMLAQ_M_F "vcmla") (VCMLAQ_ROT90_M_F "vcmla")
(VCMLAQ_ROT180_M_F "vcmla") (VCMLAQ_ROT270_M_F "vcmla")
(VCMULQ_M_F "vcmul") (VCMULQ_ROT90_M_F "vcmul")
(VCMULQ_ROT180_M_F "vcmul") (VCMULQ_ROT270_M_F "vcmul")
(VCREATEQ_S "vcreate") (VCREATEQ_U "vcreate") (VCREATEQ_F
"vcreate")
(VDUPQ_M_N_S "vdup") (VDUPQ_M_N_U "vdup") (VDUPQ_M_N_F "vdup")
@@ -1204,6 +1209,7 @@
(VSUBQ_M_N_S "vsub") (VSUBQ_M_N_U "vsub") (VSUBQ_M_N_F "vsub")
(VSUBQ_M_S "vsub") (VSUBQ_M_U "vsub") (VSUBQ_M_F "vsub")
(VSUBQ_N_S "vsub") (VSUBQ_N_U "vsub") (VSUBQ_N_F "vsub")
+ (UNSPEC_VCMLA "vcmla") (UNSPEC_VCMLA90 "vcmla")
(UNSPEC_VCMLA180 "vcmla") (UNSPEC_VCMLA270 "vcmla")
])
(define_int_attr isu [
@@ -2198,7 +2204,12 @@
(VCMULQ_M_F "0")
(VCMULQ_ROT90_M_F "90")
(VCMULQ_ROT180_M_F "180")
- (VCMULQ_ROT270_M_F "270")])
+ (VCMULQ_ROT270_M_F "270")
+ (VCMLAQ_M_F "0")
+ (VCMLAQ_ROT90_M_F "90")
+ (VCMLAQ_ROT180_M_F "180")
+ (VCMLAQ_ROT270_M_F "270")
+ ])
;; The complex operations when performed on a real complex number require two
;; instructions to perform the operation. e.g. complex multiplication requires
@@ -2250,7 +2261,11 @@
(VCMULQ_M_F "")
(VCMULQ_ROT90_M_F "_rot90")
(VCMULQ_ROT180_M_F "_rot180")
- (VCMULQ_ROT270_M_F "_rot270")])
+ (VCMULQ_ROT270_M_F "_rot270")
+ (VCMLAQ_M_F "")
+ (VCMLAQ_ROT90_M_F "_rot90")
+ (VCMLAQ_ROT180_M_F "_rot180")
+ (VCMLAQ_ROT270_M_F "_rot270")])
(define_int_attr fcmac1 [(UNSPEC_VCMLA "a") (UNSPEC_VCMLA_CONJ "a")
(UNSPEC_VCMLA180 "s") (UNSPEC_VCMLA180_CONJ "s")])
diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index 0b99bf017dc..a2cbcff1a6f 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -2087,7 +2087,7 @@
;;
;; [vcmlaq, vcmlaq_rot90, vcmlaq_rot180, vcmlaq_rot270])
;;
-(define_insn "mve_vcmlaq<mve_rot><mode>"
+(define_insn "@mve_<mve_insn>q<mve_rot>_f<mode>"
[
(set (match_operand:MVE_0 0 "s_register_operand" "=w,w")
(plus:MVE_0 (match_operand:MVE_0 1 "reg_or_zero_operand" "Dz,0")
@@ -3180,70 +3180,22 @@
(set_attr "length""8")])
;;
-;; [vcmlaq_m_f])
-;;
-(define_insn "mve_vcmlaq_m_f<mode>"
- [
- (set (match_operand:MVE_0 0 "s_register_operand" "=w")
- (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
- (match_operand:MVE_0 2 "s_register_operand" "w")
- (match_operand:MVE_0 3 "s_register_operand" "w")
- (match_operand:<MVE_VPRED> 4 "vpr_register_operand"
"Up")]
- VCMLAQ_M_F))
- ]
- "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vpst\;vcmlat.f%#<V_sz_elem> %q0, %q2, %q3, #0"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
-;;
-;; [vcmlaq_rot180_m_f])
-;;
-(define_insn "mve_vcmlaq_rot180_m_f<mode>"
- [
- (set (match_operand:MVE_0 0 "s_register_operand" "=w")
- (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
- (match_operand:MVE_0 2 "s_register_operand" "w")
- (match_operand:MVE_0 3 "s_register_operand" "w")
- (match_operand:<MVE_VPRED> 4 "vpr_register_operand"
"Up")]
- VCMLAQ_ROT180_M_F))
- ]
- "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vpst\;vcmlat.f%#<V_sz_elem> %q0, %q2, %q3, #180"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
-;;
-;; [vcmlaq_rot270_m_f])
+;; [vcmlaq_m_f]
+;; [vcmlaq_rot90_m_f]
+;; [vcmlaq_rot180_m_f]
+;; [vcmlaq_rot270_m_f]
;;
-(define_insn "mve_vcmlaq_rot270_m_f<mode>"
- [
- (set (match_operand:MVE_0 0 "s_register_operand" "=w")
- (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
- (match_operand:MVE_0 2 "s_register_operand" "w")
- (match_operand:MVE_0 3 "s_register_operand" "w")
- (match_operand:<MVE_VPRED> 4 "vpr_register_operand"
"Up")]
- VCMLAQ_ROT270_M_F))
- ]
- "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vpst\;vcmlat.f%#<V_sz_elem> %q0, %q2, %q3, #270"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
-;;
-;; [vcmlaq_rot90_m_f])
-;;
-(define_insn "mve_vcmlaq_rot90_m_f<mode>"
+(define_insn "@mve_<mve_insn>q<mve_rot>_m_f<mode>"
[
(set (match_operand:MVE_0 0 "s_register_operand" "=w")
(unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
(match_operand:MVE_0 2 "s_register_operand" "w")
(match_operand:MVE_0 3 "s_register_operand" "w")
(match_operand:<MVE_VPRED> 4 "vpr_register_operand"
"Up")]
- VCMLAQ_ROT90_M_F))
+ MVE_VCMLAQ_M))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vpst\;vcmlat.f%#<V_sz_elem> %q0, %q2, %q3, #90"
+ "vpst\;<mve_insn>t.f%#<V_sz_elem>\t%q0, %q2, %q3, #<rot>"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
--
2.34.1
