redundant vsetvl in fixed-vlmax vectorized
codes[PR112326]
Hi Juzhe,
in principle this LGTM. It could use some function comments, though ;)
> +imm_avl_p (machine_mode mode)
> {
>poly_uint64 nuints = GET_MODE_NUNITS (mode);
>
>return nuints.is_constant ()
> -/* The vset
Hi Juzhe,
in principle this LGTM. It could use some function comments, though ;)
> +imm_avl_p (machine_mode mode)
> {
>poly_uint64 nuints = GET_MODE_NUNITS (mode);
>
>return nuints.is_constant ()
> -/* The vsetivli can only hold register 0~31. */
> -? (IN_RANGE
With compile option --param=riscv-autovec-preference=fixed-vlmax, we have
redundant AVL/VL toggling:
vsetvli a5,a3,e8,mf4,ta,ma -> should be changed into e32m1
vle32.v v1,0(a1)
vle32.v v2,0(a0)
vsetivlizero,4,e32,m1,ta,ma -> redundant
slli
