Committed, thanks Robin.
Pan
-Original Message-
From: Gcc-patches On Behalf
Of ???
Sent: Thursday, August 3, 2023 8:48 PM
To: rdapp.gcc ; gcc-patches
Cc: rdapp.gcc ; kito.cheng ;
kito.cheng ; Jeff Law
Subject: Re: Re: [PATCH V2] RISC-V: Support CALL conditional autovec patterns
5 "registers" when doing the merge by itself
>> and we only have 4?
Yes.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-08-03 19:03
To: Juzhe-Zhong; gcc-patches
CC: rdapp.gcc; kito.cheng; kito.cheng; jeffreyalaw
Subject: Re: [PATCH V2] RISC-V: Support CALL conditional autovec patte
Hi Juzhe,
I would find it a bit clearer if the prepare_ternay part were a
separate patch. As it's mostly mechanical replacements I don't
mind too much, though so it's LGTM from my side without that.
As to the lmul = 8 ICE, is the problem that the register allocator
would actually need 5
