Hi Robin and Juzhe,
I changed to use the most original method, please see V3 as below:
https://gcc.gnu.org/pipermail/gcc-patches/2023-September/631076.html
On 2023/9/20 17:51, Robin Dapp wrote:
So, IMHO, a complicate pattern which combine initial 0 value + extension +
reduction + vmerge may be
> So, IMHO, a complicate pattern which combine initial 0 value + extension +
> reduction + vmerge may be more reasonable.
If that works I would also prefer that.
Regards
Robin
more reasonable.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-09-20 17:14
To: Lehua Ding; gcc-patches
CC: rdapp.gcc; juzhe.zhong; kito.cheng; palmer; jeffreyalaw
Subject: Re: [PATCH V2] RISC-V: Support combine cond extend and reduce sum to
widen reduce sum
Hi Lehua,
I think this is bette
Hi Lehua,
I think this is better but still a bit weird :D Allowing constants
and forcing them into registers unconditionally is slightly dubious as
well, though. One thing that always sticks out is - how is 0 special?
Wouldn't we want other constants as well?
For reductions I think the vectoriz
V2 Change: Use new method to simple move const 0 to vector.
This patch support combining cond extend and reduce_sum to cond widen reduce_sum
like combine the following three insns:
(set (reg:RVVM2HI 149)
(const_vector:RVVM2HI repeat [
(const_int 0)
]))
(set (reg:RVVM2HI
