when prepare the v5.
Pan
-Original Message-
From: Robin Dapp
Sent: Wednesday, July 5, 2023 4:03 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: rdapp@gmail.com; juzhe.zh...@rivai.ai; jeffreya...@gmail.com; Wang,
Yanzhang ; kito.ch...@gmail.com
Subject: Re: [PATCH v4] RISC-V: Fix o
Hi Pan,
yes, the problem is fixed for me. Still some comments ;) Sorry
it took a while.
> 1. By default, the RVV floating-point will take dyn mode.
> 2. DYN is invalid in FRM register for RVV floating-point.
>
> When mode switching the function entry and exit, it will take DYN as
> the frm
-patches@gcc.gnu.org; juzhe.zh...@rivai.ai;
jeffreya...@gmail.com; Wang, Yanzhang
Subject: Re: [PATCH v4] RISC-V: Fix one bug for floating-point static frm
> LGTM, thanks :)
just a moment please, I still wanted to reply ;)
Regards
Robin
On Wed, Jul 5, 2023 at 3:12 PM Robin Dapp via Gcc-patches
wrote:
>
> > LGTM, thanks :)
>
> just a moment please, I still wanted to reply ;)
Sure :)
>
> Regards
> Robin
>
> LGTM, thanks :)
just a moment please, I still wanted to reply ;)
Regards
Robin
LGTM, thanks :)
On Wed, Jul 5, 2023 at 3:03 PM Pan Li via Gcc-patches
wrote:
>
> From: Pan Li
>
> This patch would like to fix one bug to align below items of spec.
>
> 1. By default, the RVV floating-point will take dyn mode.
> 2. DYN is invalid in FRM register for RVV floating-point.
>
> When
From: Pan Li
This patch would like to fix one bug to align below items of spec.
1. By default, the RVV floating-point will take dyn mode.
2. DYN is invalid in FRM register for RVV floating-point.
When mode switching the function entry and exit, it will take DYN as
the frm mode.
Signed-off-by:
