Re: [PATCH v5, rs6000] Change mode and insn condition for VSX scalar extract/insert instructions

2022-12-12 Thread Segher Boessenkool
Hi! On Fri, Dec 02, 2022 at 03:03:46PM +0800, HAO CHEN GUI wrote: > For scalar extract/insert instructions, exponent field can be stored in a > 32-bit register. So this patch changes the mode of exponent field from DI to > SI so that these instructions can be generated in a 32-bit environment.

Re: [PATCH v5, rs6000] Change mode and insn condition for VSX scalar extract/insert instructions

2022-12-12 Thread Kewen.Lin via Gcc-patches
on 2022/12/12 11:23, HAO CHEN GUI wrote: > Hi Kewen, > > 在 2022/12/8 16:47, Kewen.Lin 写道: >> This documentation update reminds me of that the current prototype of >> __ieee128 >> variant can be: >> >> unsigned int scalar_extract_exp (__ieee128 source); >> >> type unsigned int is enough for the

Re: [PATCH v5, rs6000] Change mode and insn condition for VSX scalar extract/insert instructions

2022-12-11 Thread HAO CHEN GUI via Gcc-patches
Hi Kewen, 在 2022/12/8 16:47, Kewen.Lin 写道: > This documentation update reminds me of that the current prototype of > __ieee128 > variant can be: > > unsigned int scalar_extract_exp (__ieee128 source); > > type unsigned int is enough for the exponent. It means xsxexpqp_ can > also > use

Re: [PATCH v5, rs6000] Change mode and insn condition for VSX scalar extract/insert instructions

2022-12-08 Thread Kewen.Lin via Gcc-patches
Hi Haochen, Thanks for the update, some comments are inlined as below. on 2022/12/2 15:03, HAO CHEN GUI wrote: > Hi, > For scalar extract/insert instructions, exponent field can be stored in a > 32-bit register. So this patch changes the mode of exponent field from DI to > SI so that these

[PATCH v5, rs6000] Change mode and insn condition for VSX scalar extract/insert instructions

2022-12-01 Thread HAO CHEN GUI via Gcc-patches
Hi, For scalar extract/insert instructions, exponent field can be stored in a 32-bit register. So this patch changes the mode of exponent field from DI to SI so that these instructions can be generated in a 32-bit environment. Also it removes TARGET_64BIT check for these instructions. The