This patch is to handle the differences in instruction generation
between Vector and XTheadVector. In this version, we only support
partial xtheadvector instructions that leverage directly from current
RVV1.0 with simple adding "th." prefix. For different name xtheadvector
instructions but share
atches"
抄 送:Jim Wilson; palmer;
andrew; "philipp.tomsich";
jeffreyalaw;
"christoph.muellner";
jinma; "cooper.qu"
主 题:Re: Re:[PATCH v5] RISC-V: Handle differences between XTheadvector and Vector
Why do you need to invade existing shapes ?
juzhe.zh...@
时间:2024年1月10日(星期三) 15:17
收件人:"cooper.joshua";
"gcc-patches"
抄 送:Jim Wilson; palmer;
andrew; "philipp.tomsich";
jeffreyalaw;
"christoph.muellner";
jinma; "cooper.qu"
主 题:Re: Re:[PATCH v5] RISC-V: Handle differences between XTheadvector and Vecto
pp.tomsich";
jeffreyalaw;
"christoph.muellner";
jinma; "cooper.qu"
主 题:Re: Re:[PATCH v5] RISC-V: Handle differences between XTheadvector and Vector
Why do you add theadvector shapes ? I think you can reuse the current existing
shapes.
+thead-vector-builtins.o: \+ $(srcdir)/con
ph.muellner";
jinma; "cooper.qu"
主 题:Re: Re:[PATCH v5] RISC-V: Handle differences between XTheadvector and Vector
Why do you add theadvector shapes ? I think you can reuse the current existing
shapes.
+thead-vector-builtins.o: \+ $(srcdir)/config/riscv/thead-vector-builtins.
muellner";
"cooper.joshua";
jinma; "cooper.qu"
主 题:Re: [PATCH v5] RISC-V: Handle differences between XTheadvector and Vector
Thanks for your patience.
LGTM from myside.
I think it's pretty clean now. I can image in the future when some day the
theadvector i
; cooper.qu
主题: Re:[PATCH v5] RISC-V: Handle differences between XTheadvector and Vector
Hi Juzhe,
Thank you for so many useful comments for this patch!
There are some more patches to support xtheadvector
special instrinsics as well as handle register overlap issue and
rewrite assembly output.
https
ot;type" "vicmp")
- (set_attr "mode" "")])
+ (set_attr "mode" "")
+ (set_attr "group_overlap" "th,th,th,th,none,none,none,none")])
You are add ", , , " which will be enabled when TARGET_VECTOR.
You shou
"cooper.joshua";
jinma; "cooper.qu"
主 题:Re: [PATCH v5] RISC-V: Handle differences between XTheadvector and Vector
Thanks for your patience.
LGTM from myside.
I think it's pretty clean now. I can image in the future when some day the
theadvector is no longer used, we c
;
christoph.muellner; juzhe.zhong; Jun Sha (Joshua); Jin Ma; Xianmiao Qu
Subject: [PATCH v5] RISC-V: Handle differences between XTheadvector and Vector
This patch is to handle the differences in instruction generation
between Vector and XTheadVector. In this version, we only support
partial xtheadvector
This patch is to handle the differences in instruction generation
between Vector and XTheadVector. In this version, we only support
partial xtheadvector instructions that leverage directly from current
RVV1.0 with simple adding "th." prefix. For different name xtheadvector
instructions but share
This patch is to handle the differences in instruction generation
between Vector and XTheadVector. In this version, we only support
partial xtheadvector instructions that leverage directly from current
RVV1.0 with simple adding "th." prefix. For different name xtheadvector
instructions but share
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