2011/12/15 Georg-Johann Lay a...@gjlay.de:
http://gcc.gnu.org/ml/gcc-patches/2011-12/msg00471.html
Georg-Johann Lay wrote:
Georg-Johann Lay wrote:
Denis Chertykov wrote:
The only question that remains is what the -m64 option should be like?
[ ] Omit it altogether
[ ] Leave it as is (off
http://gcc.gnu.org/ml/gcc-patches/2011-12/msg00471.html
Georg-Johann Lay wrote:
Georg-Johann Lay wrote:
Denis Chertykov wrote:
The only question that remains is what the -m64 option should be like?
[ ] Omit it altogether
[ ] Leave it as is (off per default)
[ ] Set it on per default
As
Georg-Johann Lay wrote:
Denis Chertykov wrote:
The only question that remains is what the -m64 option should be like?
[ ] Omit it altogether
[ ] Leave it as is (off per default)
[ ] Set it on per default
As soon as the direction is clear, I'll post a follow-up patch to
add the missing
Denis Chertykov wrote:
The only question that remains is what the -m64 option should be like?
[ ] Omit it altogether
[ ] Leave it as is (off per default)
[ ] Set it on per default
As soon as the direction is clear, I'll post a follow-up patch to
add the missing bits like, e.g.,
On 11/22/2011 01:15 AM, Georg-Johann Lay wrote:
ldi r30,lo8(1) ; 25*movqi/2[length = 1]
cp r10,r18 ; 26*cmpqi/2[length = 1]
brlo .L2 ; 27branch[length = 1]
ldi r30,lo8(0) ; 28*movqi/1[length = 1]
.L2:
add r11,r19 ;
Richard Henderson wrote:
On 11/21/2011 11:31 AM, Georg-Johann Lay wrote:
;; The caveat is that if there are insns for some mode, there must also be a
;; respective move insn that describes reloads. Therefore, this
;; implementation uses an accumulator-based model with two hard-coded,
;;
On 11/29/2011 10:11 AM, Georg-Johann Lay wrote:
The only question that remains is what the -m64 option should be like?
[ ] Omit it altogether
[ ] Leave it as is (off per default)
[ ] Set it on per default
As soon as the direction is clear, I'll post a follow-up patch to add the
missing
-Original Message-
From: Richard Henderson
Sent: Tuesday, November 29, 2011 11:30 AM
To: Georg-Johann Lay
Cc: gcc-patches@gcc.gnu.org; Denis Chertykov; Weddington, Eric;
Anatoly
Sokolov
Subject: Re: [Patch,AVR] Light-weight DImode implementation.
On 11/29/2011 10:11 AM, Georg
2011/11/30 Weddington, Eric eric.wedding...@atmel.com:
-Original Message-
From: Richard Henderson
Sent: Tuesday, November 29, 2011 11:30 AM
To: Georg-Johann Lay
Cc: gcc-patches@gcc.gnu.org; Denis Chertykov; Weddington, Eric;
Anatoly
Sokolov
Subject: Re: [Patch,AVR] Light-weight
This adds support for DImode insns that don't operate byte-wise like NEG,
COMPARE, PLUS, MINUS, ASHIFT, LSHIFTRT, ASHIFTRT, ROTATE.
The crucial point is that there is no movdi, with the following reasoning as
cited from new avr-dimode.md:
;; The purpose of this file is to provide a light-weight
On 11/21/2011 11:31 AM, Georg-Johann Lay wrote:
;; The caveat is that if there are insns for some mode, there must also be a
;; respective move insn that describes reloads. Therefore, this
;; implementation uses an accumulator-based model with two hard-coded,
;; accumulator-like registers
;;
Richard Henderson schrieb:
On 11/21/2011 11:31 AM, Georg-Johann Lay wrote:
;; The caveat is that if there are insns for some mode, there must also be a
;; respective move insn that describes reloads. Therefore, this
;; implementation uses an accumulator-based model with two hard-coded,
;;
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