[Patch AArch64] Improve SIMD concatenation with zeroes

Hi, In AArch64, SIMD instructions which only touch the bottom 64-bits of a vector register write zeroes to the upper 64-bits. In other words, we have a cheap way to implement a "zero extend" of a SIMD operation, and can generate efficient code for: [(set (match_operand 0)

Re: [Patch AArch64] Improve SIMD concatenation with zeroes

On 02/10/15 09:12, James Greenhalgh wrote: 2015-10-01 James Greenhalgh * config/aarch64/aarch64-simd.md (*aarch64_combinez): Add alternatives for reads from memory and moves from general-purpose registers. (*aarch64_combinez_be):