Hi aarch64 maintainers, Question 1: In __aarch64_sync_cache_range function, if CTR_EL0.IDC = 0b1, Shall the dc cvau and the dsb ish will be removed or only dc cvau will be removed?
- for (; address < (const char *) end; address += dcache_lsize) - asm volatile ("dc\tcvau, %0" - : - : "r" (address) - : "memory"); - - asm volatile ("dsb\tish" : : : "memory"); - Question 2: In __aarch64_sync_cache_range function, if CTR_EL0.DIC = 0b1, Shall the ic ivau, dsb ish and isb will be removed or only ic ivau and dsb ish will be removed, only isb left? - for (; address < (const char *) end; address += icache_lsize) - asm volatile ("ic\tivau, %0" - : - : "r" (address) - : "memory"); - - asm volatile ("dsb\tish; isb" : : : "memory"); Question 3: For ic ivau/iallu/ialluis, is there any other place that would use these instructions except self-modify scenario? Question 4: If CTR_EL0.IDC = 0b1 and CTR_EL0.DIC = 0b1, if software still execute ic ivau/iallu/ialluis instrution, is it ok for cpu to treat it as NOP? Cheers, Shaokun