As discussed at http://gcc.gnu.org/ml/gcc/2014-04/msg00241.html, this changes
the compiler to directly emit a 'casa' instruction with an appropriate ASI on
LEON3 and adds the -muser-mode switch.
Tested on SPARC/Solaris and LEON3, applied on mainline, 4.9 and 4.8 branches.
2014-04-28 Eric Botcazou <ebotca...@adacore.com>
* configure.ac: Tweak GAS check for LEON instructions on SPARC.
* configure: Regenerate.
* config/sparc/sparc.opt (muser-mode): New option.
* config/sparc/sync.md (atomic_compare_and_swap<mode>_1): Do not enable
for LEON3.
(atomic_compare_and_swap_leon3_1): New instruction for LEON3.
* doc/invoke.texi (SPARC options): Document -muser-mode.
--
Eric BotcazouIndex: doc/invoke.texi
===================================================================
--- doc/invoke.texi (revision 209819)
+++ doc/invoke.texi (working copy)
@@ -993,6 +993,7 @@ See RS/6000 and PowerPC Options.
-mhard-quad-float -msoft-quad-float @gol
-mstack-bias -mno-stack-bias @gol
-munaligned-doubles -mno-unaligned-doubles @gol
+-muser-mode -mno-user-mode @gol
-mv8plus -mno-v8plus -mvis -mno-vis @gol
-mvis2 -mno-vis2 -mvis3 -mno-vis3 @gol
-mcbcond -mno-cbcond @gol
@@ -20961,6 +20962,14 @@ Specifying this option avoids some rare
generated by other compilers. It is not the default because it results
in a performance loss, especially for floating-point code.
+@item -muser-mode
+@itemx -mno-user-mode
+@opindex muser-mode
+@opindex mno-user-mode
+Do not generate code that can only run in supervisor mode. This is relevant
+only for the @code{casa} instruction emitted for the LEON3 processor. The
+default is @option{-mno-user-mode}.
+
@item -mno-faster-structs
@itemx -mfaster-structs
@opindex mno-faster-structs
Index: configure.ac
===================================================================
--- configure.ac (revision 209819)
+++ configure.ac (working copy)
@@ -3647,7 +3647,7 @@ foo:
.align 4
smac %g2, %g3, %g1
umac %g2, %g3, %g1
- cas [[%g2]], %g3, %g1],,
+ casa [[%g2]] 0xb, %g3, %g1],,
[AC_DEFINE(HAVE_AS_LEON, 1,
[Define if your assembler supports LEON instructions.])])
;;
Index: config/sparc/sparc.opt
===================================================================
--- config/sparc/sparc.opt (revision 209819)
+++ config/sparc/sparc.opt (working copy)
@@ -113,6 +113,10 @@ mrelax
Target
Optimize tail call instructions in assembler and linker
+muser-mode
+Target Report Mask(USER_MODE)
+Do not generate code that can only run in supervisor mode
+
mcpu=
Target RejectNegative Joined Var(sparc_cpu_and_features) Enum(sparc_processor_type) Init(PROCESSOR_V7)
Use features of and schedule code for given CPU
Index: config/sparc/sync.md
===================================================================
--- config/sparc/sync.md (revision 209819)
+++ config/sparc/sync.md (working copy)
@@ -200,10 +200,27 @@ (define_insn "*atomic_compare_and_swap<m
[(match_operand:I48MODE 2 "register_operand" "r")
(match_operand:I48MODE 3 "register_operand" "0")]
UNSPECV_CAS))]
- "(TARGET_V9 || TARGET_LEON3) && (<MODE>mode != DImode || TARGET_ARCH64)"
+ "TARGET_V9 && (<MODE>mode != DImode || TARGET_ARCH64)"
"cas<modesuffix>\t%1, %2, %0"
[(set_attr "type" "multi")])
+(define_insn "*atomic_compare_and_swap_leon3_1"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (match_operand:SI 1 "mem_noofs_operand" "+w"))
+ (set (match_dup 1)
+ (unspec_volatile:SI
+ [(match_operand:SI 2 "register_operand" "r")
+ (match_operand:SI 3 "register_operand" "0")]
+ UNSPECV_CAS))]
+ "TARGET_LEON3"
+{
+ if (TARGET_USER_MODE)
+ return "casa\t%1 0xa, %2, %0"; /* ASI for user data space. */
+ else
+ return "casa\t%1 0xb, %2, %0"; /* ASI for supervisor data space. */
+}
+ [(set_attr "type" "multi")])
+
(define_insn "*atomic_compare_and_swapdi_v8plus"
[(set (match_operand:DI 0 "register_operand" "=h")
(match_operand:DI 1 "mem_noofs_operand" "+w"))
