On Mon, Apr 2, 2012 at 10:11 PM, Vladimir Makarov vmaka...@redhat.com wrote:
On 03/31/2012 01:38 AM, Ye Joey wrote:
Yes, if you mean spilling in LRA. But IRA can assign union of general and
SSE classes to a pseudo if it is profitable.
Any chance for IRA not to do so, saying by introducing an
On Wed, Mar 28, 2012 at 1:07 AM, Vladimir Makarov vmaka...@redhat.com wrote:
The following patch implements general spilling one class pseudos
into another class hard registers *instead of memory* in LRA.
Can't find the patch itself
- Joey
Vladimir Makarov vmaka...@redhat.com writes:
The following patch implements general spilling one class pseudos
into another class hard registers *instead of memory* in LRA.
Nice.
Just double checking: would it automatically disable itself with
-mno-sse2 for code that does not support the
On 03/28/2012 02:39 AM, Ye Joey wrote:
On Wed, Mar 28, 2012 at 1:07 AM, Vladimir Makarovvmaka...@redhat.com wrote:
The following patch implements general spilling one class pseudos
into another class hard registers *instead of memory* in LRA.
Can't find the patch itself
Sorry, my bad.
The following patch implements general spilling one class pseudos
into another class hard registers *instead of memory* in LRA.
Currently, the patch implements spilling of general reg pseudos into
SSE regs for Intel Core architecture as it is recommended by Intel
optimization guide. Such
The optimization might be useful for some other processors which
have direct move insns for the two considered classes and when IRA for
some reasons did not use the class union. At least I see
that we could try this for ARM (spilling general regs into VF regs)
and for extended powerpc
