[patch, rs6000] Implement optab_isinf for SFmode, DFmode and TFmode [PR97786]

[HAO CHEN GUI]

Hi,
  This patch implemented optab_isinf for SF/DF/TFmode by rs6000 test
data class instructions.

  Bootstrapped and tested on powerpc64-linux BE and LE with no
regressions. Is it OK for next stage 1?

Thanks
Gui Haochen

ChangeLog
rs6000: Implement optab_isinf for SFmode, DFmode and TFmode

gcc/
        PR target/97786
        * config/rs6000/vsx.md (isinf<mode>2): New expand for SFmode and
        DFmode.
        (isinf<mode>2): New expand for TFmode.

gcc/testsuite/
        PR target/97786
        * gcc.target/powerpc/pr97786-1.c: New test.
        * gcc.target/powerpc/pr97786-2.c: New test.

patch.diff
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index f135fa079bd..f0cc02f7e7b 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -5313,6 +5313,26 @@ (define_expand "xststdc<sd>p"
   operands[4] = CONST0_RTX (SImode);
 })

+(define_expand "isinf<mode>2"
+  [(use (match_operand:SI 0 "gpc_reg_operand"))
+   (use (match_operand:SFDF 1 "gpc_reg_operand"))]
+  "TARGET_HARD_FLOAT
+   && TARGET_P9_VECTOR"
+{
+  emit_insn (gen_xststdc<sd>p (operands[0], operands[1], GEN_INT (0x30)));
+  DONE;
+})
+
+(define_expand "isinf<mode>2"
+  [(use (match_operand:SI 0 "gpc_reg_operand"))
+   (use (match_operand:IEEE128 1 "gpc_reg_operand"))]
+  "TARGET_HARD_FLOAT
+   && TARGET_P9_VECTOR"
+{
+  emit_insn (gen_xststdcqp_<mode> (operands[0], operands[1], GEN_INT (0x30)));
+  DONE;
+})
+
 ;; The VSX Scalar Test Negative Quad-Precision
 (define_expand "xststdcnegqp_<mode>"
   [(set (match_dup 2)
diff --git a/gcc/testsuite/gcc.target/powerpc/pr97786-1.c 
b/gcc/testsuite/gcc.target/powerpc/pr97786-1.c
new file mode 100644
index 00000000000..1b1e6d642de
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr97786-1.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mdejagnu-cpu=power9 -mvsx" } */
+
+int test1 (double x)
+{
+  return __builtin_isinf (x);
+}
+
+int test2 (float x)
+{
+  return __builtin_isinf (x);
+}
+
+int test3 (float x)
+{
+  return __builtin_isinff (x);
+}
+
+/* { dg-final { scan-assembler-not {\mfcmpu\M} } } */
+/* { dg-final { scan-assembler-times {\mxststdc[sd]p\M} 3 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/pr97786-2.c 
b/gcc/testsuite/gcc.target/powerpc/pr97786-2.c
new file mode 100644
index 00000000000..de7f2d67c4b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr97786-2.c
@@ -0,0 +1,17 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-require-effective-target ppc_float128_sw } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mdejagnu-cpu=power9 -mvsx -mabi=ieeelongdouble 
-Wno-psabi" } */
+
+int test1 (long double x)
+{
+  return __builtin_isinf (x);
+}
+
+int test2 (long double x)
+{
+  return __builtin_isinfl (x);
+}
+
+/* { dg-final { scan-assembler-not {\mxscmpuqp\M} } } */
+/* { dg-final { scan-assembler-times {\mxststdcqp\M} 2 } } */