-Original Message-
From: Richard Sandiford [mailto:rdsandif...@googlemail.com]
Sent: Tuesday, April 15, 2014 4:32 PM
To: Moore, Catherine
Cc: Rozycki, Maciej; Matthew Fortune; gcc-patches@gcc.gnu.org
Subject: Re: [PATCH] [MIPS] Fix operands for microMIPS SW16, SH16 and
SB16
Subject: RE: [PATCH] [MIPS] Fix operands for microMIPS SW16, SH16 and
SB16
-Original Message-
From: Maciej W. Rozycki [mailto:ma...@codesourcery.com]
Sent: Tuesday, April 15, 2014 7:28 AM
To: Richard Sandiford
Cc: Matthew Fortune; Moore, Catherine; gcc-patches
Maciej W. Rozycki ma...@codesourcery.com writes:
On Sat, 12 Apr 2014, Richard Sandiford wrote:
I went ahead and applied the adjusted version of the patch to trunk
as below (because I wanted to add a testcase too).
I believe you need to adjust constraints to ensure constant 0 is known to
Richard Sandiford rdsandif...@googlemail.com writes:
Maciej W. Rozycki ma...@codesourcery.com writes:
On Sat, 12 Apr 2014, Richard Sandiford wrote:
I went ahead and applied the adjusted version of the patch to trunk
as below (because I wanted to add a testcase too).
I believe you
On Tue, 15 Apr 2014, Richard Sandiford wrote:
I believe you need to adjust constraints to ensure constant 0 is known to
produce a 16-bit instruction encoding where possible. Otherwise you'll
end up with suboptimal code when the instruction is in a branch delay
slot.
Yeah, it'd be
-Original Message-
From: Maciej W. Rozycki [mailto:ma...@codesourcery.com]
Sent: Tuesday, April 15, 2014 7:28 AM
To: Richard Sandiford
Cc: Matthew Fortune; Moore, Catherine; gcc-patches@gcc.gnu.org
Subject: Re: [PATCH] [MIPS] Fix operands for microMIPS SW16, SH16 and
SB16
-Original Message-
From: Moore, Catherine
Sent: Tuesday, April 15, 2014 8:49 AM
To: Rozycki, Maciej; Richard Sandiford
Cc: Matthew Fortune; gcc-patches@gcc.gnu.org; Moore, Catherine
Subject: RE: [PATCH] [MIPS] Fix operands for microMIPS SW16, SH16 and
SB16
-Original
for microMIPS SW16, SH16 and
SB16
-Original Message-
From: Maciej W. Rozycki [mailto:ma...@codesourcery.com]
Sent: Tuesday, April 15, 2014 7:28 AM
To: Richard Sandiford
Cc: Matthew Fortune; Moore, Catherine; gcc-patches@gcc.gnu.org
Subject: Re: [PATCH] [MIPS] Fix operands
-Original Message-
From: Richard Sandiford [mailto:rdsandif...@googlemail.com]
Sent: Saturday, April 12, 2014 6:41 AM
To: Matthew Fortune
Cc: Moore, Catherine; gcc-patches@gcc.gnu.org; rguent...@suse.de;
ja...@redhat.com
Subject: Re: [PATCH] [MIPS] Fix operands for microMIPS SW16
Moore, Catherine catherine_mo...@mentor.com writes:
Adding a new register class is definitely a bit invasive for this
stage of 4.9.
OTOH microMIPS is a new feature and it would be good to have it working in
4.9.0. Since the testing suggests that the patch really doesn't affect non-
microMIPS
On Sat, 12 Apr 2014, Richard Sandiford wrote:
I went ahead and applied the adjusted version of the patch to trunk
as below (because I wanted to add a testcase too).
I believe you need to adjust constraints to ensure constant 0 is known to
produce a 16-bit instruction encoding where possible.
Matthew Fortune matthew.fort...@imgtec.com writes:
Hi Catherine/Richard,
I think there may be some impact on register move costs by introducing
this class.
Yeah, I was worried about that too. I'm going to do some code comparison
tests for SE and MIPS16 to see what happens.
Is it worth
Richard Sandiford rdsandif...@googlemail.com writes:
Matthew Fortune matthew.fort...@imgtec.com writes:
Hi Catherine/Richard,
I think there may be some impact on register move costs by introducing
this class.
Yeah, I was worried about that too. I'm going to do some code comparison
tests
Hi Catherine/Richard,
I think there may be some impact on register move costs by introducing this
class. Is it worth having mips_canonicalize_move_class return M16_REGS for
M16_STORE_REGS to reduce the effect on costings? Given the extra register is
only $0 then this would seem mostly
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