Committed, thanks Kito.
Pan
-Original Message-
From: Kito Cheng
Sent: Tuesday, October 10, 2023 11:20 AM
To: Juzhe-Zhong
Cc: gcc-patches@gcc.gnu.org; kito.ch...@gmail.com; jeffreya...@gmail.com;
rdapp@gmail.com
Subject: Re: [PATCH] RISC-V: Add available vector size for RVV
LGTM
LGTM
On Mon, Oct 9, 2023 at 4:23 PM Juzhe-Zhong wrote:
>
> For RVV, we have VLS modes enable according to TARGET_MIN_VLEN
> from M1 to M8.
>
> For example, when TARGET_MIN_VLEN = 128 bits, we enable
> 128/256/512/1024 bits VLS modes.
>
> This patch fixes following FAIL:
> FAIL:
