RE: [PATCH] Remove AVX512_VP2INTERSECT from PTA_SAPPHIRERAPIDS

[Liu, Hongtao via Gcc-patches]

> -----Original Message-----
> From: Cui, Lili <lili....@intel.com>
> Sent: Wednesday, October 12, 2022 11:00 AM
> To: gcc-patches@gcc.gnu.org
> Cc: Liu, Hongtao <hongtao....@intel.com>; ubiz...@gmail.com; Lu, Hongjiu
> <hongjiu...@intel.com>
> Subject: [PATCH] Remove AVX512_VP2INTERSECT from PTA_SAPPHIRERAPIDS
> 
> Hi Hontao,
> 
> This patch is to remove AVX512_VP2INTERSECT from PTA_SAPPHIRERAPIDS.
> The new intel ISE removes AVX512_VP2INTERSECT from SAPPHIRERAPIDS,
> AVX512_VP2INTERSECT is only supportted in Tigerlake.
> 
> Hi Uros,
> 
> This patch is to remove AVX512_VP2INTERSECT from PTA_SAPPHIRERAPIDS.
> The new intel ISE removes AVX512_VP2INTERSECT from SAPPHIRERAPIDS,
> AVX512_VP2INTERSECT is only supportted in Tigerlake.
> 
> Bootstrap is ok, and no regressions for i386/x86-64 testsuite.
> 
> OK for master?
Yes, thanks.
> 
> 
> gcc/ChangeLog:
> 
>       * config/i386/driver-i386.cc (host_detect_local_cpu):
>       Move sapphirerapids out of AVX512_VP2INTERSECT.
>       * config/i386/i386.h: Remove AVX512_VP2INTERSECT from
> PTA_SAPPHIRERAPIDS
>       * doc/invoke.texi: Remove AVX512_VP2INTERSECT from
> SAPPHIRERAPIDS
> ---
>  gcc/config/i386/driver-i386.cc | 13 +++++--------
>  gcc/config/i386/i386.h         |  7 +++----
>  gcc/doc/invoke.texi            |  8 ++++----
>  3 files changed, 12 insertions(+), 16 deletions(-)
> 
> diff --git a/gcc/config/i386/driver-i386.cc b/gcc/config/i386/driver-i386.cc 
> index
> 3c702fdca33..ef567045c67 100644
> --- a/gcc/config/i386/driver-i386.cc
> +++ b/gcc/config/i386/driver-i386.cc
> @@ -589,15 +589,12 @@ const char *host_detect_local_cpu (int argc, const
> char **argv)
>             /* This is unknown family 0x6 CPU.  */
>             if (has_feature (FEATURE_AVX))
>               {
> +               /* Assume Tiger Lake */
>                 if (has_feature (FEATURE_AVX512VP2INTERSECT))
> -                 {
> -                   if (has_feature (FEATURE_TSXLDTRK))
> -                     /* Assume Sapphire Rapids.  */
> -                     cpu = "sapphirerapids";
> -                   else
> -                     /* Assume Tiger Lake */
> -                     cpu = "tigerlake";
> -                 }
> +                 cpu = "tigerlake";
> +               /* Assume Sapphire Rapids.  */
> +               else if (has_feature (FEATURE_TSXLDTRK))
> +                 cpu = "sapphirerapids";
>                 /* Assume Cooper Lake */
>                 else if (has_feature (FEATURE_AVX512BF16))
>                   cpu = "cooperlake";
> diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index
> 900a3bc3673..372a2cff8fe 100644
> --- a/gcc/config/i386/i386.h
> +++ b/gcc/config/i386/i386.h
> @@ -2326,10 +2326,9 @@ constexpr wide_int_bitmask PTA_ICELAKE_SERVER
> = PTA_ICELAKE_CLIENT  constexpr wide_int_bitmask PTA_TIGERLAKE =
> PTA_ICELAKE_CLIENT | PTA_MOVDIRI
>    | PTA_MOVDIR64B | PTA_CLWB | PTA_AVX512VP2INTERSECT | PTA_KL |
> PTA_WIDEKL;  constexpr wide_int_bitmask PTA_SAPPHIRERAPIDS =
> PTA_ICELAKE_SERVER | PTA_MOVDIRI
> -  | PTA_MOVDIR64B | PTA_AVX512VP2INTERSECT | PTA_ENQCMD |
> PTA_CLDEMOTE
> -  | PTA_PTWRITE | PTA_WAITPKG | PTA_SERIALIZE | PTA_TSXLDTRK |
> PTA_AMX_TILE
> -  | PTA_AMX_INT8 | PTA_AMX_BF16 | PTA_UINTR | PTA_AVXVNNI |
> PTA_AVX512FP16
> -  | PTA_AVX512BF16;
> +  | PTA_MOVDIR64B | PTA_ENQCMD | PTA_CLDEMOTE | PTA_PTWRITE |
> + PTA_WAITPKG  | PTA_SERIALIZE | PTA_TSXLDTRK | PTA_AMX_TILE |
> + PTA_AMX_INT8 | PTA_AMX_BF16  | PTA_UINTR | PTA_AVXVNNI |
> + PTA_AVX512FP16 | PTA_AVX512BF16;
>  constexpr wide_int_bitmask PTA_KNL = PTA_BROADWELL | PTA_AVX512PF
>    | PTA_AVX512ER | PTA_AVX512F | PTA_AVX512CD | PTA_PREFETCHWT1;
> constexpr wide_int_bitmask PTA_BONNELL = PTA_CORE2 | PTA_MOVBE; diff --
> git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index
> 271c8bb8468..a9ecc4426a4 100644
> --- a/gcc/doc/invoke.texi
> +++ b/gcc/doc/invoke.texi
> @@ -32057,11 +32057,11 @@ Intel sapphirerapids CPU with 64-bit extensions,
> MOVBE, MMX, SSE, SSE2, SSE3,  SSSE3, SSE4.1, SSE4.2, POPCNT, CX16, SAHF,
> FXSR, AVX, XSAVE, PCLMUL, FSGSBASE,  RDRND, F16C, AVX2, BMI, BMI2, LZCNT,
> FMA, MOVBE, HLE, RDSEED, ADCX, PREFETCHW,  AES, CLFLUSHOPT, XSAVEC,
> XSAVES, SGX, AVX512F, AVX512VL, AVX512BW, AVX512DQ, -AVX512CD, PKU,
> AVX512VBMI, AVX512IFMA, SHA, AVX512VNNI, GFNI, VAES, AVX512VBMI2
> +AVX512CD, PKU, AVX512VBMI, AVX512IFMA, SHA, AVX512VNNI, GFNI, VAES,
> +AVX512VBMI2,
>  VPCLMULQDQ, AVX512BITALG, RDPID, AVX512VPOPCNTDQ, PCONFIG,
> WBNOINVD, CLWB, -MOVDIRI, MOVDIR64B, AVX512VP2INTERSECT, ENQCMD,
> CLDEMOTE, PTWRITE, WAITPKG, -SERIALIZE, TSXLDTRK, UINTR, AMX-BF16,
> AMX-TILE, AMX-INT8, AVX-VNNI, AVX512FP16 -and AVX512BF16 instruction set
> support.
> +MOVDIRI, MOVDIR64B, ENQCMD, CLDEMOTE, PTWRITE, WAITPKG, SERIALIZE,
> +TSXLDTRK, UINTR, AMX-BF16, AMX-TILE, AMX-INT8, AVX-VNNI, AVX512FP16
> and
> +AVX512BF16 instruction set support.
> 
>  @item alderlake
>  Intel Alderlake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,
> SSSE3,
> --
> 2.17.1
> 
> Thanks,
> Lili.
> Thanks