Hi Srinath,
> -----Original Message-----
> From: Srinath Parvathaneni <srinath.parvathan...@arm.com>
> Sent: 18 March 2020 17:18
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov <kyrylo.tkac...@arm.com>
> Subject: [PATCH v2][ARM][GCC][1/5x]: MVE store intrinsics.
>
> Hello Kyrill,
>
> Following patch is the rebased version of v1.
> (version v1) https://gcc.gnu.org/pipermail/gcc-patches/2019-
> November/534334.html
>
> ####
>
> Hello,
>
> This patch supports the following MVE ACLE store intrinsics.
>
> vstrbq_scatter_offset_s8, vstrbq_scatter_offset_s32,
> vstrbq_scatter_offset_s16, vstrbq_scatter_offset_u8,
> vstrbq_scatter_offset_u32, vstrbq_scatter_offset_u16, vstrbq_s8, vstrbq_s32,
> vstrbq_s16, vstrbq_u8, vstrbq_u32, vstrbq_u16, vstrwq_scatter_base_s32,
> vstrwq_scatter_base_u32.
>
> Please refer to M-profile Vector Extension (MVE) intrinsics [1] for more
> details.
> [1] https://developer.arm.com/architectures/instruction-sets/simd-
> isas/helium/mve-intrinsics
>
> Regression tested on arm-none-eabi and found no regressions.
>
> Ok for trunk?
Thanks, I've pushed this patch into master.
Kyrill
>
> Thanks,
> Srinath.
>
> gcc/ChangeLog:
>
> 2019-11-01 Andre Vieira <andre.simoesdiasvie...@arm.com>
> Mihail Ionescu <mihail.ione...@arm.com>
> Srinath Parvathaneni <srinath.parvathan...@arm.com>
>
> * config/arm/arm-builtins.c (STRS_QUALIFIERS): Define builtin
> qualifier.
> (STRU_QUALIFIERS): Likewise.
> (STRSS_QUALIFIERS): Likewise.
> (STRSU_QUALIFIERS): Likewise.
> (STRSBS_QUALIFIERS): Likewise.
> (STRSBU_QUALIFIERS): Likewise.
> * config/arm/arm_mve.h (vstrbq_s8): Define macro.
> (vstrbq_u8): Likewise.
> (vstrbq_u16): Likewise.
> (vstrbq_scatter_offset_s8): Likewise.
> (vstrbq_scatter_offset_u8): Likewise.
> (vstrbq_scatter_offset_u16): Likewise.
> (vstrbq_s16): Likewise.
> (vstrbq_u32): Likewise.
> (vstrbq_scatter_offset_s16): Likewise.
> (vstrbq_scatter_offset_u32): Likewise.
> (vstrbq_s32): Likewise.
> (vstrbq_scatter_offset_s32): Likewise.
> (vstrwq_scatter_base_s32): Likewise.
> (vstrwq_scatter_base_u32): Likewise.
> (__arm_vstrbq_scatter_offset_s8): Define intrinsic.
> (__arm_vstrbq_scatter_offset_s32): Likewise.
> (__arm_vstrbq_scatter_offset_s16): Likewise.
> (__arm_vstrbq_scatter_offset_u8): Likewise.
> (__arm_vstrbq_scatter_offset_u32): Likewise.
> (__arm_vstrbq_scatter_offset_u16): Likewise.
> (__arm_vstrbq_s8): Likewise.
> (__arm_vstrbq_s32): Likewise.
> (__arm_vstrbq_s16): Likewise.
> (__arm_vstrbq_u8): Likewise.
> (__arm_vstrbq_u32): Likewise.
> (__arm_vstrbq_u16): Likewise.
> (__arm_vstrwq_scatter_base_s32): Likewise.
> (__arm_vstrwq_scatter_base_u32): Likewise.
> (vstrbq): Define polymorphic variant.
> (vstrbq_scatter_offset): Likewise.
> (vstrwq_scatter_base): Likewise.
> * config/arm/arm_mve_builtins.def (STRS_QUALIFIERS): Use builtin
> qualifier.
> (STRU_QUALIFIERS): Likewise.
> (STRSS_QUALIFIERS): Likewise.
> (STRSU_QUALIFIERS): Likewise.
> (STRSBS_QUALIFIERS): Likewise.
> (STRSBU_QUALIFIERS): Likewise.
> * config/arm/mve.md (MVE_B_ELEM): Define mode attribute
> iterator.
> (VSTRWSBQ): Define iterators.
> (VSTRBSOQ): Likewise.
> (VSTRBQ): Likewise.
> (mve_vstrbq_<supf><mode>): Define RTL pattern.
> (mve_vstrbq_scatter_offset_<supf><mode>): Likewise.
> (mve_vstrwq_scatter_base_<supf>v4si): Likewise.
>
> gcc/testsuite/ChangeLog:
>
> 2019-11-01 Andre Vieira <andre.simoesdiasvie...@arm.com>
> Mihail Ionescu <mihail.ione...@arm.com>
> Srinath Parvathaneni <srinath.parvathan...@arm.com>
>
> * gcc.target/arm/mve/intrinsics/vstrbq_s16.c: New test.
> * gcc.target/arm/mve/intrinsics/vstrbq_s32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrbq_s8.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s16.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s32.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s8.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u16.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u32.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u8.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrbq_u16.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrbq_u32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrbq_u8.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_s32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_u32.c: Likewise.
>
>
> ############### Attachment also inlined for ease of reply
> ###############
>
>
> diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c
> index
> 26f0379f62b95886414d2eb4d7c6a6c4fc235e60..b285f074285116ce621e324b
> 644d43efb6538b9d 100644
> --- a/gcc/config/arm/arm-builtins.c
> +++ b/gcc/config/arm/arm-builtins.c
> @@ -579,6 +579,39 @@
> arm_quadop_unone_unone_unone_none_unone_qualifiers[SIMD_MAX_BU
> ILTIN_ARGS]
> #define QUADOP_UNONE_UNONE_UNONE_NONE_UNONE_QUALIFIERS \
> (arm_quadop_unone_unone_unone_none_unone_qualifiers)
>
> +static enum arm_type_qualifiers
> +arm_strs_qualifiers[SIMD_MAX_BUILTIN_ARGS]
> + = { qualifier_void, qualifier_pointer, qualifier_none }; #define
> +STRS_QUALIFIERS (arm_strs_qualifiers)
> +
> +static enum arm_type_qualifiers
> +arm_stru_qualifiers[SIMD_MAX_BUILTIN_ARGS]
> + = { qualifier_void, qualifier_pointer, qualifier_unsigned }; #define
> +STRU_QUALIFIERS (arm_stru_qualifiers)
> +
> +static enum arm_type_qualifiers
> +arm_strss_qualifiers[SIMD_MAX_BUILTIN_ARGS]
> + = { qualifier_void, qualifier_pointer, qualifier_unsigned,
> + qualifier_none};
> +#define STRSS_QUALIFIERS (arm_strss_qualifiers)
> +
> +static enum arm_type_qualifiers
> +arm_strsu_qualifiers[SIMD_MAX_BUILTIN_ARGS]
> + = { qualifier_void, qualifier_pointer, qualifier_unsigned,
> + qualifier_unsigned};
> +#define STRSU_QUALIFIERS (arm_strsu_qualifiers)
> +
> +static enum arm_type_qualifiers
> +arm_strsbs_qualifiers[SIMD_MAX_BUILTIN_ARGS]
> + = { qualifier_void, qualifier_unsigned, qualifier_immediate,
> +qualifier_none}; #define STRSBS_QUALIFIERS (arm_strsbs_qualifiers)
> +
> +static enum arm_type_qualifiers
> +arm_strsbu_qualifiers[SIMD_MAX_BUILTIN_ARGS]
> + = { qualifier_void, qualifier_unsigned, qualifier_immediate,
> + qualifier_unsigned};
> +#define STRSBU_QUALIFIERS (arm_strsbu_qualifiers)
> +
> /* End of Qualifier for MVE builtins. */
>
> /* void ([T element type] *, T, immediate). */ diff --git
> a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index
> 4f8135d83f942e54b4db9dd43954af8bf027746e..019e907c6dc0b0572b7597f9
> e82b7ad8e6331bef 100644
> --- a/gcc/config/arm/arm_mve.h
> +++ b/gcc/config/arm/arm_mve.h
> @@ -1702,6 +1702,20 @@ typedef struct { uint8x16_t val[4]; } uint8x16x4_t;
> #define vsubq_m_f16(__inactive, __a, __b, __p)
> __arm_vsubq_m_f16(__inactive, __a, __b, __p) #define
> vsubq_m_n_f32(__inactive, __a, __b, __p)
> __arm_vsubq_m_n_f32(__inactive, __a, __b, __p) #define
> vsubq_m_n_f16(__inactive, __a, __b, __p)
> __arm_vsubq_m_n_f16(__inactive, __a, __b, __p)
> +#define vstrbq_s8( __addr, __value) __arm_vstrbq_s8( __addr, __value)
> +#define vstrbq_u8( __addr, __value) __arm_vstrbq_u8( __addr, __value)
> +#define vstrbq_u16( __addr, __value) __arm_vstrbq_u16( __addr, __value)
> +#define vstrbq_scatter_offset_s8( __base, __offset, __value)
> +__arm_vstrbq_scatter_offset_s8( __base, __offset, __value) #define
> +vstrbq_scatter_offset_u8( __base, __offset, __value)
> +__arm_vstrbq_scatter_offset_u8( __base, __offset, __value) #define
> +vstrbq_scatter_offset_u16( __base, __offset, __value)
> +__arm_vstrbq_scatter_offset_u16( __base, __offset, __value) #define
> +vstrbq_s16( __addr, __value) __arm_vstrbq_s16( __addr, __value) #define
> +vstrbq_u32( __addr, __value) __arm_vstrbq_u32( __addr, __value) #define
> +vstrbq_scatter_offset_s16( __base, __offset, __value)
> +__arm_vstrbq_scatter_offset_s16( __base, __offset, __value) #define
> +vstrbq_scatter_offset_u32( __base, __offset, __value)
> +__arm_vstrbq_scatter_offset_u32( __base, __offset, __value) #define
> +vstrbq_s32( __addr, __value) __arm_vstrbq_s32( __addr, __value) #define
> +vstrbq_scatter_offset_s32( __base, __offset, __value)
> +__arm_vstrbq_scatter_offset_s32( __base, __offset, __value) #define
> +vstrwq_scatter_base_s32(__addr, __offset, __value)
> +__arm_vstrwq_scatter_base_s32(__addr, __offset, __value) #define
> +vstrwq_scatter_base_u32(__addr, __offset, __value)
> +__arm_vstrwq_scatter_base_u32(__addr, __offset, __value)
> #endif
>
> __extension__ extern __inline void
> @@ -10995,6 +11009,103 @@ __arm_vshrntq_m_n_u16 (uint8x16_t __a,
> uint16x8_t __b, const int __imm, mve_pred
> return __builtin_mve_vshrntq_m_n_uv8hi (__a, __b, __imm, __p); }
>
> +__extension__ extern __inline void
> +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
> +__arm_vstrbq_scatter_offset_s8 (int8_t * __base, uint8x16_t __offset,
> +int8x16_t __value) {
> + __builtin_mve_vstrbq_scatter_offset_sv16qi ((__builtin_neon_qi *)
> +__base, __offset, __value); }
> +
> +__extension__ extern __inline void
> +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
> +__arm_vstrbq_scatter_offset_s32 (int8_t * __base, uint32x4_t __offset,
> +int32x4_t __value) {
> + __builtin_mve_vstrbq_scatter_offset_sv4si ((__builtin_neon_qi *)
> +__base, __offset, __value); }
> +
> +__extension__ extern __inline void
> +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
> +__arm_vstrbq_scatter_offset_s16 (int8_t * __base, uint16x8_t __offset,
> +int16x8_t __value) {
> + __builtin_mve_vstrbq_scatter_offset_sv8hi ((__builtin_neon_qi *)
> +__base, __offset, __value); }
> +
> +__extension__ extern __inline void
> +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
> +__arm_vstrbq_scatter_offset_u8 (uint8_t * __base, uint8x16_t __offset,
> +uint8x16_t __value) {
> + __builtin_mve_vstrbq_scatter_offset_uv16qi ((__builtin_neon_qi *)
> +__base, __offset, __value); }
> +
> +__extension__ extern __inline void
> +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
> +__arm_vstrbq_scatter_offset_u32 (uint8_t * __base, uint32x4_t __offset,
> +uint32x4_t __value) {
> + __builtin_mve_vstrbq_scatter_offset_uv4si ((__builtin_neon_qi *)
> +__base, __offset, __value); }
> +
> +__extension__ extern __inline void
> +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
> +__arm_vstrbq_scatter_offset_u16 (uint8_t * __base, uint16x8_t __offset,
> +uint16x8_t __value) {
> + __builtin_mve_vstrbq_scatter_offset_uv8hi ((__builtin_neon_qi *)
> +__base, __offset, __value); }
> +
> +__extension__ extern __inline void
> +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
> +__arm_vstrbq_s8 (int8_t * __addr, int8x16_t __value) {
> + __builtin_mve_vstrbq_sv16qi ((__builtin_neon_qi *) __addr, __value);
> +}
> +
> +__extension__ extern __inline void
> +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
> +__arm_vstrbq_s32 (int8_t * __addr, int32x4_t __value) {
> + __builtin_mve_vstrbq_sv4si ((__builtin_neon_qi *) __addr, __value); }
> +
> +__extension__ extern __inline void
> +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
> +__arm_vstrbq_s16 (int8_t * __addr, int16x8_t __value) {
> + __builtin_mve_vstrbq_sv8hi ((__builtin_neon_qi *) __addr, __value); }
> +
> +__extension__ extern __inline void
> +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
> +__arm_vstrbq_u8 (uint8_t * __addr, uint8x16_t __value) {
> + __builtin_mve_vstrbq_uv16qi ((__builtin_neon_qi *) __addr, __value);
> +}
> +
> +__extension__ extern __inline void
> +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
> +__arm_vstrbq_u32 (uint8_t * __addr, uint32x4_t __value) {
> + __builtin_mve_vstrbq_uv4si ((__builtin_neon_qi *) __addr, __value); }
> +
> +__extension__ extern __inline void
> +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
> +__arm_vstrbq_u16 (uint8_t * __addr, uint16x8_t __value) {
> + __builtin_mve_vstrbq_uv8hi ((__builtin_neon_qi *) __addr, __value); }
> +
> +__extension__ extern __inline void
> +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
> +__arm_vstrwq_scatter_base_s32 (uint32x4_t __addr, const int __offset,
> +int32x4_t __value) {
> + __builtin_mve_vstrwq_scatter_base_sv4si (__addr, __offset, __value);
> +}
> +
> +__extension__ extern __inline void
> +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
> +__arm_vstrwq_scatter_base_u32 (uint32x4_t __addr, const int __offset,
> +uint32x4_t __value) {
> + __builtin_mve_vstrwq_scatter_base_uv4si (__addr, __offset, __value);
> +}
> #if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */
>
> __extension__ extern __inline void
> @@ -17630,6 +17741,35 @@ extern void *__ARM_undef;
> int
> (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_m
> ve_type_uint16x8_t]: __arm_vmulq_m_u16 (__ARM_mve_coerce(__p0,
> uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce(__p2, uint16x8_t), p3), \
> int
> (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_m
> ve_type_uint32x4_t]: __arm_vmulq_m_u32 (__ARM_mve_coerce(__p0,
> uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce(__p2, uint32x4_t), p3));})
>
> +#define vstrbq(p0,p1) __arm_vstrbq(p0,p1) #define __arm_vstrbq(p0,p1)
> +({ __typeof(p0) __p0 = (p0); \
> + __typeof(p1) __p1 = (p1); \
> + _Generic( (int
> (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0,
> +\
> + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]:
> +__arm_vstrbq_s8 (__ARM_mve_coerce(__p0, int8_t *),
> +__ARM_mve_coerce(__p1, int8x16_t)), \
> + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int16x8_t]:
> +__arm_vstrbq_s16 (__ARM_mve_coerce(__p0, int8_t *),
> +__ARM_mve_coerce(__p1, int16x8_t)), \
> + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int32x4_t]:
> +__arm_vstrbq_s32 (__ARM_mve_coerce(__p0, int8_t *),
> +__ARM_mve_coerce(__p1, int32x4_t)), \
> + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]:
> +__arm_vstrbq_u8 (__ARM_mve_coerce(__p0, uint8_t *),
> +__ARM_mve_coerce(__p1, uint8x16_t)), \
> + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]:
> +__arm_vstrbq_u16 (__ARM_mve_coerce(__p0, uint8_t *),
> +__ARM_mve_coerce(__p1, uint16x8_t)), \
> + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]:
> +__arm_vstrbq_u32 (__ARM_mve_coerce(__p0, uint8_t *),
> +__ARM_mve_coerce(__p1, uint32x4_t)));})
> +
> +#define vstrbq_scatter_offset(p0,p1,p2)
> +__arm_vstrbq_scatter_offset(p0,p1,p2)
> +#define __arm_vstrbq_scatter_offset(p0,p1,p2) ({ __typeof(p0) __p0 =
> +(p0); \
> + __typeof(p1) __p1 = (p1); \
> + __typeof(p2) __p2 = (p2); \
> + _Generic( (int
> +(*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_ty
> peid(__
> +p2)])0, \
> + int
> +(*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t][__ARM_
> mve_typ
> +e_int8x16_t]: __arm_vstrbq_scatter_offset_s8 (__ARM_mve_coerce(__p0,
> +int8_t *), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2,
> +int8x16_t)), \
> + int
> +(*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_
> mve_typ
> +e_int16x8_t]: __arm_vstrbq_scatter_offset_s16 (__ARM_mve_coerce(__p0,
> +int8_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2,
> +int16x8_t)), \
> + int
> +(*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_
> mve_typ
> +e_int32x4_t]: __arm_vstrbq_scatter_offset_s32 (__ARM_mve_coerce(__p0,
> +int8_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2,
> +int32x4_t)), \
> + int
> +(*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t][__ARM_
> mve_ty
> +pe_uint8x16_t]: __arm_vstrbq_scatter_offset_u8
> (__ARM_mve_coerce(__p0,
> +uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t),
> __ARM_mve_coerce(__p2,
> +uint8x16_t)), \
> + int
> +(*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_
> mve_ty
> +pe_uint16x8_t]: __arm_vstrbq_scatter_offset_u16
> (__ARM_mve_coerce(__p0,
> +uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t),
> __ARM_mve_coerce(__p2,
> +uint16x8_t)), \
> + int
> +(*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_
> mve_ty
> +pe_uint32x4_t]: __arm_vstrbq_scatter_offset_u32
> (__ARM_mve_coerce(__p0,
> +uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t),
> __ARM_mve_coerce(__p2,
> +uint32x4_t)));})
> +
> +#define vstrwq_scatter_base(p0,p1,p2)
> +__arm_vstrwq_scatter_base(p0,p1,p2)
> +#define __arm_vstrwq_scatter_base(p0,p1,p2) ({ __typeof(p2) __p2 =
> +(p2); \
> + _Generic( (int (*)[__ARM_mve_typeid(__p2)])0, \
> + int (*)[__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_base_s32(p0,
> +p1, __ARM_mve_coerce(__p2, int32x4_t)), \
> + int (*)[__ARM_mve_type_uint32x4_t]:
> __arm_vstrwq_scatter_base_u32(p0,
> +p1, __ARM_mve_coerce(__p2, uint32x4_t)));})
> +
> #endif /* MVE Integer. */
>
> #define vqrdmlahq_m(p0,p1,p2,p3) __arm_vqrdmlahq_m(p0,p1,p2,p3) diff
> --git a/gcc/config/arm/arm_mve_builtins.def
> b/gcc/config/arm/arm_mve_builtins.def
> index
> b448889fc5f22e11975af97016d1908043254727..2c675240984ac3aa64faf6a91
> 99441c29528c704 100644
> --- a/gcc/config/arm/arm_mve_builtins.def
> +++ b/gcc/config/arm/arm_mve_builtins.def
> @@ -685,3 +685,9 @@ VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE,
> vandq_m_f, v8hf, v4sf)
> VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vaddq_m_n_f, v8hf,
> v4sf)
> VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vaddq_m_f, v8hf, v4sf)
> VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vabdq_m_f, v8hf, v4sf)
> +VAR3 (STRS, vstrbq_s, v16qi, v8hi, v4si)
> +VAR3 (STRU, vstrbq_u, v16qi, v8hi, v4si)
> +VAR3 (STRSS, vstrbq_scatter_offset_s, v16qi, v8hi, v4si)
> +VAR3 (STRSU, vstrbq_scatter_offset_u, v16qi, v8hi, v4si)
> +VAR1 (STRSBS, vstrwq_scatter_base_s, v4si)
> +VAR1 (STRSBU, vstrwq_scatter_base_u, v4si)
> diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index
> bf4eb5da11c27d8a10d7804ad28de9c40cb1878a..3d0a1725d416aa3e465de9
> 409977394d06c19897 100644
> --- a/gcc/config/arm/mve.md
> +++ b/gcc/config/arm/mve.md
> @@ -191,7 +191,8 @@
> VCMLAQ_ROT90_M_F VCMULQ_M_F
> VCMULQ_ROT180_M_F
> VCMULQ_ROT270_M_F VCMULQ_ROT90_M_F
> VFMAQ_M_F
> VFMAQ_M_N_F VFMASQ_M_N_F VFMSQ_M_F
> VMAXNMQ_M_F
> - VMINNMQ_M_F VSUBQ_M_F])
> + VMINNMQ_M_F VSUBQ_M_F VSTRWQSB_S
> VSTRWQSB_U
> + VSTRBQSO_S VSTRBQSO_U VSTRBQ_S VSTRBQ_U])
>
> (define_mode_attr MVE_CNVT [(V8HI "V8HF") (V4SI "V4SF")
> (V8HF "V8HI") (V4SF "V4SI")])
> @@ -342,7 +343,9 @@
> (VQRSHRNTQ_M_N_S "s") (VQRSHRNTQ_M_N_U "u")
> (VQRSHRNBQ_M_N_S "s") (VQRSHRNBQ_M_N_U "u")
> (VMLALDAVAXQ_P_S "s") (VMLALDAVAXQ_P_U "u")
> - (VMLALDAVAQ_P_S "s") (VMLALDAVAQ_P_U "u")])
> + (VMLALDAVAQ_P_S "s") (VMLALDAVAQ_P_U "u")
> + (VSTRWQSB_S "s") (VSTRWQSB_U "u") (VSTRBQSO_S "s")
> + (VSTRBQSO_U "u") (VSTRBQ_S "s") (VSTRBQ_U "u")])
>
> (define_int_attr mode1 [(VCTP8Q "8") (VCTP16Q "16") (VCTP32Q "32")
> (VCTP64Q "64") (VCTP8Q_M "8") (VCTP16Q_M "16")
> @@ -359,6 +362,7 @@
>
> (define_mode_attr MVE_constraint1 [ (V8HI "Ra") (V4SI "Rc")])
> (define_mode_attr MVE_pred1 [ (V8HI "mve_imm_7") (V4SI
> "mve_imm_15")])
> +(define_mode_attr MVE_B_ELEM [ (V16QI "V16QI") (V8HI "V8QI") (V4SI
> +"V4QI")])
>
> (define_int_iterator VCVTQ_TO_F [VCVTQ_TO_F_S VCVTQ_TO_F_U])
> (define_int_iterator VMVNQ_N [VMVNQ_N_U VMVNQ_N_S]) @@ -562,6
> +566,9 @@ (define_int_iterator VSHLLTQ_M_N [VSHLLTQ_M_N_U
> VSHLLTQ_M_N_S]) (define_int_iterator VSHRNBQ_M_N [VSHRNBQ_M_N_S
> VSHRNBQ_M_N_U]) (define_int_iterator VSHRNTQ_M_N [VSHRNTQ_M_N_S
> VSHRNTQ_M_N_U])
> +(define_int_iterator VSTRWSBQ [VSTRWQSB_S VSTRWQSB_U])
> +(define_int_iterator VSTRBSOQ [VSTRBQSO_S VSTRBQSO_U])
> +(define_int_iterator VSTRBQ [VSTRBQ_S VSTRBQ_U])
>
> (define_insn "*mve_mov<mode>"
> [(set (match_operand:MVE_types 0 "nonimmediate_operand"
> "=w,w,r,w,w,r,w,Us") @@ -7940,3 +7947,65 @@
> "vpst\;vsubt.f%#<V_sz_elem>\t%q0, %q2, %3"
> [(set_attr "type" "mve_move")
> (set_attr "length""8")])
> +
> +;;
> +;; [vstrbq_s vstrbq_u]
> +;;
> +(define_insn "mve_vstrbq_<supf><mode>"
> + [(set (match_operand:<MVE_B_ELEM> 0 "memory_operand" "=Us")
> + (unspec:<MVE_B_ELEM> [(match_operand:MVE_2 1
> "s_register_operand" "w")]
> + VSTRBQ))
> + ]
> + "TARGET_HAVE_MVE"
> +{
> + rtx ops[2];
> + int regno = REGNO (operands[1]);
> + ops[1] = gen_rtx_REG (TImode, regno);
> + ops[0] = operands[0];
> + output_asm_insn("vstrb.<V_sz_elem>\t%q1, %E0",ops);
> + return "";
> +}
> + [(set_attr "length" "4")])
> +
> +;;
> +;; [vstrbq_scatter_offset_s vstrbq_scatter_offset_u] ;; (define_insn
> +"mve_vstrbq_scatter_offset_<supf><mode>"
> + [(set (match_operand:<MVE_B_ELEM> 0 "memory_operand" "=Us")
> + (unspec:<MVE_B_ELEM>
> + [(match_operand:MVE_2 1 "s_register_operand" "w")
> + (match_operand:MVE_2 2 "s_register_operand" "w")]
> + VSTRBSOQ))
> + ]
> + "TARGET_HAVE_MVE"
> +{
> + rtx ops[3];
> + ops[0] = operands[0];
> + ops[1] = operands[1];
> + ops[2] = operands[2];
> + output_asm_insn("vstrb.<V_sz_elem>\t%q2, [%m0, %q1]",ops);
> + return "";
> +}
> + [(set_attr "length" "4")])
> +
> +;;
> +;; [vstrwq_scatter_base_s vstrwq_scatter_base_u] ;; (define_insn
> +"mve_vstrwq_scatter_base_<supf>v4si"
> + [(set (mem:BLK (scratch))
> + (unspec:BLK
> + [(match_operand:V4SI 0 "s_register_operand" "w")
> + (match_operand:SI 1 "immediate_operand" "i")
> + (match_operand:V4SI 2 "s_register_operand" "w")]
> + VSTRWSBQ))
> + ]
> + "TARGET_HAVE_MVE"
> +{
> + rtx ops[3];
> + ops[0] = operands[0];
> + ops[1] = operands[1];
> + ops[2] = operands[2];
> + output_asm_insn("vstrw.u32\t%q2, [%q0, %1]",ops);
> + return "";
> +}
> + [(set_attr "length" "4")])
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s16.c
> new file mode 100644
> index
> 0000000000000000000000000000000000000000..80fce9caebed26f782a10aa
> 2b2aa2094e02f0af2
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s16.c
> @@ -0,0 +1,22 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> +/* { dg-add-options arm_v8_1m_mve } */
> +/* { dg-additional-options "-O2" } */
> +
> +#include "arm_mve.h"
> +
> +void
> +foo (int8_t * addr, int16x8_t value)
> +{
> + vstrbq_s16 (addr, value);
> +}
> +
> +/* { dg-final { scan-assembler "vstrb.16" } } */
> +
> +void
> +foo1 (int8_t * addr, int16x8_t value)
> +{
> + vstrbq (addr, value);
> +}
> +
> +/* { dg-final { scan-assembler "vstrb.16" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s32.c
> new file mode 100644
> index
> 0000000000000000000000000000000000000000..ae3c89e0d4becc810a08f52
> c6349582f70334649
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s32.c
> @@ -0,0 +1,22 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> +/* { dg-add-options arm_v8_1m_mve } */
> +/* { dg-additional-options "-O2" } */
> +
> +#include "arm_mve.h"
> +
> +void
> +foo (int8_t * addr, int32x4_t value)
> +{
> + vstrbq_s32 (addr, value);
> +}
> +
> +/* { dg-final { scan-assembler "vstrb.32" } } */
> +
> +void
> +foo1 (int8_t * addr, int32x4_t value)
> +{
> + vstrbq (addr, value);
> +}
> +
> +/* { dg-final { scan-assembler "vstrb.32" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s8.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s8.c
> new file mode 100644
> index
> 0000000000000000000000000000000000000000..72a3673dd5f2707f2809ba2
> ae0eb55fbffecd69e
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s8.c
> @@ -0,0 +1,22 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> +/* { dg-add-options arm_v8_1m_mve } */
> +/* { dg-additional-options "-O2" } */
> +
> +#include "arm_mve.h"
> +
> +void
> +foo (int8_t * addr, int8x16_t value)
> +{
> + vstrbq_s8 (addr, value);
> +}
> +
> +/* { dg-final { scan-assembler "vstrb.8" } } */
> +
> +void
> +foo1 (int8_t * addr, int8x16_t value)
> +{
> + vstrbq (addr, value);
> +}
> +
> +/* { dg-final { scan-assembler "vstrb.8" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s16.c
> new file mode 100644
> index
> 0000000000000000000000000000000000000000..b4ad4f7e3a57473d9a99be6
> 6b3aaf803f76003e7
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_
> +++ s16.c
> @@ -0,0 +1,22 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> +/* { dg-add-options arm_v8_1m_mve } */
> +/* { dg-additional-options "-O2" } */
> +
> +#include "arm_mve.h"
> +
> +void
> +foo (int8_t * base, uint16x8_t offset, int16x8_t value) {
> + vstrbq_scatter_offset_s16 (base, offset, value); }
> +
> +/* { dg-final { scan-assembler "vstrb.16" } } */
> +
> +void
> +foo1 (int8_t * base, uint16x8_t offset, int16x8_t value) {
> + vstrbq_scatter_offset (base, offset, value); }
> +
> +/* { dg-final { scan-assembler "vstrb.16" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s32.c
> new file mode 100644
> index
> 0000000000000000000000000000000000000000..507eef819914bea10e6fd01
> 7d4cda902d568d767
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_
> +++ s32.c
> @@ -0,0 +1,22 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> +/* { dg-add-options arm_v8_1m_mve } */
> +/* { dg-additional-options "-O2" } */
> +
> +#include "arm_mve.h"
> +
> +void
> +foo (int8_t * base, uint32x4_t offset, int32x4_t value) {
> + vstrbq_scatter_offset_s32 (base, offset, value); }
> +
> +/* { dg-final { scan-assembler "vstrb.32" } } */
> +
> +void
> +foo1 (int8_t * base, uint32x4_t offset, int32x4_t value) {
> + vstrbq_scatter_offset (base, offset, value); }
> +
> +/* { dg-final { scan-assembler "vstrb.32" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s8.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s8.c
> new file mode 100644
> index
> 0000000000000000000000000000000000000000..f5467c3bc3d086dc7c88bbe
> 8073c65cdc3c718f9
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_
> +++ s8.c
> @@ -0,0 +1,22 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> +/* { dg-add-options arm_v8_1m_mve } */
> +/* { dg-additional-options "-O2" } */
> +
> +#include "arm_mve.h"
> +
> +void
> +foo (int8_t * base, uint8x16_t offset, int8x16_t value) {
> + vstrbq_scatter_offset_s8 (base, offset, value); }
> +
> +/* { dg-final { scan-assembler "vstrb.8" } } */
> +
> +void
> +foo1 (int8_t * base, uint8x16_t offset, int8x16_t value) {
> + vstrbq_scatter_offset (base, offset, value); }
> +
> +/* { dg-final { scan-assembler "vstrb.8" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u16.c
> new file mode 100644
> index
> 0000000000000000000000000000000000000000..cea669925436dc4a6867daf
> b47356642a7ee7238
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_
> +++ u16.c
> @@ -0,0 +1,22 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> +/* { dg-add-options arm_v8_1m_mve } */
> +/* { dg-additional-options "-O2" } */
> +
> +#include "arm_mve.h"
> +
> +void
> +foo (uint8_t * base, uint16x8_t offset, uint16x8_t value) {
> + vstrbq_scatter_offset_u16 (base, offset, value); }
> +
> +/* { dg-final { scan-assembler "vstrb.16" } } */
> +
> +void
> +foo1 (uint8_t * base, uint16x8_t offset, uint16x8_t value) {
> + vstrbq_scatter_offset (base, offset, value); }
> +
> +/* { dg-final { scan-assembler "vstrb.16" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u32.c
> new file mode 100644
> index
> 0000000000000000000000000000000000000000..6ad7ec6f738e95056fd947ff
> f979aafc2ecb7107
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_
> +++ u32.c
> @@ -0,0 +1,22 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> +/* { dg-add-options arm_v8_1m_mve } */
> +/* { dg-additional-options "-O2" } */
> +
> +#include "arm_mve.h"
> +
> +void
> +foo (uint8_t * base, uint32x4_t offset, uint32x4_t value) {
> + vstrbq_scatter_offset_u32 (base, offset, value); }
> +
> +/* { dg-final { scan-assembler "vstrb.32" } } */
> +
> +void
> +foo1 (uint8_t * base, uint32x4_t offset, uint32x4_t value) {
> + vstrbq_scatter_offset (base, offset, value); }
> +
> +/* { dg-final { scan-assembler "vstrb.32" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u8.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u8.c
> new file mode 100644
> index
> 0000000000000000000000000000000000000000..4122622142d4d600b9fe992
> f4d0936f1ac0c2f42
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_
> +++ u8.c
> @@ -0,0 +1,22 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> +/* { dg-add-options arm_v8_1m_mve } */
> +/* { dg-additional-options "-O2" } */
> +
> +#include "arm_mve.h"
> +
> +void
> +foo (uint8_t * base, uint8x16_t offset, uint8x16_t value) {
> + vstrbq_scatter_offset_u8 (base, offset, value); }
> +
> +/* { dg-final { scan-assembler "vstrb.8" } } */
> +
> +void
> +foo1 (uint8_t * base, uint8x16_t offset, uint8x16_t value) {
> + vstrbq_scatter_offset (base, offset, value); }
> +
> +/* { dg-final { scan-assembler "vstrb.8" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u16.c
> new file mode 100644
> index
> 0000000000000000000000000000000000000000..5871fbdbfa046e45cb47d32
> 11afc5df7d9c1855d
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u16.c
> @@ -0,0 +1,22 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> +/* { dg-add-options arm_v8_1m_mve } */
> +/* { dg-additional-options "-O2" } */
> +
> +#include "arm_mve.h"
> +
> +void
> +foo (uint8_t * addr, uint16x8_t value)
> +{
> + vstrbq_u16 (addr, value);
> +}
> +
> +/* { dg-final { scan-assembler "vstrb.16" } } */
> +
> +void
> +foo1 (uint8_t * addr, uint16x8_t value) {
> + vstrbq (addr, value);
> +}
> +
> +/* { dg-final { scan-assembler "vstrb.16" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u32.c
> new file mode 100644
> index
> 0000000000000000000000000000000000000000..31d6d86f9fd85854c4f2e333
> aef00a9d9d536d60
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u32.c
> @@ -0,0 +1,22 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> +/* { dg-add-options arm_v8_1m_mve } */
> +/* { dg-additional-options "-O2" } */
> +
> +#include "arm_mve.h"
> +
> +void
> +foo (uint8_t * addr, uint32x4_t value)
> +{
> + vstrbq_u32 (addr, value);
> +}
> +
> +/* { dg-final { scan-assembler "vstrb.32" } } */
> +
> +void
> +foo1 (uint8_t * addr, uint32x4_t value) {
> + vstrbq (addr, value);
> +}
> +
> +/* { dg-final { scan-assembler "vstrb.32" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u8.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u8.c
> new file mode 100644
> index
> 0000000000000000000000000000000000000000..7415b98e35e8c973b376598
> 226417942812bfd28
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u8.c
> @@ -0,0 +1,22 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> +/* { dg-add-options arm_v8_1m_mve } */
> +/* { dg-additional-options "-O2" } */
> +
> +#include "arm_mve.h"
> +
> +void
> +foo (uint8_t * addr, uint8x16_t value)
> +{
> + vstrbq_u8 (addr, value);
> +}
> +
> +/* { dg-final { scan-assembler "vstrb.8" } } */
> +
> +void
> +foo1 (uint8_t * addr, uint8x16_t value) {
> + vstrbq (addr, value);
> +}
> +
> +/* { dg-final { scan-assembler "vstrb.8" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_s32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_s32.c
> new file mode 100644
> index
> 0000000000000000000000000000000000000000..0fb6af6b7c96b325e1d7669
> 9f42e86f7280884ee
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_s3
> +++ 2.c
> @@ -0,0 +1,22 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> +/* { dg-add-options arm_v8_1m_mve } */
> +/* { dg-additional-options "-O2" } */
> +
> +#include "arm_mve.h"
> +
> +void
> +foo (uint32x4_t addr, int32x4_t value)
> +{
> + vstrwq_scatter_base_s32 (addr, 8, value); }
> +
> +/* { dg-final { scan-assembler "vstrw.u32" } } */
> +
> +void
> +foo1 (uint32x4_t addr, int32x4_t value) {
> + vstrwq_scatter_base (addr, 8, value); }
> +
> +/* { dg-final { scan-assembler "vstrw.u32" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_u32.c
> new file mode 100644
> index
> 0000000000000000000000000000000000000000..795c0b44e69ea9b969b1d4
> 385b6f43de5d4923f2
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_u3
> +++ 2.c
> @@ -0,0 +1,22 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> +/* { dg-add-options arm_v8_1m_mve } */
> +/* { dg-additional-options "-O2" } */
> +
> +#include "arm_mve.h"
> +
> +void
> +foo (uint32x4_t addr, uint32x4_t value) {
> + vstrwq_scatter_base_u32 (addr, 8, value); }
> +
> +/* { dg-final { scan-assembler "vstrw.u32" } } */
> +
> +void
> +foo1 (uint32x4_t addr, uint32x4_t value) {
> + vstrwq_scatter_base (addr, 8, value); }
> +
> +/* { dg-final { scan-assembler "vstrw.u32" } } */
