On 4 June 2015 at 14:36, Renlin Li renlin...@arm.com wrote:
Hi Marcus,
Sorry for the delay. I have come up with an updated patch. Two test cases
are added to check against the limit.
__ARM_ALIGN_MAX_STACK_PWR is hard coded into 16.
__ARM_ALIGN_MAX_PWR is hard coded into 28 which is the
On 29/04/15 11:58, Marcus Shawcroft wrote:
On 29 April 2015 at 01:24, Andrew Pinski pins...@gmail.com wrote:
On Tue, Dec 16, 2014 at 2:19 AM, Renlin Li renlin...@arm.com wrote:
Hi all,
This is a simple patch to add another two ACLE 2.0 predefined macros into
aarch64 backend.
They are
On 29 April 2015 at 01:24, Andrew Pinski pins...@gmail.com wrote:
On Tue, Dec 16, 2014 at 2:19 AM, Renlin Li renlin...@arm.com wrote:
Hi all,
This is a simple patch to add another two ACLE 2.0 predefined macros into
aarch64 backend.
They are __ARM_ALIGN_MAX_PWR and __ARM_ALIGN_MAX_STACK_PWR.
On Tue, Dec 16, 2014 at 2:19 AM, Renlin Li renlin...@arm.com wrote:
Hi all,
This is a simple patch to add another two ACLE 2.0 predefined macros into
aarch64 backend.
They are __ARM_ALIGN_MAX_PWR and __ARM_ALIGN_MAX_STACK_PWR. Currently, those
two values are hard-wired to 16.
The following
On 16 December 2014 at 10:19, Renlin Li renlin...@arm.com wrote:
2014-12-16 Renlin Li renlin...@arm.com
* config/aarch64/aarch64.h(TARGET_CPU_CPP_BUILTINS): Define
__ARM_ALIGN_MAX_PWR
and __ARM_ALIGN_MAX_STACK_PWR.
OK /Marcus
