On 2/6/24 6:14 AM, Robin Dapp wrote:
The root cause is this following RTL pattern, after fwprop1:
(insn 82 78 84 9 (set (reg:DI 230)
(sign_extend:DI (minus:SI (subreg/s/v:SI (reg:DI 150 [ niters.10 ]) 0)
(subreg:SI (reg:DI 221) 0 13 {subsi3_extended}
Subject: Re: [PATCH] RISC-V: Allow LICM hoist POLY_INT configuration code
sequence
> The root cause is this following RTL pattern, after fwprop1:
>
> (insn 82 78 84 9 (set (reg:DI 230)
> (sign_extend:DI (minus:SI (subreg/s/v:SI (reg:DI 150 [ niters.10 ]) 0)
>
> The root cause is this following RTL pattern, after fwprop1:
>
> (insn 82 78 84 9 (set (reg:DI 230)
> (sign_extend:DI (minus:SI (subreg/s/v:SI (reg:DI 150 [ niters.10 ]) 0)
> (subreg:SI (reg:DI 221) 0 13 {subsi3_extended}
> (expr_list:REG_EQUAL (sign_extend:DI
= XEXP (rhs, 0);
- else
+ //rhs = find_reg_equal_equiv_note (insn);
+ //if (rhs)
+ // rhs = XEXP (rhs, 0);
+ //else
rhs = SET_SRC (set);
Any thoughts ?
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2024-02-02 16:50
To: Juzhe-Zhong
CC: gcc-patches; kito.cheng; jeffreyalaw; rdapp.g
LGTM :)
On Thu, Feb 1, 2024 at 11:46 PM Juzhe-Zhong wrote:
>
> Realize in recent benchmark evaluation (coremark-pro zip-test):
>
> vid.v v2
> vmv.v.i v5,0
> .L9:
> vle16.v v3,0(a4)
> vrsub.vxv4,v2,a6 ---> LICM failed to hoist it outside the
> loop.
>
