Committed, thanks Kito.
Pan
-Original Message-
From: Kito Cheng
Sent: Wednesday, November 15, 2023 3:36 PM
To: juzhe.zh...@rivai.ai
Cc: Kito.cheng ; gcc-patches ;
jeffreyalaw ; Robin Dapp
Subject: Re: Re: [PATCH] RISC-V: Disallow RVV mode address for any
load/store[PR112535]
LGTM
@rivai.ai
>
>
> From: Kito Cheng
> Date: 2023-11-15 15:24
> To: Juzhe-Zhong
> CC: gcc-patches; kito.cheng; jeffreyalaw; rdapp.gcc
> Subject: Re: [PATCH] RISC-V: Disallow RVV mode address for any
> load/store[PR112535]
> Curious about the code gen impact, does it make IRA/LRA in
.
I think it should be COST MODEL issue.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-11-15 15:24
To: Juzhe-Zhong
CC: gcc-patches; kito.cheng; jeffreyalaw; rdapp.gcc
Subject: Re: [PATCH] RISC-V: Disallow RVV mode address for any
load/store[PR112535]
Curious about the code gen impact, does
Curious about the code gen impact, does it make IRA/LRA insert one more
move like (set (reg:DI) (subreg:DI (reg:V1DI 155) 0)) and then (set (mem:SI
(reg:DI)) (const_int 0))?
On Wed, Nov 15, 2023 at 3:15 PM Juzhe-Zhong wrote:
> This patch is quite obvious patch which disallow for load/store
