Re: [ssa-coalesce] Rename register_ssa_partition

On Mon, Nov 14, 2016 at 11:56 PM, kugan wrote: > Hi Richard, > > On 08/11/16 23:45, Richard Biener wrote: >> >> On Tue, Nov 8, 2016 at 3:32 AM, kugan >> wrote: >>> >>> Hi, >>> >>> In tree-ssa-coalesce, register_ssa_partition )

Re: [patch,libgfortran] PR51119 - MATMUL slow for large matrices

On Mon, Nov 14, 2016 at 11:13 PM, Jerry DeLisle wrote: > On 11/13/2016 11:03 PM, Thomas Koenig wrote: >> >> Hi Jerry, >> >> I think this >> >> + /* Parameter adjustments */ >> + c_dim1 = m; >> + c_offset = 1 + c_dim1; >> >> should be >> >> + /* Parameter

[PATCH] [ARC] New option handling, refurbish multilib support.

Please find attached the revised patch as requested. Ok to apply? Claudiu gcc/ 2016-05-09 Claudiu Zissulescu * config/arc/arc-arch.h: New file. * config/arc/arc-arches.def: Likewise. * config/arc/arc-cpus.def: Likewise. *

Re: [PATCH] PR77359: Properly align local variables in functions calling alloca.

On Fri, Nov 11, 2016 at 02:17:58PM -0600, Segher Boessenkool wrote: > On Fri, Nov 11, 2016 at 09:58:21AM +0100, Dominik Vogt wrote: > > > You say it needs more testing -- what testing? > > > > Regression testing on AIX (David has done this in reply to the > > original message), possibly also on

Re: [PATCH] Enable Intel AVX512_4FMAPS and AVX512_4VNNIW instructions

On Mon, Nov 14, 2016 at 7:28 PM, Andrew Senkevich wrote: > 2016-11-11 14:16 GMT+03:00 Uros Bizjak : >> The x86 part of the patch is OK with the above changes and additional >> target attribute test for flags2 ISA features.. > > Fixed according your

Re: Move misplaced assignment in num_sign_bit_copies1

> 2016-11-15 Richard Sandiford > Alan Hayward > David Sherwood > > * rtlanal.c (num_sign_bit_copies1): Calculate bitwidth after > handling VOIDmode. OK, thanks, but please change

Re: [v3 PATCH] Implement P0504R0 (Revisiting in-place tag types for any/optional/variant).

On 14 November 2016 at 22:51, Ville Voutilainen wrote: > On 14 November 2016 at 22:49, Ville Voutilainen > wrote: >> I needed to do some minor tweaks in >> testsuite/20_util/in_place/requirements.cc. I committed the attached >> after

Re: RFA (openmp): C++ PATCH to make some references TREE_CONSTANT

On Mon, Nov 14, 2016 at 11:53:55PM -0500, Jason Merrill wrote: > The standard says that references that refer to a constant address can > be used in a constant-expression, but we haven't allowed that. This > patch implements it, but without the parser.c hunk it broke > libgomp.c++/target-14.C.

[PATCH v2] df: Change defs in entry and uses in exit block during separate shrink-wrapping

So far all target implementations of the separate shrink-wrapping hooks use the DF LIVE info to figure out around which basic blocks the non- volatile registers need to be saved. This is done by looking at the IN+GEN+KILL sets of the basic blocks. However, that doesn't work for registers that DF

Re: [libstdc++, testsuite] Add dg-require-thread-fence

On 14 November 2016 at 21:31, Ramana Radhakrishnan wrote: > > On Mon, 14 Nov 2016 at 19:59, Christophe Lyon > wrote: >> >> On 14 November 2016 at 18:54, Mike Stump wrote: >> > On Oct 21, 2016, at 1:00 AM, Christophe

Re: [MIPS] Enable descriptors for nested functions in Ada

> Thanks for the patch. I'm a bit concerned about the interaction this > will have with microMIPS which can (albeit not implemented today) use > 2-byte alignment on function entry points. > > Is the solution for other targets to mandate 4-byte alignment when > using function descriptors? Yes,

Move misplaced assignment in num_sign_bit_copies1

[ This patch is part of the SVE series posted here: https://gcc.gnu.org/ml/gcc/2016-11/msg00030.html ] The old assignment to bitwidth was before we handled VOIDmode with: if (mode == VOIDmode) mode = GET_MODE (x); so when VOIDmode was specified we would always use: if (bitwidth <

Re: [patch] Disable LTO note about strict aliasing

> Can you verify that a TU compiled with -fstrict-aliasing will link as > if -fno-strict-aliasing if -fno-strict-aliasing is specified at link time? Yes, it does: eric@polaris:~/build/gcc/native> ~/install/gcc/bin/gcc -c t.c -O2 -flto eric@polaris:~/build/gcc/native> ~/install/gcc/bin/gcc -o t

Re: [PATCH] Fix find error in license boilerplate

On 15/11/16 14:36 +, Jonathan Wakely wrote: There are 138 test files that says "a moved_to of the GNU General Public License", presumably from a find& replace that then got copied to new tests. Fixed as obvious, as shown by this patch (the full patch is too big for the mailing list).

[committed] Add PR c++/71988 testcase

Hi! I've fixed this PR already in r240198 as part of the PR77482 fix, thus I've just added the testcase for it. Tested on x86_64-linux, committed to trunk as obvious. 2016-11-15 Jakub Jelinek PR c++/71988 * g++.dg/cpp0x/constexpr-71988.C: New test. ---

Re: [PATCH] libiberty: demangler crash with missing :? or fold expression component.

On Mon, Nov 14, 2016 at 3:39 PM, Mark Wielaard wrote: > When construction a :? or fold expression that requires a third > expression only the first and second were explicitly checked to > not be NULL. Since the third expression is also required in these > constructs it needs to be

Use MEM_SIZE rather than GET_MODE_SIZE in dce.c

Using MEM_SIZE is more general, since it copes with cases where targets are forced to use BLKmode references for whatever reason. Thanks, Richard [ This patch is part of the SVE series posted here: https://gcc.gnu.org/ml/gcc/2016-11/msg00030.html ] gcc/ 2016-11-15 Richard Sandiford

Re: Use MEM_SIZE rather than GET_MODE_SIZE in dce.c

On 11/15/2016 09:17 AM, Richard Sandiford wrote: Using MEM_SIZE is more general, since it copes with cases where targets are forced to use BLKmode references for whatever reason. Thanks, Richard [ This patch is part of the SVE series posted here:

Re: [PATCH][PR libgfortran/78314] Fix ieee_support_halting

Hi, > There seems to be a separate api for checking trapping support: > ieee_support_halting, but it only checked if the exception status > flags are available, so check trapping support too by enabling > and disabling traps. Thanks for the patch. I am worried about the unnecessary operations

Use df_read_modify_subreg_p in cprop.c

local_cprop_find_used_regs punted on all multiword registers, with the comment: /* Setting a subreg of a register larger than word_mode leaves the non-written words unchanged. */ But this only applies if the outer mode is smaller than the inner mode. If they're the same size

[PATCH] Add sem_item::m_hash_set (PR ipa/78309)

Hi. As seen on ppc64le during compilation of Firefox with LTO, combining inchash value with a pointer, enum value and an integer, one can eventually get zero value. Thus I decided to introduce a new flag that would distinguish between not set hash value and a valid and (possibly) zero value.

Re: [PATCH][PR libgfortran/78314] Fix ieee_support_halting

> disabling/enabling makes this api a lot heavier > than before, but trapping cannot be decided at > compile-time, although the result may be cached, > i think this should not be a frequent operation. > > otoh rereading my patch i think i fail to restore > the original exception state correctly.

Re: Add a load_extend_op wrapper

Jeff Law writes: > On 11/15/2016 05:42 AM, Richard Sandiford wrote: >> LOAD_EXTEND_OP only applies to scalar integer modes that are narrower >> than a word. However, callers weren't consistent about which of these >> checks they made beforehand, and also weren't consistent about

Add more subreg offset helpers

Provide versions of subreg_lowpart_offset and subreg_highpart_offset that work on mode sizes rather than modes. Also provide a routine that converts an lsb position to a subreg offset. The intent (in combination with later patches) is to move the handling of the BYTES_BIG_ENDIAN !=

Re: [PATCH][PR libgfortran/78314] Fix ieee_support_halting

On 15/11/16 16:22, FX wrote: >> There seems to be a separate api for checking trapping support: >> ieee_support_halting, but it only checked if the exception status >> flags are available, so check trapping support too by enabling >> and disabling traps. > > Thanks for the patch. > > I am

Re: [1/9][RFC][DWARF] Reserve three DW_OP numbers in vendor extension space

On 15/11/16 16:18, Jakub Jelinek wrote: On Tue, Nov 15, 2016 at 04:00:40PM +, Jiong Wang wrote: Takes one signed LEB128 offset and retrieves 8-byte contents from the address calculated by CFA plus this offset, the contents then authenticated as per A key for instruction pointer

Fix vec_cmp comparison mode

vec_cmps assign the result of a vector comparison to a mask. The optab was called with the destination having mode mask_mode but with the source (the comparison) having mode VOIDmode, which led to invalid rtl if the source operand was used directly. Tested on aarch64-linux-gnu and

Re: [C++ PATCH] SOme further g++.dg/cpp1z/decomp*.C tests

OK. On Tue, Nov 15, 2016 at 9:13 AM, Jakub Jelinek wrote: > Hi! > > This patch adds 3 new tests. Tested on x86_64-linux, ok for trunk? > > 2016-11-15 Jakub Jelinek > > * g++.dg/cpp1z/decomp13.C: New test. > * g++.dg/cpp1z/decomp14.C: New

Re: [PATCH,rs6000] Add built-in function support for Power9 byte instructions

On Tue, Nov 15, 2016 at 11:05:07AM -0700, Kelvin Nilsen wrote: > >>* config/rs6000/altivec.md (UNSPEC_CMPRB): New unspec value. > >>(UNSPEC_CMPRB2): New unspec value. > > > > I wonder if you really need both? The number of arguments will tell > > which is which, anyway? > > I appreciate

Re: [RFC][PATCH] Remove a bad use of SLOW_UNALIGNED_ACCESS

On 11/01/2016 03:39 PM, Wilco Dijkstra wrote: Jeff Law wrote: I think you'll need to look at bz61320 before this could go in. I had a look, but there is nothing there that is related - eventually a latent alignment bug was fixed in IVOpt. Excellent. Thanks for digging

Re: [PATCH/AARCH64] Have the verbose cost model output output be controllable

On Fri, Oct 7, 2016 at 1:01 AM, Kyrill Tkachov wrote: > Hi Andrew, > > > On 24/09/16 06:46, Andrew Pinski wrote: >> >> Hi, >>As reported in PR 61367, the aarch64 back-end is too verbose when it >> is dealing with the cost model. I tend to agree, no other back-end

Re: Rework subreg_get_info

Richard Sandiford writes: > This isn't intended to change the behaviour, just rewrite the > existing logic in a different (and hopefully clearer) way. > The new form -- particularly the part based on the "block" > concept -- is easier to convert to polynomial sizes. > >

Re: [PATCH][PPC] Fix ICE using power9 with soft-float

On 15/11/16 12:29, Segher Boessenkool wrote: The peepholes do not support it, or maybe the define_insns do not either. The machine of course will not care. Oh, OK, so probably the bug is not in the peephole at all, but in the define_insn, or lack thereof. More investigation required.

Re: [PATCH] Add map clauses to libgomp test device-3.f90

On Tue, Nov 15, 2016 at 07:52:56PM +0300, Alexander Monakov wrote: > On Mon, 14 Nov 2016, Alexander Monakov wrote: > > On Mon, 14 Nov 2016, Martin Jambor wrote: > > > > > Hi, > > > > > > yesterday I forgot to send out the following patch. The test > > >

Re: [PATCH] Add map clauses to libgomp test device-3.f90

On Tue, 15 Nov 2016, Alexander Monakov wrote: > Yep, I do see new test execution failures with both Intel MIC and PTX > offloading > on device-1.f90, device-3.f90 and target2.f90. Here's an actually-tested > patch > for the first two (on target2.f90 there's a different problem). And here's a

Re: Fix handling of unknown sizes in rtx_addr_can_trap_p

On 11/15/2016 09:21 AM, Richard Sandiford wrote: If the size passed in to rtx_addr_can_trap_p was zero, the frame handling would get the size from the mode instead. However, this too can be zero if the mode is BLKmode, i.e. if we have a BLKmode memory reference with no MEM_SIZE (which should be

Rework subreg_get_info

This isn't intended to change the behaviour, just rewrite the existing logic in a different (and hopefully clearer) way. The new form -- particularly the part based on the "block" concept -- is easier to convert to polynomial sizes. Tested on aarch64-linux-gnu and x86_64-linux-gnu. OK to

Re: [PATCH] libiberty: Fix some demangler crashes caused by reading past end of input.

On Mon, Nov 14, 2016 at 1:19 AM, Mark Wielaard wrote: > In various situations the cplus_demangle () function could read past the > end of input causing crashes. Add checks in various places to not advance > the demangle string location and fail early when end of string is reached.

Re: Move misplaced assignment in num_sign_bit_copies1

Eric Botcazou writes: >> 2016-11-15 Richard Sandiford >> Alan Hayward >> David Sherwood >> >> * rtlanal.c (num_sign_bit_copies1): Calculate bitwidth after >>

[hsa-branch] Replace all omp references of GPGPU with HSA grid

Hi, this is the last patch to the hsa branch before using it to create the merge-to-trunk patches. Basically, it replaces all references to "GPGPU gridification" in omp-low.c to "HSA gridification" as requested by Jakub at the Cauldron. Committed to the HSA branch, it is part of the posted

[hsa branch] Move hsa headers to plugin libgomp directory

Hi, this is one of the last two commits to the hsa branch I made while preparing the merge to trunk, it moves headers generated from HSA documentation to the plugin directory. Committed to the HSA branch, it is part of the posted patches merging it to trunk. Thanks, Martin 2016-11-12 Martin

Re: [patch,libgfortran] PR51119 - MATMUL slow for large matrices

On 11/15/2016 07:59 AM, Jerry DeLisle wrote: On 11/14/2016 11:22 PM, Thomas Koenig wrote: Hi Jerry, With these changes, OK for trunk? Just going over this with a fine comb... One thing just struck me: The loop variables should be index_type, so const index_type m = xcount, n =

Re: [PATCH] Add sem_item::m_hash_set (PR ipa/78309)

> Hi. > > As seen on ppc64le during compilation of Firefox with LTO, combining inchash > value > with a pointer, enum value and an integer, one can eventually get zero value. > Thus I decided to introduce a new flag that would distinguish between not set > hash value > and a valid and

Re: [PATCH] Add map clauses to libgomp test device-3.f90

On Mon, 14 Nov 2016, Alexander Monakov wrote: > On Mon, 14 Nov 2016, Martin Jambor wrote: > > > Hi, > > > > yesterday I forgot to send out the following patch. The test > > libgomp/testsuite/libgomp.fortran/examples-4/device-3.f90 was failing > > for me when I was testing the HSA branch merge

Fix instances of gen_rtx_REG (VOIDmode, ...)

Several definitions of INCOMING_RETURN_ADDR_RTX used gen_rtx_REG (VOIDmode, ...), which with later patches would trip an assert. This patch converts them to use Pmode instead. Tested on aarch64-linux-gnu and x86_64-linux-gnu. OK to install? Thanks, Richard [ This patch is part of the SVE

Re: [C++ PATCH] Add mangling for P0217R3 decompositions at namespace scope

OK. On Tue, Nov 15, 2016 at 9:12 AM, Jakub Jelinek wrote: > Hi! > > On the following testcase we ICE, because the underlying artificial decls > have NULL DECL_NAME (intentional), thus mangling is not able to figure out > what to do. This patch attempts to follow the >

Re: [PATCH,rs6000] Add built-in function support for Power9 byte instructions

Thank you very much for the prompt and thorough review. There are a few points below where I'd like to seek further clarification. On 11/15/2016 04:19 AM, Segher Boessenkool wrote: > Hi! > > On Mon, Nov 14, 2016 at 04:43:35PM -0700, Kelvin Nilsen wrote: >> * config/rs6000/altivec.md

Re: [PATCH] Add sem_item::m_hash_set (PR ipa/78309)

On 11/15/2016 09:43 AM, Martin Liška wrote: Hi. As seen on ppc64le during compilation of Firefox with LTO, combining inchash value with a pointer, enum value and an integer, one can eventually get zero value. Thus I decided to introduce a new flag that would distinguish between not set hash

Re: [1/9][RFC][DWARF] Reserve three DW_OP numbers in vendor extension space

On 15/11/16 16:18, Jakub Jelinek wrote: On Tue, Nov 15, 2016 at 04:00:40PM +, Jiong Wang wrote: Takes one signed LEB128 offset and retrieves 8-byte contents from the address calculated by CFA plus this offset, the contents then authenticated as per A key for instruction pointer

Re: [PATCH/AARCH64] Have the verbose cost model output output be controllable

On Tue, Nov 15, 2016 at 08:48:04AM -0800, Andrew Pinski wrote: > On Fri, Oct 7, 2016 at 1:01 AM, Kyrill Tkachov > wrote: > > Hi Andrew, > > > > > > On 24/09/16 06:46, Andrew Pinski wrote: > >> > >> Hi, > >>As reported in PR 61367, the aarch64 back-end is too

Re: [patch] remove more GCJ references

On 15.11.2016 16:52, Jeff Law wrote: > On 11/15/2016 03:55 AM, Matthias Klose wrote: >> This patch removes some references to gcj in the top level and config >> directories and in the gcc documentation. The change to the config directory >> requires regenerating aclocal.m4 and configure in each

Re: Fix instances of gen_rtx_REG (VOIDmode, ...)

On 11/15/2016 09:52 AM, Richard Sandiford wrote: Several definitions of INCOMING_RETURN_ADDR_RTX used gen_rtx_REG (VOIDmode, ...), which with later patches would trip an assert. This patch converts them to use Pmode instead. Tested on aarch64-linux-gnu and x86_64-linux-gnu. OK to install?

[PATCH] Add std::string constructor for substring of string_view (LWG 2742)

This is another issue resolution for C++17 features that was approved at the recent meeting. I think this resolution is wrong too, but in this case the fix is obvious so I've gone ahead and done it. * doc/xml/manual/intro.xml: Document LWG 2742 status. * doc/html/*: Regenerate.

Re: [PATCH] Enable Intel AVX512_4FMAPS and AVX512_4VNNIW instructions

On 11/15/2016 05:55 AM, Andrew Senkevich wrote: 2016-11-11 14:16 GMT+03:00 Uros Bizjak : --- a/gcc/genmodes.c +++ b/gcc/genmodes.c --- a/gcc/init-regs.c +++ b/gcc/init-regs.c --- a/gcc/machmode.h +++ b/gcc/machmode.h These are middle-end changes, you will need a separate

Re: [C++ PATCH] tweak PR77337 testcase

OK. On Tue, Nov 15, 2016 at 9:39 AM, Jakub Jelinek wrote: > On Thu, Nov 10, 2016 at 10:50:27PM +0100, Jakub Jelinek wrote: >> > + self(); // error: use of 'decltype(auto) >> > fix_type::operator()() [with Functor = >> > main()::]' before deduction of

[PATCH] Fix find error in license boilerplate

There are 138 test files that says "a moved_to of the GNU General Public License", presumably from a find& replace that then got copied to new tests. Fixed as obvious, as shown by this patch (the full patch is too big for the mailing list). commit 4ae2edc3c515f76e02712f744a0e3081de94be18

Re: Fix nb_iterations calculation in tree-vect-loop-manip.c

Richard Biener writes: > On Tue, Nov 15, 2016 at 1:44 PM, Richard Sandiford > wrote: >> We previously stored the number of loop iterations rather >> than the number of latch iterations. > > So ->nb_iterations was unused without SVE?

Re: Use simplify_gen_binary in canon_rtx

On 11/15/2016 09:07 AM, Richard Sandiford wrote: After simplifying the operands of a PLUS, canon_rtx checked only for cases in which one of the simplified operands was a constant, falling back to gen_rtx_PLUS otherwise. This left the PLUS in a non-canonical order if one of the simplified

RE: [PATCH] MIPS/GCC: Mark text contents as code or data

Maciej Rozycki writes: > gcc/ > * config/mips/mips-protos.h (mips_set_text_contents_type): New > prototype. > * config/mips/mips.h (ASM_OUTPUT_BEFORE_CASE_LABEL): New macro. > (ASM_OUTPUT_CASE_END): Likewise. > * config/mips/mips.c

Re: [1/9][RFC][DWARF] Reserve three DW_OP numbers in vendor extension space

On 11/11/16 19:38, Jakub Jelinek wrote: On Fri, Nov 11, 2016 at 06:21:48PM +, Jiong Wang wrote: This patch introduces three AARCH64 private DWARF operations in vendor extension space. DW_OP_AARCH64_pauth 0xea === Takes one unsigned LEB 128 Pointer Authentication Description. Bits [3:0]

Add a mem_alias_size helper class

alias.c encodes memory sizes as follows: size > 0: the exact size is known size == 0: the size isn't known size < 0: the exact size of the reference itself is known, but the address has been aligned via AND. In this case "-size" includes the size of the reference and the worst-case number

Re: Add a load_extend_op wrapper

On 11/15/2016 05:42 AM, Richard Sandiford wrote: LOAD_EXTEND_OP only applies to scalar integer modes that are narrower than a word. However, callers weren't consistent about which of these checks they made beforehand, and also weren't consistent about whether "smaller" was based on (bit)size or

[PATCH, Fortran, pr78356, v1] [7 Regression] [OOP] segfault allocating polymorphic variable with polymorphic component with allocatable component

Hi all, attached patch fixes the issue raised. The issue here was, that a copy of the base class was generated and its address passed to the _vptr->copy()-method, which then accessed memory, that was not present in the copy being an object of the base class. The patch fixes this by making sure

Re: [PATCH, vec-tails] Support loop epilogue vectorization

Hi All, Here is patch for non-masked epilogue vectoriziation. Bootstrap and regression testing did not show any new failures. Is it OK for trunk? Thanks. Changelog: 2016-11-15 Yuri Rumyantsev * params.def (PARAM_VECT_EPILOGUES_NOMASK): New. * tree-if-conv.c

RE: [PATCH,testsuite] MIPS: Downgrade from R6 to R5 to prevent redundant testing of branch-cost-1.c.

> From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches- > ow...@gcc.gnu.org] On Behalf Of Toma Tabacu > Sent: 15 November 2016 14:00 > To: gcc-patches@gcc.gnu.org > Cc: Matthew Fortune; catherine_mo...@mentor.com > Subject: [PATCH,testsuite] MIPS: Downgrade from R6 to R5 to prevent > redundant

RE: [PATCH] [ARC] New option handling, refurbish multilib support.

> This looks fine. Thanks for all your effort revising this patch. > > Andrew > Committed r242425. Thank you for your review, Claudiu

Re: Fix nb_iterations calculation in tree-vect-loop-manip.c

On Tue, Nov 15, 2016 at 1:44 PM, Richard Sandiford wrote: > We previously stored the number of loop iterations rather > than the number of latch iterations. So ->nb_iterations was unused without SVE? Otherwise can you please add a testcase? Thanks, Richard. > Tested

Re: [patch] remove more GCJ references

On 11/15/2016 03:55 AM, Matthias Klose wrote: This patch removes some references to gcj in the top level and config directories and in the gcc documentation. The change to the config directory requires regenerating aclocal.m4 and configure in each sub directory. Ok for the trunk? Matthias

Re: [patch,libgfortran] PR51119 - MATMUL slow for large matrices

On 11/14/2016 11:22 PM, Thomas Koenig wrote: Hi Jerry, With these changes, OK for trunk? Just going over this with a fine comb... One thing just struck me: The loop variables should be index_type, so const index_type m = xcount, n = ycount, k = count; [...] index_type a_dim1,

[C++ PATCH] tweak PR77337 testcase

On Thu, Nov 10, 2016 at 10:50:27PM +0100, Jakub Jelinek wrote: > > + self(); // error: use of 'decltype(auto) > > fix_type::operator()() [with Functor = main()::]' > > before deduction of 'auto' > > Wouldn't it be clearer to turn that // error: line into > // { dg-bogus

[PATCH] Fix PR78306

Appearantly for some unknown reason we refuse to inline anything into functions calling cilk_spawn. That breaks fortified headers and all other always-inline function calls (intrinsics come to my mind as well). Bootstrapped and tested on x86_64-unknown-linux-gnu, ok for trunk? Thanks,

Re: [patch] Disable LTO note about strict aliasing

On Tue, Nov 15, 2016 at 1:19 PM, Eric Botcazou wrote: >> Yes, I know -fno-strict-aliasing is globally set, but will all >> -fstrict-aliasing optimization attributes on functions be "overwritten"? >> That is, are you sure that when optimizing a function originally compiled

Use simplify_gen_binary in canon_rtx

After simplifying the operands of a PLUS, canon_rtx checked only for cases in which one of the simplified operands was a constant, falling back to gen_rtx_PLUS otherwise. This left the PLUS in a non-canonical order if one of the simplified operands was (plus (reg R1) (const_int X)); we'd end up

Tweak LRA handling of shared spill slots

The previous code processed the users of a stack slot in order of decreasing size and allocated the slot based on the first user. This seems a bit dangerous, since the ordering is based on the mode of the biggest reference while the allocation is based also on the size of the register itself

Optimise CONCAT handling in emit_group_load

The CONCAT handling in emit_group_load chooses between doing an extraction from a single component or forcing the whole thing to memory and extracting from there. The condition for the former (more efficient) option was: if ((bytepos == 0 && bytelen == slen0) || (bytepos

Re: RFA (openmp): C++ PATCH to make some references TREE_CONSTANT

On Tue, Nov 15, 2016 at 4:32 AM, Jakub Jelinek wrote: > So, is there a way to treat references the similarly? I.e. only "fold" > reference vars to what they refer (DECL_INITIAL) in constexpr.c evaluation, > or gimplification where a langhook or omp_notice_variable etc. has the

Re: Fix nb_iterations_estimate calculation in tree-vect-loop.c

On Tue, Nov 15, 2016 at 1:57 PM, Richard Sandiford wrote: > vect_transform_loop has to reduce three iteration counts by > the vectorisation factor: nb_iterations_upper_bound, > nb_iterations_likely_upper_bound and nb_iterations_estimate. > All three are latch execution

[PATCH][PR libgfortran/78314] Fix ieee_support_halting

When fpu trapping is enabled in libgfortran, the return value of feenableexcept is not checked. Glibc reports there if the operation was unsuccessful which happens if the target has no trapping support. There seems to be a separate api for checking trapping support: ieee_support_halting, but it

Re: [1/9][RFC][DWARF] Reserve three DW_OP numbers in vendor extension space

On Tue, Nov 15, 2016 at 04:00:40PM +, Jiong Wang wrote: > >> Takes one signed LEB128 offset and retrieves 8-byte contents from the > >> address > >> calculated by CFA plus this offset, the contents then authenticated as > >> per A > >> key for instruction pointer using current CFA as

Fix handling of unknown sizes in rtx_addr_can_trap_p

If the size passed in to rtx_addr_can_trap_p was zero, the frame handling would get the size from the mode instead. However, this too can be zero if the mode is BLKmode, i.e. if we have a BLKmode memory reference with no MEM_SIZE (which should be rare these days). This meant that the conditions

[PATCH] Constrain swap overload for std::optional (LWG 2748)

This implements the resolution to LWG 2748 which was approved the other day at the WG21 meeting. I think the resolution is wrong, because as the test shows it means that optional is swappable in some cases. I've raised that with the LWG and will probably create a new issue for it, but in the

RE: [PATCH 2/2] [ARC] Update target specific tests.

PING! Once the new options are in, we need also to update the tests. Andrew, please can you check it, Claudiu > -Original Message- > From: Claudiu Zissulescu > Sent: Monday, May 30, 2016 2:33 PM > To: gcc-patches@gcc.gnu.org > Cc: Claudiu Zissulescu ;

Re: [PATCH] Support -fsanitize=integer-arith-overflow even for vectors (PR sanitizer/77823)

On 11/15/2016 07:03 AM, Jakub Jelinek wrote: Hi! On Mon, Nov 14, 2016 at 10:58:51AM +0100, Jakub Jelinek wrote: Working virtually out of Samoa. The following patch is an attempt to handle -fsanitize=undefined for vectors. We already diagnose out of bounds accesses for vector subscripts, this

RE: [PATCH 2/2] [ARC] [libgcc] Fix defines

> Is there a reason that instruction should be uppercase? > > This otherwise looks fine to me. > Committed r242428. Thank you for your review, Claudiu

Re: Some backward threader refactoring

On 11/14/2016 02:39 AM, Jeff Law wrote: I was looking at the possibility of dropping threading from VRP1/VRP2 or DOM1/DOM2 in favor of the backwards threader -- the obvious idea being to recover some compile-time for gcc-7. Of the old-style threader passes (VRP1, VRP2, DOM1, DOM2), VRP2 is by

C++ PATCH for c++/78358 (decltype and decomposition)

OK, (hopefully) one more patch for decltype and C++17 decomposition declarations. I hadn't been thinking that "referenced type" meant to look through references in the tuple case, since other parts of [dcl.decomp] define "the referenced type" directly, but that does seem to be how it's used

Re: [PATCH] Enable Intel AVX512_4FMAPS and AVX512_4VNNIW instructions

2016-11-15 17:56 GMT+03:00 Jeff Law : > On 11/15/2016 05:55 AM, Andrew Senkevich wrote: >> >> 2016-11-11 14:16 GMT+03:00 Uros Bizjak : >>> >>> --- a/gcc/genmodes.c >>> +++ b/gcc/genmodes.c >>> --- a/gcc/init-regs.c >>> +++ b/gcc/init-regs.c >>> ---

Re: Optimise CONCAT handling in emit_group_load

> 2016-11-15 Richard Sandiford > Alan Hayward > David Sherwood > > * expr.c (emit_group_load_1): Tighten check for whether an > access involves only one operand of a CONCAT. Use

Re: [PATCH] fix PR68468

Hi, Jakub Jelinek wrote, > On Wed, Nov 09, 2016 at 04:08:39PM +0100, Bernd Schmidt wrote: > > On 11/05/2016 06:14 PM, Waldemar Brodkorb wrote: > > >Hi, > > > > > >the following patch fixes PR68468. > > >Patch is used for a while in Buildroot without issues. > > > > > >2016-11-05 Waldemar

[PATCH] Make std::tuple_size SFINAE-friendly (LWG 2770)

This is needed to avoid problems with the new structured bindings feature that landed in trunk yesterday. As part of this patch I'm removing the docs for the DR 2742 and 2748 changes that I added earlier today. The manual doesn't need to track changes against new features that only appear in

Re: [PATCH,rs6000] Add built-in function support for Power9 byte instructions

On Tue, Nov 15, 2016 at 12:16:19PM -0700, Kelvin Nilsen wrote: > The reason I am using SI mode is so that I don't have to disqualify the > use of these functions on a 32-bit big-endian configuration. > > Do you want me to switch to DI mode for all the operands? SI is fine, and can give slightly

Re: Fix handling of unknown sizes in rtx_addr_can_trap_p

Jeff Law writes: > On 11/15/2016 09:21 AM, Richard Sandiford wrote: >> If the size passed in to rtx_addr_can_trap_p was zero, the frame >> handling would get the size from the mode instead. However, this >> too can be zero if the mode is BLKmode, i.e. if we have a BLKmode >>

Re: Add a load_extend_op wrapper

> 2016-11-15 Richard Sandiford > Alan Hayward > David Sherwood > > * rtl.h (load_extend_op): Declare. > * rtlanal.c (load_extend_op): New function. I'd make it an inline function. --

Re: [PATCH,rs6000] Add built-in function support for Power9 byte instructions

> >> Thanks for catching this. I think I got endian confusion inside my head >> while I was writing the above. I will rewrite these comments, below also. > > Note the ISA calls the bits in 32-bit registers 32..63, so that 63 is > the rightmost bit in all registers. > True, but the ISA only

Re: [PATCH] Add std::string constructor for substring of string_view (LWG 2742)

On 15/11/16 14:33 +, Jonathan Wakely wrote: This is another issue resolution for C++17 features that was approved at the recent meeting. I think this resolution is wrong too, but in this case the fix is obvious so I've gone ahead and done it. * doc/xml/manual/intro.xml: Document LWG

[PATCH 0/9] RFC: Add optimization -foutline-msabi-xlougues (for Wine 64)

Due to differences between the 64-bit Microsoft and System V ABIs, any msabi function that calls a sysv function must consider RSI, RDI and XMM6-15 as clobbered. The result is that such functions are bloated with SSE saves/restores costing as much as 106 bytes each (up to 200-ish bytes per

[PATCH] Fix PR77848

Hi, https://gcc.gnu.org/bugzilla/show_bug.cgi?id=77848 identifies a situation where if-conversion causes degradation when the if-converted loop is not subsequently vectorized. The if-conversion pass does not have a cost model to avoid such degradations. However, it does have a capability to

Re: [patch] remove more GCJ references

On 15.11.2016 16:52, Jeff Law wrote: > On 11/15/2016 03:55 AM, Matthias Klose wrote: >> This patch removes some references to gcj in the top level and config >> directories and in the gcc documentation. The change to the config directory >> requires regenerating aclocal.m4 and configure in each

Re: Fix vec_cmp comparison mode

On 11/15/2016 09:49 AM, Richard Sandiford wrote: vec_cmps assign the result of a vector comparison to a mask. The optab was called with the destination having mode mask_mode but with the source (the comparison) having mode VOIDmode, which led to invalid rtl if the source operand was used

Re: [patch] remove more GCJ references

On 15.11.2016 21:41, Matthias Klose wrote: > On 15.11.2016 16:52, Jeff Law wrote: >> On 11/15/2016 03:55 AM, Matthias Klose wrote: >>> This patch removes some references to gcj in the top level and config >>> directories and in the gcc documentation. The change to the config >>> directory >>>

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