[PATCH][X86] Fix rounding pattern similar to PR73350

This is the same issue as PR73350 and PR80862 for disabling FP exceptions. gcc -O0 -mavx512f -mavx512er returns exception gcc -O2 -mavx512f -mavx512er returns nan For this code: #include #include #include #include #include int main(int argc, char *argv[]) { __m512 a =

[Patch AArch64] Stop generating BSL for simple integer code

Hi, In this testcase, all argument registers and the return register will be general purpose registers: long long foo (long long a, long long b, long long c) { return ((a ^ b) & c) ^ b; } However, due to the implementation of aarch64_simd_bsl_internal we'll match that pattern and

Merge from GCC trunk to gccgo branch

I've merged GCC trunk revision 249111 to the gccgo branch. Ian

Re: [Patch match.pd] Fold (A / (1 << B)) to (A >> B)

On Mon, 12 Jun 2017, James Greenhalgh wrote: > > Hi, > > As subject, for the testcase in the patch: > > unsigned long > f2 (unsigned long a, int b) > { > unsigned long x = 1UL << b; > return a / x; > } > > We currently generate: > > f2: > mov x2, 1 > lsl

Re: [PATCH][SPARC] PR target/80968 Prevent stack loads in return delay slot.

From: Eric Botcazou Date: Mon, 12 Jun 2017 11:27:10 +0200 >> I do not see a direct gen_return happening in function.c in the gcc-7 >> branch. >> >> Is it somewhere else? > > There is a call from force_nonfallthru_and_redirect in cfgrtl.c AFAICS. > > So the code

Re: [Mechanical Patch ARM/AArch64 1/2] Rename load/store scheduling types to encode data size

On 12/06/17 14:53, James Greenhalgh wrote: Hi, In the AArch64 backend and scheduling models there is some confusion as to what the load1/load2 etc. scheduling types refer to. This leads to us using load1/load2 in two contexts - for a variety of 32-bit, 64-bit and 128-bit loads in AArch32 and

Output cgraph profile inconsistencies

Hi, this patch adds code to output profile instantieis in callgraph. Bootstrapped/regtested x86_64-linux, comitted. Honza Index: cgraph.c === --- cgraph.c(revision 249112) +++ cgraph.c(working copy) @@ -2094,7 +2094,7 @@

Re: [PATCH 00/30] [ARM] Reworking the -mcpu, -march and -mfpu options

On 12/06/17 12:49, Christophe Lyon wrote: > On 10 June 2017 at 01:27, Richard Earnshaw (lists) > wrote: >> On 09/06/17 23:45, Christophe Lyon wrote: >>> Hi Richard, >>> >>> >>> On 9 June 2017 at 14:53, Richard Earnshaw wrote: During

Re: [PATCH, testsuite] Add effective target stack_size

Hi Tom, On 9 June 2017 at 17:25, Mike Stump wrote: > On Jun 9, 2017, at 7:24 AM, Tom de Vries wrote: >> this patch adds effective target stack_size. > >> OK for trunk if x86_64 and nvptx testing succeeds? > > Ok. > > The only last issue in this

[PATCH] Fix PR81065

I am re-testing the following patch to fix PR81065 with the fold_addr_of_array_ref_difference hunk added which was the only case causing the gcc_unreachable to trigger in a all languages bootstrap and regtest on x86_64-unknown-linux-gnu. The patch to commit will omit this case completely.

Re: [PATCH][X86] Fix rounding pattern similar to PR73350

On Mon, Jun 12, 2017 at 6:21 AM, Koval, Julia wrote: > This is the same issue as PR73350 and PR80862 for disabling FP exceptions. > > gcc -O0 -mavx512f -mavx512er returns exception > gcc -O2 -mavx512f -mavx512er returns nan > > For this code: > > #include > #include >

[Patch ARM] Fix PR71778

Hi, PR71778 is an ICE when you pass a non-constant argument to an intrinsic which requires a constant. This ICE was introduced after we rewrote some of the builtin handling for Neon intrinsics, the issue is that after throwing an error in arm_expand_builtin_args, we return const0_rtx to

[GCC][PATCH][AARCH64][Committed] Fix failing lrint inline tests on bare-metal.

Hi All, The tests introduced for lrint in r249064 are failing on aarch64 bare metal because it's using different registers. This patch generalizes the regexpr for the result so that it works both for bare metal and linux. regtested on aarch64-none-linux-gnu and aarch64-none-elf Committed as

[GCC][PATCH][ARM][Committed] Disable sdiv_1 test on softfloat targets.

Hi All, I committed this as r249122 under the GCC obvious rule. This fixes the failing test gcc.target/arm/sdiv_costs_1.c on soft float targets by disabling it on those targets since the div calls aren't expanded. gcc/testsuite/ 2017-06-12 Tamar Christina *

[Patch match.pd] Fold (A / (1 << B)) to (A >> B)

Hi, As subject, for the testcase in the patch: unsigned long f2 (unsigned long a, int b) { unsigned long x = 1UL << b; return a / x; } We currently generate: f2: mov x2, 1 lsl x1, x2, x1 udivx0, x0, x1 ret Which could instead be

Re: Mark abort, trap, unreachable and C++ EH and terminations as cold

> On 06/09/2017 12:53 PM, Jan Hubicka wrote: > >Hi, > >this patch marks the obvious candidates for cold attribute and enables > >cold auto-detection on some common coding patterns. > > > * class.c (build_vtbl_initializer): Mark dvirt_fn as cold. > > * decl.c (cxx_init_decl_processing,

Re: [PATCH][GCC][AArch64] Inline calls to lrint when possible

Hi Christophe, Thanks, I've committed a fix to the testcase. Tamar From: Christophe Lyon Sent: Monday, June 12, 2017 1:10:38 PM To: Tamar Christina Cc: GCC Patches; nd; Richard Earnshaw; Marcus Shawcroft Subject: Re:

Re: [PATCH, testsuite] Add effective target stack_size

On 06/12/2017 02:28 PM, Christophe Lyon wrote: Hi Tom, On 9 June 2017 at 17:25, Mike Stump wrote: On Jun 9, 2017, at 7:24 AM, Tom de Vries wrote: this patch adds effective target stack_size. OK for trunk if x86_64 and nvptx testing succeeds?

Re: [GCC][PATCH][ARM][Committed] Disable sdiv_1 test on softfloat targets.

Committed a less restrictive form in r249125 which now just requires arm_v8_vfp_ok gcc/testsuite/ 2017-06-12 Tamar Christina * gcc.target/arm/sdiv_costs_1.c: Require arm_v8_vfp_ok. Thanks, Tamar From:

[Mechanical Patch ARM/AArch64 1/2] Rename load/store scheduling types to encode data size

Hi, In the AArch64 backend and scheduling models there is some confusion as to what the load1/load2 etc. scheduling types refer to. This leads to us using load1/load2 in two contexts - for a variety of 32-bit, 64-bit and 128-bit loads in AArch32 and 128-bit loads in AArch64. That leads to an

[Patch AArch64 2/2] Fix memory sizes to load/store patterns

Hi, There seems to be a partial misconception in the AArch64 backend that load1/load2 referred to the number of registers to load, rather than the number of words to load. This patch fixes that using the new "number of byte" types added in the previous patch. That means using the load_16 and

[PATCH][aarch64] Enable ifunc resolver attribute by default

I recently noticed that the GCC 'resolver' attribute used for ifunc's is not on by default for aarch64 even though all the infrastructure to support it is in place. I made memcpy an ifunc on aarch64 in glibc and am looking at possibly using it for libatomic too. For this reason I would like to

[PATCH][AArch64] Improve Cortex-A53 FP scheduler

The Cortex-A53 scheduler model of FMAC bypass is not quite right for FMAC to FMAC forwarding. Experiments also show the latencies of FP operations are too high as well. Rather than adding more bypasses, adjust the latencies of FP instructions to get a better schedule on average. As a result

[Patch AArch64] Stop generating BSL for simple integer code

[Sorry for the re-send. I spotted that the attributes were not right for the new pattern I was adding. The change between this and the first version was: + [(set_attr "type" "neon_bsl,neon_bsl,neon_bsl,multiple") + (set_attr "length" "4,4,4,12")] ] --- Hi, In this testcase, all

[PATCH GCC][13/13]Distribute loop with loop versioning under runtime alias check

Hi, This is the main patch rewriting loop distribution in order to handle hmmer. It improves loop distribution by versioning loop under runtime alias check conditions. As described in comments, the patch basically implements distribution in the following steps: 1) Seed partitions with

[PATCH GCC][12/13]Workaround reduction statements for distribution

Hi, For now, loop distribution handles variables used outside of loop as reduction. This is inaccurate because all partitions contain statement defining induction vars. Ideally we should factor out scev-propagation as a standalone interface which can be called when necessary. Before that, this

[PATCH GCC][11/13]Annotate partition by its parallelism execution type

Hi, This patch checks and records if partition can be executed in parallel by looking if there exists data dependence cycles. The information is needed for distribution because the idea is to distribute parallel type partitions away from sequential ones. I believe current distribution doesn't

[PATCH GCC][08/13]Refactoring structure partition for distribution

Hi, This patch refactors struct partition for later distribution. It records bitmap of data references in struct partition rather than vertices' data in partition dependence graph. It simplifies code as well as enables following rewriting. Bootstrap and test on x86_64 and AArch64. Is it OK?

[PATCH GCC][10/13]Compute and cache data dependence relation

Hi, This patch computes and caches data dependence relation in a hash table so that it can be queried multiple times later for partition dependence check. Bootstrap and test on x86_64 and AArch64. Is it OK? Thanks, bin 2017-06-07 Bin Cheng *

[PING}[PATCH][Aarch64] Relational compare zero not merged into subtract

Ping. Original patch posted here: https://gcc.gnu.org/ml/gcc-patches/2017-06/msg00091.html

RE: [PING^2][PATCH][Aarch64] Add support for overflow add and sub operations

Ping ^2. Updated patch posted here: https://gcc.gnu.org/ml/gcc-patches/2017-05/msg01615.html

Re: [PATCH][X86] Fix rounding pattern similar to PR73350

On Mon, Jun 12, 2017 at 9:06 AM, Koval, Julia wrote: > I would like to, but as far as I know the only testcase possible is below, > and as far as I know there is no possibility to use dg-error for runtime > exceptions(Sorry, if I'm wrong). There are only 2 versions of the

Re: [PATCH] Fix new split-1.c testcase

On Mon, Jun 12, 2017 at 3:38 AM, Segher Boessenkool wrote: > On Sun, Jun 11, 2017 at 07:38:04PM -0700, Ian Lance Taylor wrote: >> On Sun, Jun 11, 2017 at 4:40 AM, Segher Boessenkool >> wrote: >> > >> > The new split-1.c testcase fails on

[PATCH GCC][01/13]Introduce internal function IFN_LOOP_DIST_ALIAS

Hi, I was asked by upstream to split the loop distribution patch into small ones. It is hard because data structure and algorithm are closely coupled together. Anyway, this is the patch series with smaller patches. Basically I tried to separate data structure and bug-fix changes apart with one as

[PATCH GCC][02/13]Skip distribution if there is no loop

Hi, this is a simple patch skipping distribution if there is no loop at all. Bootstrap and test on x86_64 and AArch64. Is it OK? Thanks, bin 2017-06-07 Bin Cheng * cfgloop.h (pass_loop_distribution::execute): Skip if no loops.From

[PATCH GCC][03/13]Mark and skip distributed loops

Hi, This simple patch marks distributed loops and skips it in following distribution. Bootstrap and test on x86_64 and AArch64. Is it OK? Thanks, bin 2017-06-07 Bin Cheng * tree-loop-distribution.c (generate_loops_for_partition): Mark distributed loops.

Re: [PATCH 00/30] [ARM] Reworking the -mcpu, -march and -mfpu options

On Mon, 12 Jun 2017, Richard Earnshaw (lists) wrote: > It does. The problem seems to be a generic one in the driver in that > the rewrite rules are always passed the first instance of -march and not > the last. Indeed, with the aarch64 compiler, if I write > > gcc -mcpu=native -mcpu=cortex-a53

RE: [PATCH][X86] Fix rounding pattern similar to PR73350

I'm so sorry, but I really don't get it. The right result of the test is: Floating point exception (core dumped). The wrong result of the test is: nan(no exception). If I get an exception(which is right) - the test is failed anyway. The exception is raised in one instruction, I can't get any

RE: [PATCH][X86] Fix rounding pattern similar to PR73350

I would like to, but as far as I know the only testcase possible is below, and as far as I know there is no possibility to use dg-error for runtime exceptions(Sorry, if I'm wrong). There are only 2 versions of the flag exception or no exception and the error is, when they are combined in CSE.

[PATCH] PR libstdc++/55917 do not handle exceptions in std::thread

Catching the exception and calling std::terminate() prevents a useful backtrace. Letting the runtime call terminate because of an unhandled exception gives a backtrace showing the site of the throw. PR libstdc++/55917 * src/c++11/thread.cc (execute_native_thread_routine): Remove

[PR80803 1/2] Streamline SRA access enqueuing

Hi, this is a preparation for a patch fixing PR 80803. Basically, it moves all checks for a non-null access->first_link before enqueuing a SRA access into add_access_to_work_queue instead of each caller doing it. Moreover, it fixes a thinko in ancestor enqueuing by removing an erroneous break

[PATCH] Trivial fix in dump_access_tree_1

Hello, when invoking dump_access_tree_1 from gdb, I found out that it attempts to write to dump_file even though it should dump to its parameter f. I am about to fix it by the following obvious patch, after it passes bootstrap and testing on an x86_64-linux (along with more substantive patches).

Re: [GCC][PATCH][mid-end] Optimize x * copysign (1.0, y) [Patch (1/2)]

Richard Biener writes: > On Mon, 12 Jun 2017, Tamar Christina wrote: >> Hi All, >> >> this patch implements a optimization rewriting >> >> x * copysign (1.0, y) and >> x * copysign (-1.0, y) >> >> to: >> >> x ^ (y & (1 << sign_bit_position)) >> >> This is done by

Re: [RFC] Dejagnu patch to handle multi-line directives

On Jun 10, 2017, at 12:57 AM, Tom de Vries wrote: > > one thing that has bothered me on a regular basis is the inability to spread > long dejagnu directives over multiple lines. I'm not terribly in favor of this. I'd like to retain the ability to grep and sed single

Re: [GCC][PATCH][mid-end] Optimize x * copysign (1.0, y) [Patch (1/2)]

On Mon, 12 Jun 2017, Tamar Christina wrote: > x * copysign (1.0, y) and > x * copysign (-1.0, y) > > to: > > x ^ (y & (1 << sign_bit_position)) Note that this needs to be disabled for -fsignaling-nans, as if x is a signaling NaN, the multiplication converts it to a quiet NaN and raises

[PR80803 2/2] Diligent queuing in SRA grp_write prop

Hi, the patch below fixes PR 80803 (and its newer duplicate 81063), it is essentially a semi-rewrite of propagate_subaccesses_across_link. When fixing the previous fallout from lazy setting of grp_write flag, I failed to see that it does not look on sub-accesses of the LHSs at all and thus does

Re: [PATCH][X86] Fix rounding pattern similar to PR73350

On Mon, Jun 12, 2017 at 09:08:00AM -0700, H.J. Lu wrote: > On Mon, Jun 12, 2017 at 9:06 AM, Koval, Julia wrote: > > I would like to, but as far as I know the only testcase possible is below, > > and as far as I know there is no possibility to use dg-error for runtime > >

Re: [PATCH v8] add -fpatchable-function-entry=N,M option

On 06/06/2017 03:49 AM, Torsten Duwe wrote: On Sun, Jun 04, 2017 at 08:12:49PM -0600, Sandra Loosemore wrote: On 05/29/2017 04:29 AM, Maxim Kuvyrkov wrote: diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 65308c9d933..6cbb77a8dc4 100644 --- a/gcc/doc/invoke.texi +++

[PATCH GCC][09/13]Simply cost model merges partitions with the same references

Hi, Current primitive cost model merges partitions with data references sharing the same base address. I believe it's designed to maximize data reuse in distribution, but that should be done by dedicated data reusing algorithm. At this stage of merging, we should be conservative and only

[PATCH GCC][06/13]Preserve loop nest in whole distribution life time

Hi, This simple patch computes and preserves loop nest vector for whole distribution life time. The loop nest will be used multiple times in on-demand data dependence computation. Bootstrap and test on x86_64 and AArch64. Is it OK? Thanks, bin 2017-06-07 Bin Cheng

[PATCH GCC][04/13]Sort statements in topological order for loop distribution

Hi, During the work I ran into a latent bug for distributing. For the moment we sort statements in dominance order, but that's not enough because basic blocks may be sorted in reverse order of execution flow. This results in wrong data dependence direction later. This patch fixes the issue

[PATCH GCC][07/13]Preserve data references for whole distribution life time

Hi, This patch collects and preserves all data references in loop for whole distribution life time. It will be used afterwards. Bootstrap and test on x86_64 and AArch64. Is it OK? Thanks, bin 2017-06-07 Bin Cheng * tree-loop-distribution.c (datarefs_vec,

[PATCH GCC][05/13]Refactoring partition merge

Hi, This simple patch refactors partition merge code and dump information. Bootstrap and test on x86_64 and AArch64. Is it OK? Thanks, bin 2017-06-07 Bin Cheng * tree-loop-distribution.c (enum fuse_type, fuse_message): New. (partition_merge_into): New

Re: [PATCH 0/13] D: Submission of D Front End

[Disclaimer: I can't approve any of this :-)] Iain Buclaw writes: > 001 - The front-end (DMD) language implementation and license. > 002 - The front-end (GDC) implementation. > 003 - The front-end (GDC) changelogs (here be dragons). > 004 - The front-end (GDC)

Re: [PATCH v2, rs6000] gcc mainline, add builtin support for vec_float, vec_float2, vec_floate, vec_floate, builtins

On Mon, 2017-06-12 at 14:09 -0400, Michael Meissner wrote: > > > > > > +(define_insn "vsx_xvcvsxwsp" > > > > + [(set (match_operand:V4SF 0 "vsx_register_operand" "=v") > > > > + (unspec:V4SF[(match_operand:V4SI 1 "vsx_register_operand" "v")] > > > > +

Re: [C++ PATCH] Fix sanitization ICE (PR c++/80973)

On Mon, Jun 12, 2017 at 4:04 AM, Jakub Jelinek wrote: > On Fri, Jun 09, 2017 at 12:30:10PM -0700, Jason Merrill wrote: >> On Thu, Jun 8, 2017 at 12:30 PM, Jakub Jelinek wrote: >> > cp_genericize_r now instruments INTEGER_CSTs that have REFERENCE_TYPE, >> > so

Re: [1/2] PR 78736: New warning -Wenum-conversion

This is OK with one fix: > +C ObjC Var(warn_enum_conversion) Init(0) Warning LangEnabledBy(C Objc,Wall) I believe the LangEnabledBy arguments are case-sensitive, so you need to have ObjC not Objc there for it to work correctly. (*.opt parsing isn't very good at detecting typos and giving

Re: [RFC] Dejagnu patch to handle multi-line directives

On 06/12/2017 08:59 AM, Richard Sandiford wrote: > I realise there's probably more that can go wrong with it, but how > about instead treating unbalanced { ... } as a sign that the directive > continues to the next line? This would allow: > > /* { dg-additional-options >

Re: [PATCH v2, rs6000] gcc mainline, add builtin support for vec_float, vec_float2, vec_floate, vec_floate, builtins

On Fri, Jun 09, 2017 at 04:12:25PM -0700, Carl E. Love wrote: > GCC Maintainers: > > On Fri, 2017-06-09 at 16:05 -0500, Segher Boessenkool wrote: > > Fixed the various formatting (spaces) issues. Been toying with how to > write a space checker for patches. Have to take some time to really >

Re: [GCC][PATCH][mid-end] Optimize x * copysign (1.0, y) [Patch (1/2)]

On Mon, Jun 12, 2017 at 07:56:54AM +, Tamar Christina wrote: > Hi All, > > this patch implements a optimization rewriting > > x * copysign (1.0, y) and > x * copysign (-1.0, y) > > to: > > x ^ (y & (1 << sign_bit_position)) > > This is done by creating a special builtin during matching

Go patch committed: avoid orphaning Bexpressions when processing conversions

The Go frontend method Type_conversion_expression::do_get_backend was (in some circumstances) creating a Bexpression for the source expression of the conversion and then throwing it away before using it. This patch by Than McIntosh fixes up this method to insure that the call to get_backend() on

Re: [PATCH] Fix new split-1.c testcase

On Mon, Jun 12, 2017 at 09:16:32AM -0700, Ian Lance Taylor wrote: > On Mon, Jun 12, 2017 at 3:38 AM, Segher Boessenkool > wrote: > > Ah, I see. Could you change the comment then, to say what we are > > really testing? > > Sure. Updated as follows. Committed to

[gomp5] s/void */const void */ in some omp.h APIs

Hi! OpenMP 5.0 is changing a couple of APIs, so that for pointer arguments where the pointed array is not modified we use const void * instead of void *. Committed to gomp-5_0-branch. 2017-06-12 Jakub Jelinek * omp.h.in (omp_target_is_present,

RE: [PATCH] MIPS16/GCC: Emit bounds checking as RTL in `casesi'

Maciej Rozycki writes: > Further to my changes made last November here is an update to the MIPS16 > `casesi' pattern making it emit bounds checking as RTL rather than having > it as hardcoded assembly within the `casesi_internal_mips16_' > dispatcher. See below for

[gomp5] Parsing of in_reduction/task_reduction clauses

Hi! This patch adds parsing of in_reduction and task_reduction clauses and reduction on taskloop. The lowering/expansion and library side is not done yet. Committed to gomp-5_0-branch. 2017-06-12 Jakub Jelinek * tree.def (OMP_TASKGROUP): Add another operand, move

Re: [PATCH v2, rs6000] gcc mainline, add builtin support for vec_float, vec_float2, vec_floate, vec_floate, builtins

On Mon, Jun 12, 2017 at 11:40:17AM -0700, Carl E. Love wrote: > Michael: > > OK, so sounds like I should stick to the general wa register constraint. > The third field of the define_expand I have what I believe is called the > "condition string" as "TARGET_VSX". Is that the appropriate condition

Re: [PATCH 00/30] [ARM] Reworking the -mcpu, -march and -mfpu options

On 12/06/17 18:11, Joseph Myers wrote: > On Mon, 12 Jun 2017, Richard Earnshaw (lists) wrote: > >> It does. The problem seems to be a generic one in the driver in that >> the rewrite rules are always passed the first instance of -march and not >> the last. Indeed, with the aarch64 compiler, if

Re: [C++ PATCH] Fix genericization ICE (PR c++/80984)

OK. On Wed, Jun 7, 2017 at 2:01 AM, Jakub Jelinek wrote: > Hi! > > As the testcase shows, BLOCK_VARS of the outermost scope can contain > decls other than VAR_DECL that have DECL_NAME identical to what we are > looking for, in this case a LABEL_DECL. The code is looking for

[PATCH, rs6000] (v2) Fold vector shifts in GIMPLE

Hi, [PATCH, rs6000] (v2) Fold vector shifts in GIMPLE Add support for early expansion of vector shifts. Including vec_sl (shift left), vec_sr (shift right), vec_sra (shift right algebraic), vec_rl (rotate left). Part of this includes adding the vector shift right instructions to the list of

Re: [PATCH] warn on mem calls modifying objects of non-trivial types (PR 80560)

On 06/08/2017 01:25 PM, Martin Sebor wrote: + if (TREE_CHAIN (DECL_ARGUMENTS (f))) + { + /* Skip constructors that aren't copy or move ctors. */ + if (!copy_fn_p (f)) + continue; + + cpy_or_move_ctor_p = true; + } + else + { +

Re: [PATCH 0/13] D: Submission of D Front End

On Jun 12, 2017, at 11:34 AM, Richard Sandiford wrote: > > I'm not sure who this is a question to really, but how much value is > there in reviewing the other patches? > Maybe people who know the > frontend interface well could comment on that part, but would

Re: [PATCH 0/13] D: Submission of D Front End

On 13 June 2017 at 01:22, Mike Stump wrote: > On Jun 12, 2017, at 11:34 AM, Richard Sandiford > wrote: >> >> I'm not sure who this is a question to really, but how much value is >> there in reviewing the other patches? > >> Maybe people who

Re: [PATCH] Finish implementing P0426R1 "Constexpr for std::char_traits" for C++17

On 06/05/2017 03:27 PM, Jonathan Wakely wrote: > Pedro, this is OK for trunk now we're in stage 1. Please go ahead and > commit it - thanks. Thanks Jonathan. I've pushed it in now. > > It's probably safe for gcc-7-branch too, but let's leave it on trunk > for a while first. OK. BTW, for

Re: [PATCH 0/13] D: Submission of D Front End

On 12 June 2017 at 20:34, Richard Sandiford wrote: > [Disclaimer: I can't approve any of this :-)] > > Iain Buclaw writes: >> 001 - The front-end (DMD) language implementation and license. >> 002 - The front-end (GDC) implementation. >>

libgo patch committed: clear isSystemGoroutine in goexit

This patch to libgo clears the isSystemGoroutine field of the g structure when the goroutine exits. Otherwise it may be set when the g structure is reused via gfput/gfget. Bootstrapped and ran Go testsuite on x86_64-pc-linux-gnu. Committed to mainline. Ian Index: gcc/go/gofrontend/MERGE

libgo patch committed: ignore _Gscan bit when checking status in CgocallDone

This patch to libgo ignores the _Gscan bit when checking status in CgocallDone. It also always access the atomicstatus field atomically. The effect of not checking the _Gscan bit is that if the GC decides to scan the stack just as the goroutine is leaving the system call, the goroutine might fail

Re: [PATCH v3, rs6000] gcc mainline, add builtin support for vec_float, vec_float2, vec_floate, vec_floate, builtins

GCC Maintainers: I have updated the define_expands for float2_v2di, uns_float2_v2di, unsfloatev2di, floato, unsfloatov2di per the comments from Michael Meissner. I retested the changes on powerpc64le-unknown-linux-gnu (Power 8 LE) only. Please let me know if there are any additional issues

Re: [PATCH try 2 resend] [i386] Remove warnings for ignoring -mcall-ms2sysv-xlogues.

On 06/11/2017 02:35 PM, Daniel Santos wrote: diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index c1168823af7..eec02b43a4f 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -25389,11 +25389,26 @@ using the function attributes @code{ms_abi} and @code{sysv_abi}. @opindex

Re: [patch,avr] Add support for devices with flash accessible by LD.

On Friday 09 June 2017 03:59 PM, Georg-Johann Lay wrote: Hi, This patch adds support for devices that can access flash memory by LD* instructions, hence there is no need to put .rodata in RAM. The default linker script for the new multilib versions already supports this feature, it's similar

Re: Reorganise machmode.h headers

Ping Richard Sandiford writes: > Jeff Law writes: >> On 11/16/2016 09:32 AM, Richard Sandiford wrote: >>> Later patches will make machmode.h rely on wide-int.h and the >>> new poly-int.h, so it needs to appear later in the coretypes.h >>> include

Re: Fix pessimistic DImode handling in combine.c:make_field_assignment

Ping Richard Sandiford writes: > Richard Sandiford writes: >> The make_field_assignment code: >> >> src = force_to_mode (src, mode, >> GET_MODE_PRECISION (mode) >= HOST_BITS_PER_WIDE_INT >>

Re: [2/2] PR 80769: Incorrect strlen optimisation

Ping*2 Richard Sandiford writes: > In this testcase, we (correctly) record after: > > strcpy (p1, "abcde"); > char *p2 = strchr (p1, '\0'); > strcpy (p2, q); > > that the length of p1 and p2 can be calculated by converting the > second strcpy to: > > tmp =

Re: [PATCH][GCC][AArch64] optimize float immediate moves (2 /4) - HF/DF/SF mode.

Hi All, Updating this patch with the feedback I've received from patch 1/4. Thanks, Tamar From: gcc-patches-ow...@gcc.gnu.org on behalf of Tamar Christina Sent: Wednesday, June 7, 2017 12:38:37 PM

Re: [patch,avr] Add support for devices with flash accessible by LD.

On 12.06.2017 08:30, Pitchumani Sivanupandi wrote: On Friday 09 June 2017 03:59 PM, Georg-Johann Lay wrote: Hi, This patch adds support for devices that can access flash memory by LD* instructions, hence there is no need to put .rodata in RAM. The default linker script for the new multilib

[GCC][PATCH][AArch64] Optimize x * copysign (1.0, y) [Patch (2/2)]

Hi All, this patch implements a optimization rewriting x * copysign (1.0, y) and x * copysign (-1.0, y) to: x ^ (y & (1 << sign_bit_position)) The patch provides AArch64 optabs for XORSIGN, both vectorized and scalar. This patch is a revival of a previous patch

Re: [RFC] Dejagnu patch to handle multi-line directives

Tom de Vries writes: > [ attached patch ] > > On 06/10/2017 09:57 AM, Tom de Vries wrote: >> Hi, >> >> one thing that has bothered me on a regular basis is the inability to >> spread long dejagnu directives over multiple lines. >> >> I've written a demonstrator patch

[PATCH] Fix PR81053

I am testing the following to fix PR81053. Bootstrap and regtest running on x86_64-unknown-linux-gnu. Richard. 2017-06-12 Richard Biener PR tree-optimization/81053 * tree-vect-loop.c (vect_is_simple_reduction): Handle PHI with backedge value not

Re: [PATCH][GCC][AArch64] optimize float immediate moves (1 /4) - infrastructure.

Hi Richard, Here's the updated patch, thanks for the feedback so far! Regards, Tamar From: Richard Sandiford Sent: Thursday, June 8, 2017 11:32:07 AM To: Tamar Christina Cc: GCC Patches; nd; James Greenhalgh; Marcus

Re: [PATCH] Fix PR66623

On 9 June 2017 at 17:48, Richard Biener wrote: > On June 9, 2017 5:32:10 PM GMT+02:00, Christophe Lyon > wrote: >>On 8 June 2017 at 15:49, Richard Biener wrote: >>> On Thu, 8 Jun 2017, Richard Biener wrote: >>>

[PATCH] Create an extra BB in profile-generate (PR tree-optimization/81041).

Hello. Sorry for this breakage, it's actually the same mistake I did in the PR that belongs to the test I broke. I overlooked the ICE in log file. I'm testing the patch, may I install it after it survives regression tests? Martin >From 20e5419136ec26ed009ca93eedccd2582b65dd36 Mon Sep 17

Re: [PATCH PR78005]Fix miscompare issue by computing correct guard condition for vectorized loop

"Bin.Cheng" writes: > On Sat, Jun 10, 2017 at 10:40 AM, Richard Sandiford > wrote: >> Sorry to return this old patch, but: >> >> Bin Cheng writes: >>> -/* Calculate the number of iterations under which scalar loop will be

Re: [PATCH] Fix PR66623

On Mon, 12 Jun 2017, Christophe Lyon wrote: > On 9 June 2017 at 17:48, Richard Biener wrote: > > On June 9, 2017 5:32:10 PM GMT+02:00, Christophe Lyon > > wrote: > >>On 8 June 2017 at 15:49, Richard Biener wrote: > >>>

[GCC][PATCH][mid-end] Optimize x * copysign (1.0, y) [Patch (1/2)]

Hi All, this patch implements a optimization rewriting x * copysign (1.0, y) and x * copysign (-1.0, y) to: x ^ (y & (1 << sign_bit_position)) This is done by creating a special builtin during matching and generate the appropriate instructions during expand. This new builtin is called

Re: [PATCH GCC8][32/33]Save niter check for vect peeling if loop versioning is required

On Sat, Jun 10, 2017 at 11:06 AM, Richard Sandiford wrote: > Another one sorry, but: > > Bin Cheng writes: >> diff --git a/gcc/tree-vect-loop.c b/gcc/tree-vect-loop.c >> index af874e7..98caa5e 100644 >> --- a/gcc/tree-vect-loop.c >> +++

[BUILDROBOT] No rule to make target '/home/jbglaw/repos/gcc/gcc/config/rs6000/e500.h', needed by 's-gtype' (was: [PATCH 01/14] rs6000: Remove TARGET_FPRS)

Hi Segher! On Tue, 2017-06-06 15:56:17 +, Segher Boessenkool wrote: > Since rs6000 no longer supports SPE, TARGET_FPRS now always is true. > > This makes TARGET_{SF,DF}_SPE always false. Many patterns in spe.md > can now be deleted; which makes it possible to

Re: [GCC][PATCH][mid-end] Optimize x * copysign (1.0, y) [Patch (1/2)]

On Mon, 12 Jun 2017, Tamar Christina wrote: > Hi All, > > this patch implements a optimization rewriting > > x * copysign (1.0, y) and > x * copysign (-1.0, y) > > to: > > x ^ (y & (1 << sign_bit_position)) > > This is done by creating a special builtin during matching and generate the >

Re: [PATCH, GCC/LTO, ping] Fix PR69866: LTO with def for weak alias in regular object file

Ping? Best regards, Thomas On 06/06/17 11:12, Thomas Preudhomme wrote: On 09/05/17 23:36, Jan Hubicka wrote: Ping? Sorry for late reply My turn to apologize now. Hi, This patch fixes an assert failure when linking one LTOed object file having a weak alias with a regular object file

improve stdint.h handling for VxWorks

Building a powerpc-wrs-vxworks compiler with a very recent mainline fails with numerous instances or error like: In file included from /powerpc-wrs-vxworks/sys-include/types/vxTypesOld.h:123:0, from /gcc/include-fixed/stdint.h:16, from

[BUILDROBOT] error: format ‘%d’ expects argument of type ‘int’, but argument 3 has type ‘long int’ (was: [PATCH] [ARC] Recognise add_n and sub_n in combine again)

On Fri, 2017-05-12 20:14:23 +0100, Graham Markall wrote: > Since the combine pass canonicalises shift-add insns using plus and > ashift (as opposed to plus and mult which it previously used to do), it > no longer creates *add_n or *sub_n insns, as the patterns match

Re: [PATCH PR78005]Fix miscompare issue by computing correct guard condition for vectorized loop

On Mon, Jun 12, 2017 at 9:19 AM, Richard Sandiford wrote: > "Bin.Cheng" writes: >> On Sat, Jun 10, 2017 at 10:40 AM, Richard Sandiford >> wrote: >>> Sorry to return this old patch, but: >>> >>> Bin Cheng

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