Re: [PATCH] Fix bug in simplify_ternary_operation

On 08/28/2017 08:26 PM, Tom de Vries wrote: Hi, I think I found a bug in r17465: ... * cse.c (simplify_ternary_operation): Handle more IF_THEN_ELSE simplifications. diff --git a/gcc/cse.c b/gcc/cse.c index e001597..3c27387 100644 --- a/gcc/cse.c +++ b/gcc/cse.c @@ -4713,6

Re: [PATCH][GCC][AARCH64]Bad code-gen for structure/block/unaligned memory access

Hi Tamar, I think the AArch64 parts of this patch can be substantially simplified. On Mon, Jul 03, 2017 at 07:17:51AM +0100, Tamar Christina wrote: > diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c > index >

Re: [AArch64] Remove use of wider vector modes

On Tue, Aug 22, 2017 at 10:20:46AM +0100, Richard Sandiford wrote: > The AArch64 port defined x2, x3 and x4 vector modes that were only used > in the rtl for the AdvSIMD LD{2,3,4} patterns. It seems unlikely that > this rtl would have led to any valid simplifications, since the values > involved

Re: [AArch64] Tighten address register subreg checks

On Tue, Aug 22, 2017 at 10:25:02AM +0100, Richard Sandiford wrote: > Previously we allowed subregs of non-GPR modes to be base and index > registers in non-strict mode. In practice such subregs will always > require a reload, so we get better code by disallowing them. Makes sense. > Tested on

Re: [PATCH GCC]A simple implementation of loop interchange

On Wed, Aug 30, 2017 at 3:19 PM, Richard Biener wrote: > On Wed, Aug 30, 2017 at 3:18 PM, Bin Cheng wrote: >> Hi, >> This patch implements a simple loop interchange pass in GCC, as described by >> its comments: >> +/* This pass performs loop

Re: [PATCH], PR target/82015, add PowerPC warning for unpack_vector_int128 with illegal 2nd argument

Bill Seurer pointed out to me that when I checked in the PR 82015 patches, I had changed the error message, but I didn't update the test. I checked this patch in as obvious: 2017-08-30 Michael Meissner PR target/82015 *

Re: [C++ PATCH] Make taking the address of an overloaded function a non-deduced context

On Tue, Aug 29, 2017 at 6:19 PM, Ville Voutilainen wrote: > 2017-08-29 Ville Voutilainen > > Make taking the address of an overloaded function a non-deduced context > > cp/ > > * pt.c (unify_overload_resolution_failure):

[PATCH] Fix PR81987 (SLSR dominance issue)

Hi, https://gcc.gnu.org/PR81987 identifies an SSA verification error following SLSR. The problem arises when SLSR places an initialization expression at a point not dominated by the definition of an SSA name it uses. When there are multiple conditional candidates for replacement, the

Re: AArch64 patch pings

James Greenhalgh writes: > On Wed, Aug 30, 2017 at 04:34:40PM +0100, Richard Sandiford wrote: >> Ping for a few AArch64 patches: >> >> [AArch64] Remove use of wider vector modes >> https://gcc.gnu.org/ml/gcc-patches/2017-08/msg01249.html >> >> [AArch64]

Re: Add a partial_subreg_p predicate

Jeff Law writes: > On 08/21/2017 07:34 AM, Richard Sandiford wrote: >> This patch adds a partial_subreg_p predicate to go alongside >> paradoxical_subreg_p. >> >> The first two changes to cse_insn preserve the current behaviour, >> but the condition seems strange. Shouldn't we

RE: [RFC, vectorizer] Allow single element vector types for vector reduction operations

On August 30, 2017 5:11:24 PM GMT+02:00, Jon Beniston wrote: >Hi Richard, > >> I think the issue is that with TARGET_VECTOR_MODE_SUPPORTED_P false >> for V1SI you'll get a SImode vector type and the >> >> if (VECTOR_BOOLEAN_TYPE_P (type_in) >> || VECTOR_MODE_P (TYPE_MODE

Re: [PATCH] Factor out division by squares and remove division around comparisons (2/2)

Hi all, I've attached a new version of the patch in response to a few of Wilco's comments in person. The end product of the pass is still the same, but I have fixed several bugs. Now tested independently of the other patches. On 08/15/2017 03:07 PM, Richard Biener wrote: On Thu, Aug 10,

Re: [C++ PATCH] Make taking the address of an overloaded function a non-deduced context

On 30 August 2017 at 19:07, Jason Merrill wrote: > Please also remove the error. OK with that change. Here's a new and much improved version as discussed on IRC. Tested on Linux-PPC64. Ok for trunk? 2017-08-30 Ville Voutilainen Make

Re: [AArch64] Rename cmp_result iterator

On Tue, Aug 22, 2017 at 10:22:37AM +0100, Richard Sandiford wrote: > The comparison results provided by the V_cmp_result/v_cmp_result > attribute were simply the corresponding integer vector. We'd also > like to have easy access to the integer vector for SVE, but using > "cmp_result" would be

Re: [Patch][aarch64] Use IFUNCs to enable LSE instructions in libatomic on aarch64

On Tue, 2017-08-29 at 12:25 +0100, Szabolcs Nagy wrote: >  > it's a general bug that most ifunc users (e.g. in binutils > tests) declare the ifunc resolvers incorrectly, the correct > prototype is the way the dynamic linker invokes the resolver > in sysdeps/aarch64/dl-irel.h: > > static inline

Re: [AArch64] Tweak aarch64_classify_address interface

On Tue, Aug 22, 2017 at 10:23:47AM +0100, Richard Sandiford wrote: > Previously aarch64_classify_address used an rtx code to distinguish > LDP/STP addresses from normal addresses; the code was PARALLEL > to select LDP/STP and anything else to select normal addresses. > This patch replaces that

Re: [PATCH][RFC] Make expansion of balanced binary trees of switches on tree level.

Hi Martin, > Yes, sorry for the missing entries. Fixed and installed as r251412. > Hopefully fall out will be small. there's UNRESOLVED: gcc.dg/tree-ssa/vrp104.c scan-tree-dump-times switchlower "switch" 1 everywhere, it seems. gcc.log has gcc.dg/tree-ssa/vrp104.c: dump file does not exist

[RFC] Make 4-stage PGO bootstrap really working

Hi. This is follow up which I've just noticed. Main problem we have is that an instrumented compiler w/ -fprofile-generate (built in $OBJDIR/gcc subfolder) will generate all *.gcda files in a same dir as *.o files. That's problematic because we then have *.gcda files spread in 'profile' subfolder

Re: [PATCH] Fix IPA ICF with ASM statements (PR inline-asm/82001).

On Wed, Aug 30, 2017 at 11:12 AM, Martin Liška wrote: > Hi. > > Following patch compares also constraints of input and output operands of ASM > statements. > Patch can bootstrap on ppc64le-redhat-linux and survives regression tests. > > Ready to be installed? It's now no longer

Re: [PATCH][GCC][AARCH64]Bad code-gen for structure/block/unaligned memory access

Hi, The test I used was testsuite/gcc.c-torture/compile/structs.c Thanks, Tamar From: H.J. Lu Sent: Friday, August 25, 2017 8:10:22 PM To: Tamar Christina Cc: Richard Sandiford; GCC Patches; nd; James Greenhalgh; Richard Earnshaw;

Re: [PATCH] Factor out division by squares and remove division around comparisons (1/2)

On 08/29/2017 01:13 PM, Richard Biener wrote: On Tue, Aug 29, 2017 at 1:35 PM, Jackson Woodruff wrote: Hi all, Apologies again to those CC'ed, who (again) received this twice. Joseph: Yes you are correct. I misread the original thread, now fixed. Richard: I've

Re: [PATCH] Fix file find utils and add unit tests (PR driver/81829).

On 08/25/2017 06:41 PM, Martin Sebor wrote: > On 08/18/2017 04:17 AM, Martin Liška wrote: >> On 08/15/2017 02:45 PM, Martin Liška wrote: >>> Hi. >>> >>> As shown in the PR, remove_prefix function is written wrongly. It does not >>> distinguish >>> in between a node in linked list and

Re: [PATCH] [MSP430] [PR80993] Prevent lto removing interrupt handlers

On Tue, Aug 29, 2017 at 5:47 PM, DJ Delorie wrote: > > Richard Biener writes: >> Humm... don't you have to register interrupt handlers somehow? > > MSP430 uses an "if they're present, they're registered" approach, so > it's driven by the user tagging

[TESTSUITE]Use strncpy instead of strcpy in testsuite/gcc.dg/memcmp-1.c

Hi, In test_driver_memcmp function, I found buf1 and buf2 is not properly terminated with null character. In lib_strncmp, strcpy will be called with buf1 and buf2. The normal implementation of strcpy function has a loop to copy character from source to destination one by one until a null

Re: [PATCH] Fix PR82011, early LTO debug fallout

On Tue, 29 Aug 2017, Richard Biener wrote: > On Tue, 29 Aug 2017, Richard Biener wrote: > > > > > The following avoids adding DW_AT_inline attributes twice on which > > dsymutil complains. The duplicate attribute is caused by stray > > code I left in (I guess I hoped nothing ends up

[PATCH] Fix last dwarf2out change with pubnames

Noticed when trying to do sth on Darwin. Lightly tested, committed as obvious. Richard. 2017-08-30 Richard Biener * dwarf2out.c (dwarf2out_finish): Remove setting AT_pubnames. (dwarf2out_early_finish): Move setting of AT_pubnames from early debug

[rs6000] int->machine_mode in rs6000-c.c

Tested on powerpc64le-linux-gnu and installed as obvious. 2017-08-30 Richard Sandiford gcc/ * config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin): Use machine_mode rather than int for arg1_mode. Index: gcc/config/rs6000/rs6000-c.c

Re: [PATCH] [MSP430] Pass -mcode/data-region to the linker and assembler

Hi Jozef, > The changes made in a series of binutils patches > (https://sourceware.org/ml/binutils/2017-08/msg00274.html) > to ld and gas require the -mcode/data-region options to be propagated > from gcc. > > The attached patch adds that functionality. Approved and applied. Cheers Nick

RE: [RFC, vectorizer] Allow single element vector types for vector reduction operations

Hi Richard, >> Ah, that's what I first tried, and mistakenly sent the patch against that. >> >> That did help the initial problem, but then I needed to add a lot of >> support for the V1SI type in the backend (which just duplicated SI >> patterns) and there are a few places where GCC seems to

Re: [RFC] [PATCH] Introduce configure flag --with-stage1-cflags.

On 08/28/2017 02:24 PM, Richard Biener wrote: > On Fri, Aug 25, 2017 at 9:51 PM, Jeff Law wrote: >> On 07/31/2017 01:47 AM, Martin Liška wrote: >>> I would like to ping this. Input from other people will be appreciated ;) >> I think the thing to keep in mind here is that IIUC

[PATCH] Fix IPA ICF with ASM statements (PR inline-asm/82001).

Hi. Following patch compares also constraints of input and output operands of ASM statements. Patch can bootstrap on ppc64le-redhat-linux and survives regression tests. Ready to be installed? Martin gcc/ChangeLog: 2017-08-28 Martin Liska PR inline-asm/82001

Re: [PATCH] Fix IPA ICF with ASM statements (PR inline-asm/82001).

On 08/30/2017 11:18 AM, Richard Biener wrote: > On Wed, Aug 30, 2017 at 11:12 AM, Martin Liška wrote: >> Hi. >> >> Following patch compares also constraints of input and output operands of >> ASM statements. >> Patch can bootstrap on ppc64le-redhat-linux and survives regression

Re: [RFC, vectorizer] Allow single element vector types for vector reduction operations

"Jon Beniston" writes: > Hi Richard, > >> I think the issue is that with TARGET_VECTOR_MODE_SUPPORTED_P false >> for V1SI you'll get a SImode vector type and the >> >> if (VECTOR_BOOLEAN_TYPE_P (type_in) >> || VECTOR_MODE_P (TYPE_MODE (type_in))) >> >>check fails. Try

Re: All carchive gotools tests fail

On Thu, Aug 24, 2017 at 3:19 AM, Uros Bizjak wrote: > Hello! > > Following carchive gotools tests fail in gccgo testsuite: > > FAIL: TestCgoCallbackGC > FAIL: TestInstall > FAIL: TestEarlySignalHandler > FAIL: TestSignalForwarding > FAIL: TestSignalForwardingExternal > FAIL:

Re: Add support to trace comparison instructions and switch statements

On Sat, Aug 5, 2017 at 11:53 AM, 吴潍浠(此彼) wrote: > Hi all > Is it worth adding my codes to gcc ? Are there some steps I need to do ? > Could somebody tell me the progress ? FYI, we've mailed a Linux kernel change that uses this instrumentation:

Re: [C++ PATCH] Make taking the address of an overloaded function a non-deduced context

On Wed, Aug 30, 2017 at 1:08 PM, Ville Voutilainen wrote: > On 30 August 2017 at 19:07, Jason Merrill wrote: >> Please also remove the error. OK with that change. > > Here's a new and much improved version as discussed on IRC. Tested on >

Re: Add a partial_subreg_p predicate

On 08/30/2017 09:41 AM, Richard Sandiford wrote: > > Even then I don't think we could ever have SET_SRC and SET_DEST being > different. The extension has to be explicit in the source. Yea, you should still have the same mode for the SET_SRC and SET_DEST. It's just that the operands underneath

Re: [PATCH] Fix PR81987 (SLSR dominance issue)

On August 30, 2017 7:22:45 PM GMT+02:00, Bill Schmidt wrote: >Hi, > >https://gcc.gnu.org/PR81987 identifies an SSA verification error >following >SLSR. The problem arises when SLSR places an initialization expression >at >a point not dominated by the definition of

Re: [TESTSUITE]Use strncpy instead of strcpy in testsuite/gcc.dg/memcmp-1.c

On Aug 30, 2017, at 8:31 AM, Renlin Li wrote: > memcpy is better than strncpy in this case. > Here is the updated patch. Ok.

Re: AArch64 patch pings

On Wed, Aug 30, 2017 at 04:34:40PM +0100, Richard Sandiford wrote: > Ping for a few AArch64 patches: > > [AArch64] Remove use of wider vector modes > https://gcc.gnu.org/ml/gcc-patches/2017-08/msg01249.html > > [AArch64] Rename cmp_result iterator >

Re: C++ PATCH for c++/80767, unnecessary instantiation of generic lambda

On Tue, Aug 29, 2017 at 3:12 PM, Jason Merrill wrote: > In this testcase, when we try to call the object of 'overloader' type, > we consider the conversion function from the first lambda to void > (*)(a) and build up a surrogate call function for it. We consider how > to

RE: [RFC, vectorizer] Allow single element vector types for vector reduction operations

On Wed, 30 Aug 2017, Jon Beniston wrote: > Hi Richard, > > >> Ah, that's what I first tried, and mistakenly sent the patch against > that. > >> > >> That did help the initial problem, but then I needed to add a lot of > >> support for the V1SI type in the backend (which just duplicated SI >

[PATCH] Expand switch statements with a single (or none) non-default case.

Hi. Simple transformation of switch statements where degenerated switch can be interpreted as gimple condition (or removed if having any non-default case). I originally though that we don't have switch statements without non-default cases, but PR82032 shows we can see it. Patch can bootstrap

[PATCH GCC]A simple implementation of loop interchange

Hi, This patch implements a simple loop interchange pass in GCC, as described by its comments: +/* This pass performs loop interchange: for example, the loop nest + + for (int j = 0; j < N; j++) + for (int k = 0; k < N; k++) + for (int i = 0; i < N; i++) +c[i][j] = c[i][j] +

RE: [PATCH][GCC][PATCHv3] Improve fpclassify w.r.t IEEE like numbers in GIMPLE.

On Tue, 29 Aug 2017, Tamar Christina wrote: > > > > -Original Message- > > From: Richard Biener [mailto:rguent...@suse.de] > > Sent: 24 August 2017 10:16 > > To: Tamar Christina > > Cc: Joseph Myers; Christophe Lyon; Markus Trippelsdorf; Jeff Law; GCC > > Patches; Wilco Dijkstra;

Re: [PATCH,AIX] Cleanup in libiberty for AIX.

On Tue, Aug 29, 2017 at 8:10 AM, REIX, Tony wrote: > Description: > * This patch does some cleanup in libiberty for AIX. > > Tests: > * AIX: Build: SUCCESS >- build made by means of gmake in trunk. >- patch generated by: > cd gcc-svn-trunk/ > svn diff

Re: [PATCH GCC]A simple implementation of loop interchange

On Wed, Aug 30, 2017 at 3:18 PM, Bin Cheng wrote: > Hi, > This patch implements a simple loop interchange pass in GCC, as described by > its comments: > +/* This pass performs loop interchange: for example, the loop nest > + > + for (int j = 0; j < N; j++) > + for (int k

Re: [PATCH][GCC][AARCH64]Bad code-gen for structure/block/unaligned memory access

On Wed, Aug 30, 2017 at 2:21 AM, Tamar Christina wrote: > Hi, > > The test I used was testsuite/gcc.c-torture/compile/structs.c Results look very nice on x86-64. Can we add a testcase to scan the compiler output to verify this optimization? Thanks. > Thanks, > Tamar >

Re: [66/77] Use scalar_mode for constant integers

Jeff Law writes: > On 07/13/2017 03:02 AM, Richard Sandiford wrote: >> This patch treats the mode associated with an integer constant as a >> scalar_mode. We can't use the more natural-sounding scalar_int_mode >> because we also use (const_int 0) for bounds-checking modes. (It

Re: [PATCH] Fix IPA ICF with ASM statements (PR inline-asm/82001).

On Wed, Aug 30, 2017 at 12:17 PM, Martin Liška wrote: > On 08/30/2017 11:18 AM, Richard Biener wrote: >> On Wed, Aug 30, 2017 at 11:12 AM, Martin Liška wrote: >>> Hi. >>> >>> Following patch compares also constraints of input and output operands of >>> ASM

Re: [PATCH] Expand switch statements with a single (or none) non-default case.

On 08/30/2017 02:28 PM, Richard Biener wrote: > On Wed, Aug 30, 2017 at 1:13 PM, Martin Liška wrote: >> Hi. >> >> Simple transformation of switch statements where degenerated switch can be >> interpreted >> as gimple condition (or removed if having any non-default case). I >>

Re: [PATCH] Factor out division by squares and remove division around comparisons (1/2)

On Wed, Aug 30, 2017 at 11:46 AM, Jackson Woodruff wrote: > On 08/29/2017 01:13 PM, Richard Biener wrote: >> >> On Tue, Aug 29, 2017 at 1:35 PM, Jackson Woodruff >> wrote: >>> >>> Hi all, >>> >>> Apologies again to those CC'ed, who

Re: [PATCH] Expand switch statements with a single (or none) non-default case.

On Wed, Aug 30, 2017 at 2:32 PM, Martin Liška wrote: > On 08/30/2017 02:28 PM, Richard Biener wrote: >> On Wed, Aug 30, 2017 at 1:13 PM, Martin Liška wrote: >>> Hi. >>> >>> Simple transformation of switch statements where degenerated switch can be >>> interpreted

Re: [PATCH][RFC] Make expansion of balanced binary trees of switches on tree level.

On 08/30/2017 10:33 AM, Rainer Orth wrote: > Hi Martin, > >> Yes, sorry for the missing entries. Fixed and installed as r251412. >> Hopefully fall out will be small. > > there's > > UNRESOLVED: gcc.dg/tree-ssa/vrp104.c scan-tree-dump-times switchlower > "switch" 1 > > everywhere, it seems.

Re: [C++ PATCH] Make taking the address of an overloaded function a non-deduced context

On 30 August 2017 at 01:25, Ville Voutilainen wrote: > On 30 August 2017 at 01:19, Ville Voutilainen > wrote: >> 2017-08-29 Ville Voutilainen >> >> Make taking the address of an overloaded function a

Re: [PATCH] Expand switch statements with a single (or none) non-default case.

On Wed, Aug 30, 2017 at 1:13 PM, Martin Liška wrote: > Hi. > > Simple transformation of switch statements where degenerated switch can be > interpreted > as gimple condition (or removed if having any non-default case). I originally > though > that we don't have switch statements

Re: [PATCH][GCC][AARCH64]Bad code-gen for structure/block/unaligned memory access

Sure, I'll split mid-end parts off and add a test. Thanks, Tamar From: H.J. Lu Sent: Wednesday, August 30, 2017 2:16:12 PM To: Tamar Christina Cc: Richard Sandiford; GCC Patches; nd; James Greenhalgh; Richard Earnshaw; Marcus

[PATCH] rs6000_expand_binop_builtin

The patch to convert rs6000.c:rs6000_expand_binop_builtin to switch statement broke bootstrap because some of the CODE_FOR_XXX labels are not guaranteed to be defined or have unique values in all configurations. Restores bootstrap on AIX. Committed. Thanks, David *

Re: [TESTSUITE]Use strncpy instead of strcpy in testsuite/gcc.dg/memcmp-1.c

On Wed, 2017-08-30 at 10:16 +0100, Renlin Li wrote: > Hi, > > In test_driver_memcmp function, I found buf1 and buf2 is not properly > terminated with null character. > > In lib_strncmp, strcpy will be called with buf1 and buf2. > The normal implementation of strcpy function has a loop to copy >

RE: [RFC, vectorizer] Allow single element vector types for vector reduction operations

Hi Richard, > I think the issue is that with TARGET_VECTOR_MODE_SUPPORTED_P false > for V1SI you'll get a SImode vector type and the > > if (VECTOR_BOOLEAN_TYPE_P (type_in) > || VECTOR_MODE_P (TYPE_MODE (type_in))) > >check fails. Try changing that to || VECTOR_TYPE_P (type_in). >The else

Re: [TESTSUITE]Use strncpy instead of strcpy in testsuite/gcc.dg/memcmp-1.c

Hi Aaron, On 30/08/17 15:37, Aaron Sawdey wrote: On Wed, 2017-08-30 at 10:16 +0100, Renlin Li wrote: Hi, Hi, Renlin you are correct that it shouldn't be using strcpy because the string may not be null terminated. However I would suggest we use memcpy instead of strncpy. The reason is

AArch64 patch pings

Ping for a few AArch64 patches: [61/77] Use scalar_int_mode in the AArch64 port https://gcc.gnu.org/ml/gcc-patches/2017-07/msg00701.html [75/77] Use scalar_mode in the AArch64 port https://gcc.gnu.org/ml/gcc-patches/2017-07/msg00715.html [AArch64] Remove use of wider vector

Re: Improve DOM's ability to derive equivalences when traversing edges

On 08/29/2017 09:42 AM, Christophe Lyon wrote: > On 29 August 2017 at 17:28, Jeff Law wrote: >> On 08/29/2017 03:13 AM, Christophe Lyon wrote: >>> Hi Jeff, >> [ ... ] commit a370df2c52074abbb044d1921a0c7df235758050 Author: law