Re: [PATCH][GCC][Arm] Add HF modes to ANY iterators

On Thu, 14 Feb 2019 at 17:52, Tamar Christina wrote: > > Hi Kyrill, > > I couldn't find a way to actually generate this case so I have instead removed > the entry from ANY128. New patch and changelog below. > > -- > > The iterator ANY64 are used in various general split patterns and is supposed

Re: Go patch committed: Harmonize types referenced by both C and Go

This breaks non-split-stack builds. ../../../libgo/runtime/stack.c: In function 'doscanstack1': ../../../libgo/runtime/stack.c:113:18: error: passing argument 1 of 'scanstackblock' makes integer from pointer without a cast [-Werror=int-conversion] 113 | scanstackblock(bottom, (uintptr)(top

Re: [PATCH] Fix tree-loop-distribution.c ICE with -ftrapv (PR tree-optimization/89278)

On Fri, Feb 15, 2019 at 3:48 PM Jakub Jelinek wrote: > > On Fri, Feb 15, 2019 at 08:33:44AM +0100, Jakub Jelinek wrote: > > On Fri, Feb 15, 2019 at 03:25:33PM +0800, Bin.Cheng wrote: > > > So with what condition we can safely rewrite trapping operations into > > > non trapping one? Does the

[patch] Fix LRA/reload issue with -fnon-call-exceptions

Hi, this is a regression present on all active branches since the controversial get_initial_register_offset stuff was added to rtlanal.c some time ago, and visible in the testsuite on PowerPC/Linux under the form of gnat.dg/opt73.adb timing out at run time. The problem is that the compiler

Re: [PATCH][DOC] Document new features for GCC 9.

On 2/14/19, David Malcolm wrote: > On Thu, 2019-02-14 at 14:19 -0700, Martin Sebor wrote: >> On 2/13/19 6:48 AM, Martin Liška wrote: >> > Hi. >> > >> > I'm sending patch where I document changes I made during GCC 9 >> > development. I would appreciate both language and factical comments >> >

Re: [PATCH][DOC] Document new features for GCC 9.

On 2/14/19 11:37 PM, David Malcolm wrote: > On Thu, 2019-02-14 at 14:19 -0700, Martin Sebor wrote: >> On 2/13/19 6:48 AM, Martin Liška wrote: >>> Hi. >>> >>> I'm sending patch where I document changes I made during GCC 9 >>> development. I would appreciate both language and factical comments >>>

[PATCH 06/42] i386: Emulate MMX mulv4hi3 with SSE

Emulate MMX mulv4hi3 with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mulv4hi3): New. (*mmx_mulv4hi3): Also allow TARGET_MMX_WITH_SSE. Add SSE support. --- gcc/config/i386/mmx.md | 26 +++--- 1 file

[PATCH 07/42] i386: Emulate MMX smulv4hi3_highpart with SSE

Emulate MMX mulv4hi3 with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_smulv4hi3_highpart): Also allow TARGET_MMX_WITH_SSE. (*mmx_smulv4hi3_highpart): Also allow TARGET_MMX_WITH_SSE. Add SSE support. ---

[PATCH 05/42] i386: Emulate MMX plusminus/sat_plusminus with SSE

Emulate MMX plusminus/sat_plusminus with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (MMXMODEI8): Require TARGET_SSE2 for V1DI. (plusminus:mmx_3): Check TARGET_MMX_WITH_SSE. (sat_plusminus:mmx_3): Likewise.

[PATCH 09/42] i386: Emulate MMX ashr3/3 with SSE

Emulate MMX ashr3/3 with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_ashr3): Also allow TARGET_MMX_WITH_SSE. Add SSE emulation. (mmx_3): Likewise. (ashr3): New. (3): Likewise. ---

[PATCH 38/42] i386: Allow MMXMODE moves with TARGET_MMX_WITH_SSE

PR target/89021 * config/i386/mmx.md (MMXMODE:mov): Also allow TARGET_MMX_WITH_SSE. (MMXMODE:*mov_internal): Likewise. (MMXMODE:movmisalign): Likewise. --- gcc/config/i386/mmx.md | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git

[PR 89330] Avoid adding dead speculative edges to inlinig heap

Hi, Martin discovered that inliner was adding deleted call graph edges to its heap when supposedly processing newly discovered direct edges. The problem is that a new edge created in the speculation part of the indirect inlining machinery created speculative edges that were immediately

GCC 8.3 Status Report (2019-02-15)

Status == The GCC 8 branch is now frozen for blocking regressions and documentation fixes only, all changes to the branch require a RM approval now. Quality Data Priority # Change from last report --- --- P10 P2

Re: [PATCH 02/42] i386: Add mmx_nonimmediate_operand

On Fri, Feb 15, 2019 at 2:58 PM H.J. Lu wrote: > > True if the operand is a register or an nonimmediate operand when > TARGET_MMX_WITH_SSE is false. > > PR target/89021 > * config/i386/predicates.md (mmx_nonimmediate_operand): New. > --- > gcc/config/i386/predicates.md | 7

Re: [PATCH 28/42] i386: Make _mm_empty () as NOP when MMX is disabled

On Fri, Feb 15, 2019 at 3:03 PM H.J. Lu wrote: > > With SSE emulation of MMX intrinsics, we should make _mm_empty () as NOP > when MMX is disabled. > > PR target/89021 > * config/i386/mmx.md (EMMS): Also allow TARGET_MMX_WITH_SSE. > (mmx_): Generate "" only when MMX is

Bugs in extended C interop

Dear Paul, I've started putting together my observations on the current status of the F2018 C interop extensions in gfortran 9.0. See the PRs 89363, 89364, 89365, 89366: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89363 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89364

[Committed][PATCH][GCC][Arm] Remove alternative from neon_softfp_fp16 directive.

Hi All, There's a bit of a disconnect between the feature flags that don't test the fpu and ones that do when the test itself also forces an architecture. The forcing of the architecture would change the defaults and without explicitly giving the correct fpu again the test would fail. I don't

Re: [PATCH 17/42] i386: Emulate MMX mmx_pextrw with SSE

On Fri, Feb 15, 2019 at 6:03 AM H.J. Lu wrote: > > Emulate MMX mmx_pextrw with SSE. Only SSE register source operand is > allowed. > > PR target/89021 > * config/i386/mmx.md (mmx_pextrw): Add SSE emulation. > --- > gcc/config/i386/mmx.md | 16 +--- > 1 file changed,

Re: [PATCH][GCC][DOC] Remove obsolete arm and aarch64 CPU names from invoke.texi

On 19/01/2019 23:37, Gerald Pfeifer wrote: > On Thu, 10 Jan 2019, Sam Tebbs wrote: >>> I believe this should also be covered in the GCC 9 release notes >>> at https://gcc.gnu.org/gcc-9/changes.html ? >> Sorry for the late reply. My email filters seem to have stumbled a bit >> so I didn't pick

[visium] Adjust to recent assembler change

This adjusts the compiler to the assembler change I recently istalled: https://sourceware.org/ml/binutils/2019-02/msg00035.html The final.c one-liner is trivial, it changes the test to the exact condition under which the fallthrough code won't segfault. Tested on visium-elf, applied on the

[testsuite] Tweak gcc.target/sparc/struct-ret-check-1.c

It cannot pass in PIE mode. Tested on SPARC64/Linux, applied on all active branches. 2019-02-15 Eric Botcazou * gcc.target/sparc/struct-ret-check-1.c: Add -fno-pie option. -- Eric Botcazou Index: gcc.target/sparc/struct-ret-check-1.c

Re: [PATCH 37/40] i386: Allow MMX intrinsic emulation with SSE

On Thu, Feb 14, 2019 at 1:33 PM H.J. Lu wrote: > > Allow MMX intrinsic emulation with SSE/SSE2/SSSE3. Don't enable MMX ISA > by default with TARGET_MMX_WITH_SSE. > > For pr82483-1.c and pr82483-2.c, "-mssse3 -mno-mmx" compiles in 64-bit > mode since MMX intrinsics can be emulated wit SSE. > >

Re: [PATCH][DOC] Document new features for GCC 9.

On 2/14/19 10:19 PM, Martin Sebor wrote: > On 2/13/19 6:48 AM, Martin Liška wrote: >> Hi. >> >> I'm sending patch where I document changes I made during GCC 9 >> development. I would appreciate both language and factical comments >> about the patch. > > Nothing technical, just a few very minor

Re: Go patch committed: Harmonize types referenced by both C and Go

On Fri, Feb 15, 2019 at 4:03 AM Rainer Orth wrote: > > Andreas Schwab writes: > > > This breaks non-split-stack builds. > > > > ../../../libgo/runtime/stack.c: In function 'doscanstack1': > > ../../../libgo/runtime/stack.c:113:18: error: passing argument 1 of > > 'scanstackblock' makes integer

Re: [PATCH] Come up with fast {function,call}_summary classes (PR ipa/89306).

Updated version where I fixed one function comment. Martin >From fb1cf6f220d6af2c1676e58bd36b160fa8d9706b Mon Sep 17 00:00:00 2001 From: marxin Date: Mon, 11 Feb 2019 14:58:31 +0100 Subject: [PATCH] Come up with fast {function,call}_summary classes (PR ipa/89306). gcc/ChangeLog: 2019-02-13

[PATCH 25/42] i386: Emulate MMX mmx_psadbw with SSE

Emulate MMX mmx_psadbw with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_psadbw): Add SSE emulation. --- gcc/config/i386/mmx.md | 19 --- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git

[PATCH 40/42] i386: Allow MMX intrinsic emulation with SSE

Allow MMX intrinsic emulation with SSE/SSE2/SSSE3. Don't enable MMX ISA by default with TARGET_MMX_WITH_SSE. For pr82483-1.c and pr82483-2.c, "-mssse3 -mno-mmx" compiles in 64-bit mode since MMX intrinsics can be emulated wit SSE. gcc/ PR target/89021 *

[PATCH 24/42] i386: Emulate MMX mmx_uavgv4hi3 with SSE

Emulate MMX mmx_uavgv4hi3 with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_uavgv4hi3): Also check TARGET_MMX and TARGET_MMX_WITH_SSE. (*mmx_uavgv4hi3): Add SSE emulation. --- gcc/config/i386/mmx.md | 22

[PATCH 28/42] i386: Make _mm_empty () as NOP when MMX is disabled

With SSE emulation of MMX intrinsics, we should make _mm_empty () as NOP when MMX is disabled. PR target/89021 * config/i386/mmx.md (EMMS): Also allow TARGET_MMX_WITH_SSE. (mmx_): Generate "" only when MMX is enabled. --- gcc/config/i386/mmx.md | 6 -- 1 file changed,

Re: GCC 7 backport

On 8/16/18 12:18 PM, Martin Liška wrote: > Hi. > > I'm going to install one more patch. > > Martin > Hi. I'm going to install another 2 patches. Thanks, Martin >From 37023f6a8e122d325cf3e3a054511425550cb6d6 Mon Sep 17 00:00:00 2001 From: marxin Date: Fri, 15 Feb 2019 11:00:42 +0100 Subject:

Re: [PATCH, GCC] PR target/86487: fix the way 'uses_hard_regs_p' handles paradoxical subregs

Hi Vlad, On 13/02/2019 16:46, Vladimir Makarov wrote: On 2019-02-13 5:54 a.m., Andre Vieira (lists) wrote: PING. Since Jeff is away can another maintainer have a look at this please? I see the following patch Yeah I uploaded the wrong patch... sorry. See attached, including a testcase,

[PATCH] Come up with fast {function,call}_summary classes (PR ipa/89306).

Hi. The patch comes up with new summaries that use vector as underlying data structure. In order to make the code more readable I decided to factor out some common code into base classes. Patch can bootstrap on x86_64-linux-gnu and survives regression tests. I tested building Inkscape w/ LTO and

Re: [PATCH][AArch64] Use implementation namespace consistently in arm_neon.h

Ping. https://gcc.gnu.org/ml/gcc-patches/2019-02/msg00345.html Thanks, Kyrill On 2/6/19 1:52 PM, Kyrill Tkachov wrote: [resending with patch compressed] Hi all, We're somewhat inconsistent in arm_neon.h when it comes to using the implementation namespace for local identifiers. This means

[PATCH 21/42] i386: Emulate MMX mmx_umulv4hi3_highpart with SSE

Emulate MMX mmx_umulv4hi3_highpart with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_umulv4hi3_highpart): Also check TARGET_MMX and TARGET_MMX_WITH_SSE. (*mmx_umulv4hi3_highpart): Add SSE emulation. ---

[PATCH 36/42] i386: Emulate MMX abs2 with SSE

Emulate MMX abs2 with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/sse.md (abs2): Add SSE emulation. --- gcc/config/i386/sse.md | 15 +-- 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/gcc/config/i386/sse.md

[PATCH 41/42] i386: Enable TM MMX intrinsics with SSE2

This pach enables TM MMX intrinsics with SSE2 when MMX is disabled. PR target/89021 * config/i386/i386.c (bdesc_tm): Enable MMX intrinsics with SSE2. --- gcc/config/i386/i386.c | 16 1 file changed, 8 insertions(+), 8 deletions(-) diff --git

[PATCH 23/42] i386: Emulate MMX mmx_uavgv8qi3 with SSE

Emulate MMX mmx_uavgv8qi3 with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_uavgv8qi3): Also check TARGET_MMX and TARGET_MMX_WITH_SSE. (*mmx_uavgv8qi3): Add SSE emulation. --- gcc/config/i386/mmx.md | 21

[PATCH 27/42] i386: Emulate MMX umulv1siv1di3 with SSE2

Emulate MMX umulv1siv1di3 with SSE2. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (sse2_umulv1siv1di3): Add SSE emulation support. (*sse2_umulv1siv1di3): Add SSE2 emulation. --- gcc/config/i386/mmx.md | 22

[PATCH 32/42] i386: Emulate MMX ssse3_pmulhrswv4hi3 with SSE

Emulate MMX ssse3_pmulhrswv4hi3 with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/sse.md (*ssse3_pmulhrswv4hi3): Add SSE emulation. --- gcc/config/i386/sse.md | 20 +--- 1 file changed, 13 insertions(+), 7 deletions(-) diff

[PATCH 29/42] i386: Emulate MMX ssse3_phwv4hi3 with SSE

Emulate MMX ssse3_phwv4hi3 with SSE by moving bits 64:95 to bits 32:63 in SSE register. Only SSE register source operand is allowed. PR target/89021 * config/i386/sse.md (ssse3_phwv4hi3): Changed to define_insn_and_split to support SSE emulation. ---

RE: [Committed][PATCH][GCC][Arm] Fix test directive

Hi Christoph, > > On Thu, 14 Feb 2019 at 19:27, Tamar Christina > wrote: > > > > Hi All, > > > > This patch fixes a failing testcase due to a use of dg-options instead > > of dg-additional-options. > > > Makes sense. > It doesn't fail in any of the configurations I test though, in what case do

Re: Go patch committed: Harmonize types referenced by both C and Go

Andreas Schwab writes: > This breaks non-split-stack builds. > > ../../../libgo/runtime/stack.c: In function 'doscanstack1': > ../../../libgo/runtime/stack.c:113:18: error: passing argument 1 of > 'scanstackblock' makes integer from pointer without a cast > [-Werror=int-conversion] > 113 |

[PATCH 13/42] i386: Emulate MMX vec_dupv2si with SSE

Emulate MMX vec_dupv2si with SSE. Add the "Yw" constraint to allow broadcast from integer register for AVX512BW with TARGET_AVX512VL. Only SSE register source operand is allowed. PR target/89021 * config/i386/constraints.md (Yw): New constraint. * config/i386/mmx.md

[PATCH 18/42] i386: Emulate MMX mmx_pinsrw with SSE

Emulate MMX mmx_pinsrw with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_pinsrw): Also check TARGET_MMX and TARGET_MMX_WITH_SSE. (*mmx_pinsrw): Add SSE emulation. --- gcc/config/i386/mmx.md | 33

[PATCH 12/42] i386: Emulate MMX mmx_eq/mmx_gt3 with SSE

Emulate MMX mmx_eq/mmx_gt3 with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_eq3): Also allow TARGET_MMX_WITH_SSE. (*mmx_eq3): Also allow TARGET_MMX_WITH_SSE. Add SSE support. (mmx_gt3): Likewise. ---

[PATCH 11/42] i386: Emulate MMX mmx_andnot3 with SSE

Emulate MMX mmx_andnot3 with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_andnot3): Also allow TARGET_MMX_WITH_SSE. Add SSE support. --- gcc/config/i386/mmx.md | 18 +++--- 1 file changed, 11 insertions(+), 7

[PATCH 37/42] Prevent allocation of MMX registers with TARGET_MMX_WITH_SSE

From: Uros Bizjak 2019-02-14 Uroš Bizjak PR target/89021 * config/i386/i386.md (*zero_extendsidi2): Add mmx_isa attribute. * config/i386/sse.md (*vec_concatv2sf_sse4_1): Ditto. (*vec_concatv2sf_sse): Ditto. (*vec_concatv2si_sse4_1): Ditto.

[PATCH 17/42] i386: Emulate MMX mmx_pextrw with SSE

Emulate MMX mmx_pextrw with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_pextrw): Add SSE emulation. --- gcc/config/i386/mmx.md | 16 +--- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git

[PATCH 39/42] i386: Allow MMX vector expanders with TARGET_MMX_WITH_SSE

PR target/89021 * config/i386/i386.c (ix86_expand_vector_init_duplicate): Set mmx_ok to true if TARGET_MMX_WITH_SSE is true. (ix86_expand_vector_init_one_nonzero): Likewise. (ix86_expand_vector_init_one_var): Likewise.

[PATCH 19/42] i386: Emulate MMX V4HI smaxmin/V8QI umaxmin with SSE

Emulate MMX V4HI smaxmin/V8QI umaxmin with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_v4hi3): Also check TARGET_MMX and TARGET_MMX_WITH_SSE. (mmx_v8qi3): Likewise. (smaxmin:v4hi3): New.

[PATCH 22/42] i386: Emulate MMX maskmovq with SSE2 maskmovdqu

Emulate MMX maskmovq with SSE2 maskmovdqu for TARGET_MMX_WITH_SSE by zero-extending source and mask operands to 128 bits. Handle unmapped bits 64:127 at memory address by adjusting source and mask operands together with memory address. PR target/89021 * config/i386/xmmintrin.h:

[PATCH 35/42] i386: Emulate MMX ssse3_palignrdi with SSE

Emulate MMX version of palignrq with SSE version by concatenating 2 64-bit MMX operands into a single 128-bit SSE operand, followed by SSE psrldq. Only SSE register source operand is allowed. PR target/89021 * config/i386/sse.md (ssse3_palignrdi): Changed to

Re: [omp] Move NE_EXPR handling to omp_adjust_for_condition

Ping please, the issue is now PR 89302. Thanks, Martin On Fri, Feb 01 2019, Martin Jambor wrote: > Hi, > > even after the two previous HSA fixes, there is still one remining > libgomp failure in the testsuite when run on an HSA-enabled APU. The > problem is that grid calculation does not work

Re: Go patch committed: Harmonize types referenced by both C and Go

On Fri, Feb 15, 2019 at 12:15 AM Andreas Schwab wrote: > > This breaks non-split-stack builds. > > ../../../libgo/runtime/stack.c: In function 'doscanstack1': > ../../../libgo/runtime/stack.c:113:18: error: passing argument 1 of > 'scanstackblock' makes integer from pointer without a cast >

[PATCH 20/42] i386: Emulate MMX mmx_pmovmskb with SSE

Emulate MMX mmx_pmovmskb with SSE by zero-extending result of SSE pmovmskb from QImode to SImode. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_pmovmskb): Changed to define_insn_and_split to support SSE emulation. ---

[PATCH 10/42] i386: Emulate MMX 3 with SSE

Emulate MMX 3 with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (any_logic:3): New. (any_logic:*mmx_3): Also allow TARGET_MMX_WITH_SSE. Add SSE support. --- gcc/config/i386/mmx.md | 27 --- 1 file

[PATCH 30/42] i386: Emulate MMX ssse3_phdv2si3 with SSE

Emulate MMX ssse3_phdv2si3 with SSE by moving bits 64:95 to bits 32:63 in SSE register. Only SSE register source operand is allowed. PR target/89021 * config/i386/sse.md (ssse3_phdv2si3): Changed to define_insn_and_split to support SSE emulation. ---

RE: [PATCH][GCC][Arm] Add HF modes to ANY iterators

Hi Christoph, > > Looking at the logs, I see strange command lines when trying to compile > arm_neon_softfp_fp16_ok: > /aci-gcc-fsf/builds/gcc-fsf-gccsrc/obj-arm-none-linux-gnueabi/gcc3/gcc/xgcc > -B/aci-gcc-fsf/builds/gcc-fsf-gccsrc/obj-arm-none-linux-gnueabi/gcc3/gcc/ >

[PATCH 01/42] i386: Allow MMX register modes in SSE registers

In 64-bit mode, SSE2 can be used to emulate MMX instructions without 3DNOW. We can use SSE2 to support MMX register modes. PR target/89021 * config/i386/i386-c.c (ix86_target_macros_internal): Define __MMX_WITH_SSE__ for TARGET_MMX_WITH_SSE. * config/i386/i386.c

[PATCH 02/42] i386: Add mmx_nonimmediate_operand

True if the operand is a register or an nonimmediate operand when TARGET_MMX_WITH_SSE is false. PR target/89021 * config/i386/predicates.md (mmx_nonimmediate_operand): New. --- gcc/config/i386/predicates.md | 7 +++ 1 file changed, 7 insertions(+) diff --git

[PATCH 00/40] V6: Emulate MMX intrinsics with SSE

On x86-64, since __m64 is returned and passed in XMM registers, we can emulate MMX intrinsics with SSE instructions. To support it, we added #define TARGET_MMX_WITH_SSE (TARGET_64BIT && TARGET_SSE2) ;; Define instruction set of MMX instructions (define_attr "mmx_isa"

[PATCH 08/42] i386: Emulate MMX mmx_pmaddwd with SSE

Emulate MMX pmaddwd with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_pmaddwd): Also allow TARGET_MMX_WITH_SSE. (*mmx_pmaddwd): Also allow TARGET_MMX_WITH_SSE. Add SSE support. --- gcc/config/i386/mmx.md | 21

[PATCH 04/42] i386: Emulate MMX punpcklXX/punpckhXX with SSE punpcklXX

Emulate MMX punpcklXX/punpckhXX with SSE punpcklXX. For MMX punpckhXX, move bits 64:127 to bits 0:63 in SSE register. Only SSE register source operand is allowed. PR target/89021 * config/i386/i386-protos.h (ix86_split_mmx_punpck): New prototype. *

[PATCH 03/42] i386: Emulate MMX packsswb/packssdw/packuswb with SSE2

Emulate MMX packsswb/packssdw/packuswb with SSE packsswb/packssdw/packuswb plus moving bits 64:95 to bits 32:63 in SSE register. Only SSE register source operand is allowed. 2019-02-08 H.J. Lu Uros Bizjak PR target/89021 * config/i386/i386-protos.h

libgo patch committed: Add S/390 support to internal/cpu package

This patch by Robin Dapp adds S/390 support to the internal/cpu package. This partially addresses PR 89123. I bootstrapped it on x86_64-pc-linux-gnu, which means little. Committed to mainline. Ian Index: gcc/go/gofrontend/MERGE

[PATCH, i386]: Add missing TARGET_FPMATH_DEFAULT_P to darwin.h

Darwin defines its own TARGET_FPMATH_DEFAULT, which should be accompanied by corresponding TARGET_FPMATH_DEFAULT_P. Patch adds missing define. While looking around, I also fixed various whitespace issues in the header. BTW: The header file still defines TARGET_64BIT which is horribly out of

Re: [PATCH 00/40] V6: Emulate MMX intrinsics with SSE

On Fri, Feb 15, 2019 at 9:50 AM Uros Bizjak wrote: > > On Fri, Feb 15, 2019 at 2:58 PM H.J. Lu wrote: > > > > On x86-64, since __m64 is returned and passed in XMM registers, we can > > emulate MMX intrinsics with SSE instructions. To support it, we added > > > > #define TARGET_MMX_WITH_SSE

Re: [PATCH 00/40] V6: Emulate MMX intrinsics with SSE

On Fri, Feb 15, 2019 at 7:20 PM H.J. Lu wrote: > > I went through the code again, and looks OK in general, modulo > > mmx_nonimmediate_operand issue and a couple of minor issues. > > > > Please substitute nonimmediate_operand predicate with > > mmx_nonimmediate_operand in expanders and insn

Re: libgo patch committed: Add S/390 support to internal/cpu package

On 15.02.19 15:52, Ian Lance Taylor wrote: > This patch by Robin Dapp adds S/390 support to the internal/cpu > package. This partially addresses PR 89123. I bootstrapped it on > x86_64-pc-linux-gnu, which means little. Committed to mainline. fails in the -m31 multilib variant with libtool:

Re: [PATCH 00/40] V6: Emulate MMX intrinsics with SSE

On Fri, Feb 15, 2019 at 2:58 PM H.J. Lu wrote: > > On x86-64, since __m64 is returned and passed in XMM registers, we can > emulate MMX intrinsics with SSE instructions. To support it, we added > > #define TARGET_MMX_WITH_SSE (TARGET_64BIT && TARGET_SSE2) > > ;; Define instruction set of MMX

[testsuite] Small tweaks for Visium

The only interesting one is gcc.dg/tree-ssa/pr84859.c: for it to pass, the undocumented -ftree-cselim must be enabled, which is done automatically only on targets with conditional moves, what the Visium is not. Tested on visium-elf, applied on the mainline and 8 branch. 2019-02-15 Eric

Re: Fortran vector math header

On 2/14/19 10:13 PM, Steve Ellcey wrote: > On Wed, 2019-02-13 at 12:34 +0100, Martin Liška wrote: >> May I please ping this so that we can reach mainline soon? >> >> Thanks, >> Martin > > Martin, I can't approve this patch but I can say that I have used it on > Aarch64 and created a follow up

[PATCH 16/42] i386: Emulate MMX sse_cvtpi2ps with SSE

Emulate MMX sse_cvtpi2ps with SSE2 cvtdq2ps, preserving upper 64 bits of destination XMM register. Only SSE register source operand is allowed. PR target/89021 * config/i386/sse.md (sse_cvtpi2ps): Changed to define_insn_and_split. Also allow TARGET_MMX_WITH_SSE. Add

[PATCH 31/42] i386: Emulate MMX ssse3_pmaddubsw with SSE

Emulate MMX ssse3_pmaddubsw with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/sse.md (ssse3_pmaddubsw): Add SSE emulation. --- gcc/config/i386/sse.md | 18 +++--- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git

[PATCH 14/42] i386: Emulate MMX pshufw with SSE

Emulate MMX pshufw with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_pshufw): Also check TARGET_MMX and TARGET_MMX_WITH_SSE. (mmx_pshufw_1): Add SSE emulation. (*vec_dupv4hi): Changed to define_insn_and_split

[PATCH 26/42] i386: Emulate MMX movntq with SSE2 movntidi

Emulate MMX movntq with SSE2 movntidi. Only register source operand is allowed. PR target/89021 * config/i386/mmx.md (sse_movntq): Add SSE2 emulation. --- gcc/config/i386/mmx.md | 14 +- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git

[PATCH 34/42] i386: Emulate MMX ssse3_psign3 with SSE

Emulate MMX ssse3_psign3 with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/sse.md (ssse3_psign3): Add SSE emulation. --- gcc/config/i386/sse.md | 18 +++--- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git

[PATCH 15/42] i386: Emulate MMX sse_cvtps2pi/sse_cvttps2pi with SSE

Emulate MMX sse_cvtps2pi/sse_cvttps2pi with SSE. PR target/89021 * config/i386/mmx.md (sse_cvtps2pi): Add SSE emulation. (sse_cvttps2pi): Likewise. --- gcc/config/i386/sse.md | 30 ++ 1 file changed, 18 insertions(+), 12 deletions(-) diff

[PATCH 33/42] i386: Emulate MMX pshufb with SSE version

Emulate MMX version of pshufb with SSE version by masking out the bit 3 of the shuffle control byte. Only SSE register source operand is allowed. PR target/89021 * config/i386/sse.md (ssse3_pshufbv8qi3): Changed to define_insn_and_split. Also allow TARGET_MMX_WITH_SSE.

Re: Fortran vector math header

On Tue, Feb 05, 2019 at 01:47:57PM +0100, Martin Liška wrote: > > gcc/fortran/ChangeLog: > > 2019-01-24 Martin Liska > > * decl.c (gfc_match_gcc_builtin): Add support for filtering > of builtin directive based on multilib ABI name. > > gcc/testsuite/ChangeLog: > > 2019-01-24

[PATCH 05/42] i386: Emulate MMX mulv4hi3 with SSE

Emulate MMX mulv4hi3 with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_mulv4hi3): Also allow TARGET_MMX_WITH_SSE. (mulv4hi3): New. (*mmx_mulv4hi3): Also allow TARGET_MMX_WITH_SSE. Add SSE support. ---

[PATCH 23/42] i386: Emulate MMX mmx_uavgv4hi3 with SSE

Emulate MMX mmx_uavgv4hi3 with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_uavgv4hi3): Also check TARGET_MMX and TARGET_MMX_WITH_SSE. (*mmx_uavgv4hi3): Add SSE emulation. --- gcc/config/i386/mmx.md | 26

[PATCH 13/42] i386: Emulate MMX pshufw with SSE

Emulate MMX pshufw with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_pshufw): Also check TARGET_MMX and TARGET_MMX_WITH_SSE. (mmx_pshufw_1): Add SSE emulation. (*vec_dupv4hi): Changed to define_insn_and_split

[PATCH 14/42] i386: Emulate MMX sse_cvtps2pi/sse_cvttps2pi with SSE

Emulate MMX sse_cvtps2pi/sse_cvttps2pi with SSE. PR target/89021 * config/i386/sse.md (sse_cvtps2pi): Add SSE emulation. (sse_cvttps2pi): Likewise. --- gcc/config/i386/sse.md | 30 ++ 1 file changed, 18 insertions(+), 12 deletions(-) diff

[PATCH 20/42] i386: Emulate MMX mmx_umulv4hi3_highpart with SSE

Emulate MMX mmx_umulv4hi3_highpart with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_umulv4hi3_highpart): Also check TARGET_MMX and TARGET_MMX_WITH_SSE. (*mmx_umulv4hi3_highpart): Add SSE emulation. ---

[PATCH 17/42] i386: Emulate MMX mmx_pinsrw with SSE

Emulate MMX mmx_pinsrw with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_pinsrw): Also check TARGET_MMX and TARGET_MMX_WITH_SSE. (*mmx_pinsrw): Add SSE emulation. --- gcc/config/i386/mmx.md | 33

[PATCH 15/42] i386: Emulate MMX sse_cvtpi2ps with SSE

Emulate MMX sse_cvtpi2ps with SSE2 cvtdq2ps, preserving upper 64 bits of destination XMM register. Only SSE register source operand is allowed. PR target/89021 * config/i386/sse.md (sse_cvtpi2ps): Changed to define_insn_and_split. Also allow TARGET_MMX_WITH_SSE. Add

[PATCH 41/42] i386: Enable TM MMX intrinsics with SSE2

This pach enables TM MMX intrinsics with SSE2 when MMX is disabled. PR target/89021 * config/i386/i386.c (bdesc_tm): Enable MMX intrinsics with SSE2. --- gcc/config/i386/i386.c | 16 1 file changed, 8 insertions(+), 8 deletions(-) diff --git

[PATCH 21/42] i386: Emulate MMX maskmovq with SSE2 maskmovdqu

Emulate MMX maskmovq with SSE2 maskmovdqu for TARGET_MMX_WITH_SSE by zero-extending source and mask operands to 128 bits. Handle unmapped bits 64:127 at memory address by adjusting source and mask operands together with memory address. PR target/89021 * config/i386/xmmintrin.h:

[PATCH 35/42] i386: Emulate MMX abs2 with SSE

Emulate MMX abs2 with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/sse.md (abs2): Add SSE emulation. --- gcc/config/i386/sse.md | 15 +-- 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/gcc/config/i386/sse.md

[PATCH 24/42] i386: Emulate MMX mmx_psadbw with SSE

Emulate MMX mmx_psadbw with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_psadbw): Add SSE emulation. --- gcc/config/i386/mmx.md | 19 --- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git

[PATCH 31/42] i386: Emulate MMX ssse3_pmulhrswv4hi3 with SSE

Emulate MMX ssse3_pmulhrswv4hi3 with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/sse.md (*ssse3_pmulhrswv4hi3): Add SSE emulation. --- gcc/config/i386/sse.md | 20 +--- 1 file changed, 13 insertions(+), 7 deletions(-) diff

[PATCH 25/42] i386: Emulate MMX movntq with SSE2 movntidi

Emulate MMX movntq with SSE2 movntidi. Only register source operand is allowed. PR target/89021 * config/i386/mmx.md (sse_movntq): Add SSE2 emulation. --- gcc/config/i386/mmx.md | 14 +- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git

[PATCH 38/42] i386: Allow MMXMODE moves with TARGET_MMX_WITH_SSE

PR target/89021 * config/i386/mmx.md (MMXMODE:mov): Also allow TARGET_MMX_WITH_SSE. (MMXMODE:*mov_internal): Likewise. (MMXMODE:movmisalign): Likewise. --- gcc/config/i386/mmx.md | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git

Re: [PATCH 00/40] V6: Emulate MMX intrinsics with SSE

On Fri, Feb 15, 2019 at 9:50 AM Uros Bizjak wrote: > > On Fri, Feb 15, 2019 at 2:58 PM H.J. Lu wrote: > > > > On x86-64, since __m64 is returned and passed in XMM registers, we can > > emulate MMX intrinsics with SSE instructions. To support it, we added > > > > #define TARGET_MMX_WITH_SSE

[testsuite] Couple of g++.dg/asan tweaks

One of the tests in g++.dg/asan/asan_oob_test.cc uses unaligned memory accesses and g++.dg/asan/function-argument-3.C assumes a specific kind of calling conventions for vectors. Tested on SPARC64/Linux, applied on the mainline. 2019-02-15 Eric Botcazou *

[PATCH 06/42] i386: Emulate MMX smulv4hi3_highpart with SSE

Emulate MMX mulv4hi3 with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_smulv4hi3_highpart): Also allow TARGET_MMX_WITH_SSE. (*mmx_smulv4hi3_highpart): Also allow TARGET_MMX_WITH_SSE. Add SSE support. ---

[PATCH 09/42] i386: Emulate MMX 3 with SSE

Emulate MMX 3 with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (any_logic:mmx_3): Also allow TARGET_MMX_WITH_SSE. (any_logic:3): New. (any_logic:*mmx_3): Also allow TARGET_MMX_WITH_SSE. Add SSE support.

[PATCH 07/42] i386: Emulate MMX mmx_pmaddwd with SSE

Emulate MMX pmaddwd with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_pmaddwd): Also allow TARGET_MMX_WITH_SSE. (*mmx_pmaddwd): Also allow TARGET_MMX_WITH_SSE. Add SSE support. --- gcc/config/i386/mmx.md | 25

[PATCH 18/42] i386: Emulate MMX V4HI smaxmin/V8QI umaxmin with SSE

Emulate MMX V4HI smaxmin/V8QI umaxmin with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_v4hi3): Also check TARGET_MMX and TARGET_MMX_WITH_SSE. (mmx_v8qi3): Likewise. (smaxmin:v4hi3): New.

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