Re: [PATCH][middle-end][i386][version 3]Add -fzero-call-used-regs=[skip|used-gpr-arg|used-arg|all-arg|used-gpr|all-gpr|used|all]

> On Oct 21, 2020, at 3:03 AM, Uros Bizjak wrote: > > On Wed, Oct 21, 2020 at 9:18 AM Uros Bizjak > wrote: >> >> On Tue, Oct 20, 2020 at 10:04 PM Qing Zhao wrote: >> >>> +/* Check whether the register REGNO should be zeroed on X86. >>> + When ALL_SSE_ZEROED is

Increase inlining limits for inline functions with builtin_constant_p on parameter

Hi, this patch implements heuristics that increases inline limits (by the hints mechanism) for inline functions that use builtin_constant_p on parameter. Those are very likely intended to be always inlined and simplify after inlining. The PR is about a function that we used to inline with

[PATCH] x86: Allow configuring with --with-arch_64=x86-64-v[234]

On Wed, Sep 30, 2020 at 06:06:31PM +0200, Florian Weimer wrote: > --- a/gcc/common/config/i386/i386-common.c > +++ b/gcc/common/config/i386/i386-common.c > @@ -1795,9 +1795,13 @@ const pta processor_alias_table[] = > PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR, 0, P_NONE}, >

[committed] libstdc++: Make structured bindings always work for subranges [PR 97512]

The definition of ranges::subrange was moved to the new header so that it could be used in without including the whole of . However, the tuple-like support that enables subrange to be used with structured bindings was left in . This is arguably conforming (to use a subrange you should include )

Re: [PATCH 1/2] [target 87767] Refactor AVX512 broadcast patterns with speical memory constraint.

On 2020-10-20 10:11 p.m., Hongtao Liu wrote: Changed, and it passed the i386/x86-64 regression test. Update patch. Thank you, Hongtao.  This patch is ok for the trunk.

[patch] vxworks: Remove interfering default #undefs from vx-common.h

This patch removes the #undef issued for LIB_SPEC and LINK_SPEC in vx-common.h, which all the ports do on their own and which impairs the bi-arch’d ppc*-vx7r2 targets, relying on linux64 definitions. Tested together with the previous changes posted for the newly introduced powerpc ports.

Re: [PATCH] x86: Allow configuring with --with-arch_64=x86-64-v[234]

* Jakub Jelinek: > On Wed, Sep 30, 2020 at 06:06:31PM +0200, Florian Weimer wrote: >> --- a/gcc/common/config/i386/i386-common.c >> +++ b/gcc/common/config/i386/i386-common.c >> @@ -1795,9 +1795,13 @@ const pta processor_alias_table[] = >> PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE |

[PATCH] phiopt: Optimize x ? __builtin_clz (x) : 32 in GIMPLE [PR97503]

Hi! While we have at the RTL level noce_try_ifelse_collapse combined with simplify_cond_clz_ctz, that optimization doesn't always trigger because e.g. on powerpc there is an define_insn to compare a reg against zero and copy that register to another one and so we end up with a different pseudo in

Re: [PATCH][PR 97506] Simplify trivial vcond_expr in expander.

On Wed, Oct 21, 2020 at 5:07 PM Jakub Jelinek wrote: > > On Wed, Oct 21, 2020 at 02:29:07PM +0800, Hongtao Liu via Gcc-patches wrote: > > gcc/ChangeLog: > > > > PR target/97506 > > * config/i386/i386-expand.c (ix86_expand_sse_movcc): Move > > op_true to dest directly When

[PATCH] SLP: Move load/store-lanes check till late

Hi All, This moves the code that checks for load/store lanes further in the pipeline and places it after slp_optimize. This would allow us to perform optimizations on the SLP tree and only bail out if we really have a permute. With this change it allows us to handle permutes such as {1,1,1,1}

Re: PING [PATCH] Enable GCC support for Intel Key Locker extension

On Wed, Oct 21, 2020 at 11:11 AM Hongyu Wang wrote: > > Hi, > > > IIRC, adding a new regclass is O(n^2), so it should be avoided. I > > think that the new patterns should follow the same path as vzeroall > > and vzeroupper patterns, where we emit the pattern with explicit hard > > regs. > > > >

Re: PING [PATCH] Enable GCC support for Intel Key Locker extension

On Wed, Oct 21, 2020 at 1:48 PM Uros Bizjak wrote: > > On Wed, Oct 21, 2020 at 11:11 AM Hongyu Wang wrote: > > > > Hi, > > > > > IIRC, adding a new regclass is O(n^2), so it should be avoided. I > > > think that the new patterns should follow the same path as vzeroall > > > and vzeroupper

Re: [PATCH] LTO: get_section: add new argument

On 10/21/20 1:17 PM, Martin Liška wrote: On 10/21/20 12:06 PM, Jan Hubicka wrote: I think the streaming should happen only from ipa-fnsummary. Oriignally ipa-prop was ipa-cp only, then indirect inlining was added, but these days we have specialized analysis pass and thus ipa-prop should be

Re: [PATCH] LTO: get_section: add new argument

On 10/21/20 12:06 PM, Jan Hubicka wrote: I think the streaming should happen only from ipa-fnsummary. Oriignally ipa-prop was ipa-cp only, then indirect inlining was added, but these days we have specialized analysis pass and thus ipa-prop should be intergrated to it. All right, there's a WIP

[PATCH] openmp: Change omp_get_initial_device () to match OpenMP 5.1 requirements

On Thu, Oct 15, 2020 at 01:02:29PM +0200, Jakub Jelinek via Gcc-patches wrote: > Therefore, I think until omp_get_initial_device () value is changed, we The following so far untested patch implements that change. OpenMP 4.5 said for omp_get_initial_device: The value of the device number is

[RFC2][PATCH] SLP vectorize across PHI nodes

This enables SLP build to handle PHI nodes in full, continuing the SLP build to non-backedges. For loop vectorization this enables outer loop vectorization of nested SLP cycles and for BB vectorization this enables vectorization of PHIs at CFG merges. Vectorized backedge defs are now filled

[Patch, committed] Fortran: class.c - update vtable comment

I was confused as I saw _deallocate – but didn't show up in the big comment at the beginning of class.c. Hence, I added it. Committed as r11-4186-g310fe80babe04ccb7d2e15c8fca7dc98180701a8 but if you have have follow-up suggestions, we can surely change it. Tobias - Mentor

Re: [PATCH] [PR rtl-optimization/97249]Simplify vec_select of paradoxical subreg.

Hongtao Liu writes: > + poly_uint64 nunits > + = GET_MODE_NUNITS (GET_MODE (SUBREG_REG (trueop0))); > + rtx par = trueop1; > + for (int i = 0; i != l1; i++) > + { > + rtx idx = XVECEXP (trueop1, 0, i); > + if

Re: [PATCH] arm: Fix multiple inheritance thunks for thumb-1 with -mpure-code

On 21/10/2020 16:49, Christophe Lyon via Gcc-patches wrote: > On Tue, 20 Oct 2020 at 13:25, Richard Earnshaw > wrote: >> >> On 20/10/2020 12:22, Richard Earnshaw wrote: >>> On 19/10/2020 17:32, Christophe Lyon via Gcc-patches wrote: On Mon, 19 Oct 2020 at 16:39, Richard Earnshaw wrote:

Re: [Ada] Improve precision of Ada.Directories.Modification_Time

Arnaud Charlet wrote: This patch breaks bootstrap on Darwin platforms. Pierre-Marie de Rodat wrote: The modification file time precision now defined by OS. Tested on x86_64-pc-linux-gnu, committed on trunk gcc/ada/ * adaint.c (__gnat_file_time): New routine.

Re: [Ada] Improve precision of Ada.Directories.Modification_Time

> >What about instead putting above extern long long __gnat_file_time the > >following: > > > >#if __APPLE__ > >#define st_mtim st_mtimespec > >#define st_atim st_atimespec > >#endif > > > >To avoid having the two (nested) #if __APPLE__ and keep the code easier two => three :-) > >to follow? >

Re: [PATCH][middle-end][i386][version 3]Add -fzero-call-used-regs=[skip|used-gpr-arg|used-arg|all-arg|used-gpr|all-gpr|used|all]

Qing Zhao writes: >>> + /* For each of the hard registers, check to see whether we should zero >>> it if: >>> + 1. it is a call-used-registers; >>> + and 2. it is not a fixed-registers; >>> + and 3. it is not live at the return of the routine; >>> + and 4. it is general registor if gpr_only

Re: [PATCH][middle-end][i386][version 3]Add -fzero-call-used-regs=[skip|used-gpr-arg|used-arg|all-arg|used-gpr|all-gpr|used|all]

On Wed, Oct 21, 2020 at 4:45 PM Qing Zhao wrote: > > > > On Oct 21, 2020, at 3:03 AM, Uros Bizjak wrote: > > On Wed, Oct 21, 2020 at 9:18 AM Uros Bizjak wrote: > > > On Tue, Oct 20, 2020 at 10:04 PM Qing Zhao wrote: > > +/* Check whether the register REGNO should be zeroed on X86. > + When

Re: [PATCH] x86: Allow configuring with --with-arch_64=x86-64-v[234]

On Wed, Oct 21, 2020 at 5:15 PM Jakub Jelinek wrote: > > On Wed, Sep 30, 2020 at 06:06:31PM +0200, Florian Weimer wrote: > > --- a/gcc/common/config/i386/i386-common.c > > +++ b/gcc/common/config/i386/i386-common.c > > @@ -1795,9 +1795,13 @@ const pta processor_alias_table[] = > > PTA_MMX |

Re: [PATCH] [PR rtl-optimization/97249]Simplify vec_select of paradoxical subreg.

On Wed, Oct 21, 2020 at 04:43:29PM +0100, Richard Sandiford wrote: > Hongtao Liu writes: > > + poly_uint64 nunits > > + = GET_MODE_NUNITS (GET_MODE (SUBREG_REG (trueop0))); > > + rtx par = trueop1; > > + for (int i = 0; i != l1; i++) > > + { > > +

Re: [PATCH] c++: Handle RANGE_EXPR indexes in init_subob_ctx [PR97328]

On Thu, 8 Oct 2020, Patrick Palka wrote: > In the testcase below, we're ICEing during constexpr evaluation of the > CONSTRUCTOR {.data={{}, [1 ... 7]={}}} of type 'vector'. The apparently > unique thing about this CONSTRUCTOR is that it has a RANGE_EXPR index > whose corresponding sub-aggregate

Re: [PATCH][middle-end][i386][version 3]Add -fzero-call-used-regs=[skip|used-gpr-arg|used-arg|all-arg|used-gpr|all-gpr|used|all]

Got it. thanks. Qing > On Oct 21, 2020, at 10:47 AM, Richard Sandiford > wrote: > > Qing Zhao writes: + /* For each of the hard registers, check to see whether we should zero it if: + 1. it is a call-used-registers; + and 2. it is not a fixed-registers; + and

Re: [PATCH] arm: Fix multiple inheritance thunks for thumb-1 with -mpure-code

On Tue, 20 Oct 2020 at 13:25, Richard Earnshaw wrote: > > On 20/10/2020 12:22, Richard Earnshaw wrote: > > On 19/10/2020 17:32, Christophe Lyon via Gcc-patches wrote: > >> On Mon, 19 Oct 2020 at 16:39, Richard Earnshaw > >> wrote: > >>> > >>> On 12/10/2020 08:59, Christophe Lyon via Gcc-patches

Re: [PATCH] arm: Fix multiple inheritance thunks for thumb-1 with -mpure-code

On Wed, 21 Oct 2020 at 18:07, Richard Earnshaw wrote: > > On 21/10/2020 16:49, Christophe Lyon via Gcc-patches wrote: > > On Tue, 20 Oct 2020 at 13:25, Richard Earnshaw > > wrote: > >> > >> On 20/10/2020 12:22, Richard Earnshaw wrote: > >>> On 19/10/2020 17:32, Christophe Lyon via Gcc-patches

Re: [Ada] Improve precision of Ada.Directories.Modification_Time

Hi Folks, This patch breaks bootstrap on Darwin platforms. Pierre-Marie de Rodat wrote: > The modification file time precision now defined by OS. > > Tested on x86_64-pc-linux-gnu, committed on trunk > > gcc/ada/ > > * adaint.c (__gnat_file_time): New routine. >

[PATCH] c++: constexpr evaluation and bare EMPTY_CLASS_EXPR [PR96575]

In the testcase below, folding of the initializer for 'ret' inside the instantiated f::lambda ends up yielding an initializer for which potential_constant_expression returns false. This causes finish_function to mark the lambda as non-constexpr, which ultimately causes us to reject 'f(g)' as a

Re: [Ada] Improve precision of Ada.Directories.Modification_Time

> This patch breaks bootstrap on Darwin platforms. > > Pierre-Marie de Rodat wrote: > > > The modification file time precision now defined by OS. > > > > Tested on x86_64-pc-linux-gnu, committed on trunk > > > > gcc/ada/ > > > > * adaint.c (__gnat_file_time): New routine. > >

Re: [PATCH][middle-end][i386][version 3]Add -fzero-call-used-regs=[skip|used-gpr-arg|used-arg|all-arg|used-gpr|all-gpr|used|all]

> On Oct 21, 2020, at 11:09 AM, Uros Bizjak wrote: > > On Wed, Oct 21, 2020 at 4:45 PM Qing Zhao wrote: >> >> >> >> -- q -- >> The CPU shall be in x87 mode upon entry to a function. Therefore, >> every function that uses the MMX registers is required to issue an >> emms or femms

[PATCH] libstdc++: Add c++2a

From: Thomas Rodgers libstdc++/Changelog: libstdc++-v3/doc/doxygen/user.cfg.in (INPUT): Add new header. libstdc++-v3/include/Makefile.am (std_headers): Add new header. libstdc++-v3/include/Makefile.in: Regenerate. libstdc++-v3/include/precompiled/stdc++.h: Include

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