[PATCH] RISC-V: Optimized for strided load/store with stride == element width[PR111450]

From: xuli When stride == element width, vlsse should be optimized into vle.v. vsse should be optimized into vse.v. PR target/111450 gcc/ChangeLog: *config/riscv/constraints.md (c01): const_int 1. (c02): const_int 2. (c04): const_int 4. (c08): const_int

Re: Re: [PATCH] RISC-V: Optimized for strided load/store with stride == element width[PR111450]

Committed, thanks Juzhe. -- Li Xu >Thanks a lot. LGTM. > > > >juzhe.zh...@rivai.ai > >From: Li Xu >Date: 2023-09-21 11:12 >To: gcc-patches >CC: kito.cheng; palmer; juzhe.zhong; xuli >Subject: [PATCH] RISC-V: Optimized for strided load/store with stride == >element width[PR111450]

Re: [PATCH][_GLIBCXX_INLINE_VERSION] Fix

Tests were successful, ok to commit ? On 20/09/2023 19:51, François Dumont wrote: libstdc++: [_GLIBCXX_INLINE_VERSION] Add handle_contract_violation symbol alias libstdc++-v3/ChangeLog:     * src/experimental/contract.cc     [_GLIBCXX_INLINE_VERSION](handle_contract_violation): Provide

Re: [PATCH] check undefine_p for one more vr

> Am 21.09.2023 um 05:10 schrieb Jiufu Guo : > > Hi, > > The root cause of PR111355 and PR111482 is missing to check if vr0 > is undefined_p before call vr0.lower_bound. > > In the pattern "(X + C) / N", > >(if (INTEGRAL_TYPE_P (type) > && get_range_query (cfun)->range_of_expr

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