Re: [PATCH 0/7] ira/lra: Support subreg coalesce

On Wed, Nov 08, 2023 at 11:47:33AM +0800, Lehua Ding wrote: > Hi, > > These patchs try to support subreg coalesce feature in > register allocation passes (ira and lra). Hi Lehua, This patch set breaks the build for at least three embedded targets. See below. For avr the GCC build fails with:

Re: [PATCH 0/7] ira/lra: Support subreg coalesce

On 11/8/23 02:40, Richard Sandiford wrote: Lehua Ding writes: Hi, These patchs try to support subreg coalesce feature in register allocation passes (ira and lra). Thanks a lot for the series. This is definitely something we've needed for a while. I probably won't be able to look at it

[PATCH] c++: non-dependent .* folding [PR112427]

Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK for trunk? -- >8 -- Here when building up the non-dependent .* expression, we crash from fold_convert on 'b.a' due to this (templated) COMPONENT_REF having an IDENTIFIER_NODE instead of FIELD_DECL operand that middle-end

[patch] OpenMP/Fortran: Implement omp allocators/allocate for ptr/allocatables

Hi all, Comment to reviewers: * Fortran: Except for ensuring that the version field in array descriptors is always set to the default (zero), the generated code should only be affected when -fopenmp-allocators is set, even though several files are touched. * Middle-end:

Re: [PATCH v2] c: Add -Wreturn-mismatch warning, split from -Wreturn-type

On Wed, 8 Nov 2023, Florian Weimer wrote: > > v2: Update comment in gcc.dg/noncompile/pr55976-2.c. Do not produce > > an error in C90 pedantic-error mode for return; in a function > > returning non-void. Add gcc.dg/Wreturn-mismatch-6.c to demonstrate > > this behavior. > > Ping?

[PATCH][_Hahstable] Use RAII to guard node pointer while constructing

Another proposal to use RAII rather than __try/__catch block. libstdc++: [_Hashtable] Use RAII type to guard node while constructing value libstdc++-v3/ChangeLog:     * include/bits/hashtable_policy.h     (struct _NodePtrGuard<_HashtableAlloc, _NodePtr>): New.    

[committed] i386: Apply LRA reload workaround to insns with high registers [PR82524]

LRA is not able to reload zero_extracted in-out operand with matched input operand in the same way as strict_low_part in-out operand. The patch applies the strict_low_part workaround, where we allow LRA to generate an instruction with non-matched input operand, which is split post reload to the

Re: [PATCH] skip debug stmts when assigning locus discriminators

On 11/8/23 08:51, Alexandre Oliva wrote: c-c++-common/goacc/kernels-loop-g.c has been failing (compare-debug) on i686-linux-gnu since r13-3172, because the implementation enabled debug stmts to cause discriminators to be assigned differently, and the discriminators are printed in the .gkd

Re: [PATCH] testsuite: force PIC/PIE off for pr58245-1.C

On 11/8/23 08:57, Alexandre Oliva wrote: This test expects a single mention of stack_chk_fail, as part of a call sequence, but when e.g. PIE is enabled by default, we output .hidden stack_chk_fail_local, which makes for a count mismatch. Disable PIC/PIE so as to not depend on the

Re: [PATCH] libgcc: Add {unsigned , }__int128 <-> _Decimal{32, 64, 128} conversion support [PR65833]

On Wed, 8 Nov 2023, Jakub Jelinek wrote: > Hi! > > The following patch adds the missing > {unsigned ,}__int128 <-> _Decimal{32,64,128} > conversion support into libgcc.a on top of the _BitInt support > (doing it without that would be larger amount of code and I hope all > the targets which

Re: [PATCH] libstdc++: optimize bit iterators assuming normalization [PR110807]

On 08/11/23 13:10 -0300, Alexandre Oliva wrote: The representation of bit iterators, using a pointer into an array of words, and an unsigned bit offset into that word, makes for some optimization challenges: because the compiler doesn't know that the offset is always in a certain narrow range,

[PATCH] testsuite: tsan: add fallback overload for pthread_cond_clockwait

LTS GNU/Linux distros from 2018, still in use, don't have pthread_cond_clockwait. There's no trivial way to detect it so as to make the test conditional, but there's an easy enough way to silence the fail due to lack of the function in libc, and that has nothing to do with the false positive

RE: [PATCH] RISC-V: Fix dynamic LMUL cost model ICE

Committed, thanks Kito. Pan -Original Message- From: Kito Cheng Sent: Thursday, November 9, 2023 10:43 AM To: Juzhe-Zhong Cc: gcc-patches@gcc.gnu.org; kito.ch...@gmail.com; jeffreya...@gmail.com; rdapp@gmail.com Subject: Re: [PATCH] RISC-V: Fix dynamic LMUL cost model ICE LGTM,

Re: [PATCH][_Hahstable] Use RAII to guard node pointer while constructing

On Wed, 8 Nov 2023 at 20:00, François Dumont wrote: > > Another proposal to use RAII rather than __try/__catch block. > > libstdc++: [_Hashtable] Use RAII type to guard node while constructing value > > libstdc++-v3/ChangeLog: > > * include/bits/hashtable_policy.h > (struct

[Committed] RISC-V: Fix dynamic tests [NFC]

This patch just adapt dynamic LMUL tests for following preparing patches. Committed. gcc/testsuite/ChangeLog: * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul-mixed-1.c: Adapt test. * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-1.c: Ditto. *

[PATCH] libsupc++: try cxa_thread_atexit_impl at runtime

g++.dg/tls/thread_local-order2.C fails when the toolchain is built for a platform that lacks __cxa_thread_atexit_impl, even if the program is built and run using that toolchain on a (later) platform that offers __cxa_thread_atexit_impl. This patch adds runtime testing for

[PATCH] RISC-V: Fix dynamic LMUL cost model ICE

When trying to use dynamic LMUL to compile benchmark. Notice there is a bunch ICEs. This patch fixes those ICEs and append tests. gcc/ChangeLog: * config/riscv/riscv-vector-costs.cc (costs::preferred_new_lmul_p): Fix ICE. gcc/testsuite/ChangeLog: *

RE: [EXTERNAL] [PATCH] skip debug stmts when assigning locus discriminators

The fix looks good to me. Will this also fix https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107169 ? It was also a bad interaction of -gstatement-frontiers and discriminators. Eugene -Original Message- From: Alexandre Oliva Sent: Wednesday, November 8, 2023 7:51 AM To:

Re: [PATCH v2] libstdc++: optimize bit iterators assuming normalization [PR110807]

On Thu, 9 Nov 2023, 01:17 Alexandre Oliva, wrote: > On Nov 8, 2023, Jonathan Wakely wrote: > > > A single underscore prefix on __GLIBCXX_BUILTIN_ASSUME and > > __GLIBCXX_DISABLE_ASSUMPTIONS please. > > That's entirely gone now. > > >> +do \ > >>

[PATCH-2v2, rs6000] Enable vector mode for by pieces equality compare [PR111449]

Hi, This patch enables vector mode for by pieces equality compare. It adds a new expand pattern - cbrnachv16qi4 and set MOVE_MAX_PIECES and COMPARE_MAX_PIECES to 16 bytes when P8 vector enabled. The compare relies both move and compare instructions, so both macro are changed. As the vector

[PATCH-3v3, rs6000] Fix regression cases caused 16-byte by pieces move [PR111449]

Hi, Originally 16-byte memory to memory is expanded via pattern. expand_block_move does an optimization on P8 LE to leverage V2DI reversed load/store for memory to memory move. Now it's done by 16-byte by pieces move and the optimization is lost. This patch adds an insn_and_split pattern to

[PATCH, expand] Call misaligned memory reference in expand_builtin_return [PR112417]

Hi, This patch modifies expand_builtin_return and make it call expand_misaligned_mem_ref to load unaligned memory. The memory reference pointed by void* pointer might be unaligned, so expanding it with unaligned move optabs is safe. The new test case illustrates the problem. rs6000 doesn't

[PATCH v2] libstdc++: optimize bit iterators assuming normalization [PR110807]

On Nov 8, 2023, Jonathan Wakely wrote: > A single underscore prefix on __GLIBCXX_BUILTIN_ASSUME and > __GLIBCXX_DISABLE_ASSUMPTIONS please. That's entirely gone now. >> +do \ >> + if (std::is_constant_evaluated ())\ >> +

Re: [PATCH] RISC-V: Fix dynamic LMUL cost model ICE

LGTM, thanks :) On Thu, Nov 9, 2023 at 10:39 AM Juzhe-Zhong wrote: > > When trying to use dynamic LMUL to compile benchmark. > Notice there is a bunch ICEs. > > This patch fixes those ICEs and append tests. > > gcc/ChangeLog: > > * config/riscv/riscv-vector-costs.cc

[PATCH v3] libstdc++: optimize bit iterators assuming normalization [PR110807]

On Nov 8, 2023, Jonathan Wakely wrote: > ofst needs to be __ofst but OK for trunk with that change. Oh, doh, thanks for catching that last-minute tweak. Retesting with that change completed successfully, so I've just pushed the following: libstdc++: optimize bit iterators assuming

[PATCH] Avoid generate vblendps with ymm16+

This patch aims to avoid generate vblendps with ymm16+, And have bootstrapped and tested on x86_64-pc-linux-gnu{-m32,-m64}. Ok for trunk? gcc/ChangeLog: PR target/112435 * config/i386/sse.md: Adding constraints to restrict the generation of vblendps.

[PATCH v1] RISC-V: Refine frm emit after bb end in succ edges

From: Pan Li This patch would like to fine the frm insn emit when we meet abnormal edge in the loop. Conceptually, we only need to emit once when abnormal instead of every iteration in the loop. This patch would like to fix this defect and only perform insert_insn_end_basic_block when at least

Re: [PATCH] Avoid generate vblendps with ymm16+

On Thu, Nov 9, 2023 at 3:15 PM Hu, Lin1 wrote: > > This patch aims to avoid generate vblendps with ymm16+, And have > bootstrapped and tested on x86_64-pc-linux-gnu{-m32,-m64}. Ok for trunk? > > gcc/ChangeLog: > > PR target/112435 > * config/i386/sse.md: Adding constraints to

Re: [PATCH] testsuite: xfail scev-[35].c on ia32

On Wed, 8 Nov 2023, Alexandre Oliva wrote: > > These gimplefe tests never got the desired optimization on ia32, but > they only started visibly failing when the representation of MEMs in > dumps changed from printing 'symbol: a' to ''. > > The transformation is not considered profitable on

Re: [PATCH] minimal support for xtheadv

Hi Yi Xuan: This patch is trivial, and generally LGTM, but I would require putting the spec into https://github.com/riscv-non-isa/riscv-toolchain-conventions before merging this, also don't forget include "RISC-V:" in the title, it would be easier to track during the RISC-V GCC sync meeting :)

[PATCH v2] DSE: Allow vector type for get_stored_val when read < store

From: Pan Li Update in v2: * Move vector type support to get_stored_val. Original log: This patch would like to allow the vector mode in the get_stored_val in the DSE. It is valid for the read rtx if and only if the read bitsize is less than the stored bitsize. Given below example code with

Re: [PATCH v1] RISC-V: Refine frm emit after bb end in succ edges

OK。 juzhe.zh...@rivai.ai From: pan2.li Date: 2023-11-09 14:50 To: gcc-patches CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng Subject: [PATCH v1] RISC-V: Refine frm emit after bb end in succ edges From: Pan Li This patch would like to fine the frm insn emit when we meet abnormal edge

[PATCH] RISC-V: Fix the illegal operands for the XTheadMemidx extension.

The pattern "*extend2_bitmanip" and "*zero_extendhi2_bitmanip" in bitmanip.md are similar to the pattern "*th_memidx_bb_extendqi2" and "*th_memidx_bb_zero_extendhi2" in thead.md, which will cause the wrong instruction to be generated and report the following error in binutils: Assembler messages:

Re: [PATCH 1/3] tree-ssa-sink: do not sink to in front of setjmp

* Alexander Monakov via Gcc-patches: > diff --git a/gcc/testsuite/gcc.dg/setjmp-7.c b/gcc/testsuite/gcc.dg/setjmp-7.c > new file mode 100644 > index 0..44b5bcbfa > --- /dev/null > +++ b/gcc/testsuite/gcc.dg/setjmp-7.c > @@ -0,0 +1,13 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O2

[PATCH] Improve C99 compatibility of gcc.dg/setjmp-7.c test

gcc/testsuite/ChangeLog: * gcc.dg/setjmp-7.c (_setjmp): Declare. --- gcc/testsuite/gcc.dg/setjmp-7.c | 1 + 1 file changed, 1 insertion(+) diff --git a/gcc/testsuite/gcc.dg/setjmp-7.c b/gcc/testsuite/gcc.dg/setjmp-7.c index 44b5bcbfa9d..579542380ba 100644 ---

Re: [PATCH] RISC-V: Removed unnecessary sign-extend for vsetvl

Committed, thanks Juzhe. On 2023/11/8 21:29, juzhe.zhong wrote: lgtm Replied Message FromLehua Ding Date11/08/2023 21:27 To gcc-patches@gcc.gnu.org Cc juzhe.zh...@rivai.ai ,

Re: testsuite: introduce hostedlib effective target

On Wed, 8 Nov 2023 at 15:30, Alexandre Oliva wrote: > > On Nov 7, 2023, Jonathan Wakely wrote: > > > An alternative approach for the g++ testsuite would be to provide a > > set of dummy headers for the non-freestanding ones, so that all the > > hosted-only headers are provided by the testsuite

[PATCH v2] [PR83782] ifunc: back-propagate ifunc_resolver to aliases

Ping? https://gcc.gnu.org/pipermail/gcc-patches/2022-August/599453.html gcc.target/i386/mvc10.c fails with -fPIE on ia32 because we omit the @PLT mark when calling an alias to an indirect function. Such aliases aren't marked as ifunc_resolvers in the cgraph, so the test that would have forced

Re: [PATCH 1/3] tree-ssa-sink: do not sink to in front of setjmp

On Wed, 8 Nov 2023, Richard Biener wrote: > >> --- /dev/null > >> +++ b/gcc/testsuite/gcc.dg/setjmp-7.c > >> @@ -0,0 +1,13 @@ > >> +/* { dg-do compile } */ > >> +/* { dg-options "-O2 -fno-guess-branch-probability -w" } */ > >> +/* { dg-require-effective-target indirect_jumps } */ > >> + > >>

[PATCH] testsuite: force PIC/PIE off for pr58245-1.C

This test expects a single mention of stack_chk_fail, as part of a call sequence, but when e.g. PIE is enabled by default, we output .hidden stack_chk_fail_local, which makes for a count mismatch. Disable PIC/PIE so as to not depend on the configurable default. Regstrapped on x86_64-linux-gnu,

[PATCH] vect: Use statement vectype for conditional mask.

Hi, as Tamar reported in PR112406 we still ICE on aarch64 in SPEC2017 when creating COND_OPs in ifcvt. The problem is that we fail to deduce the mask's type from the statement vectype and then end up with a non-matching mask in expand. This patch checks if the current op is equal to the mask

[PATCH v2] i386 PIE: accept @GOTOFF in load/store multi base address

Ping? https://gcc.gnu.org/pipermail/gcc-patches/2022-July/598872.html Looking at the code generated for sse2-{load,store}-multi.c with PIE, I realized we could use UNSPEC_GOTOFF as a base address, and that this would enable the test to use the vector insns expected by the tests even with PIC, so

Re: [PATCH] RISC-V: Removed unnecessary sign-extend for vsetvl

lgtm Replied Message FromLehua DingDate11/08/2023 21:27 Togcc-patches@gcc.gnu.org Ccjuzhe.zh...@rivai.ai,kito.ch...@gmail.com,rdapp@gmail.com,pal...@rivosinc.com,jeffreya...@gmail.com,lehua.d...@rivai.aiSubject[PATCH] RISC-V: Removed unnecessary sign-extend for vsetvl

[PATCH 4/4] Refactor x86 decl based scatter vectorization, prepare SLP

The following refactors the x86 decl based scatter vectorization similar to what I did to the gather path. This prepares scatters for SLP as well, mainly single-lane since there are multiple missing bits to support multi-lane scatters. Tested extensively on the SLP-only branch which has the

[PATCH 3/4] Fix SLP of emulated gathers

The following fixes an error in the SLP of emulated gathers, discovered by x86 specific tests when enabling single-lane SLP. Bootstrap and regtest running on x86_64-unknown-linux-gnu. * tree-vect-stmts.cc (vectorizable_load): Adjust offset vector gathering for SLP of emulated

[PATCH 2/4] TLC to vect_check_store_rhs and vect_slp_child_index_for_operand

This prepares us for the SLP of scatters. We have to tell vect_slp_child_index_for_operand whether we are dealing with a scatter/gather stmt so this adds an argument similar to the one we have for vect_get_operand_map. This also refactors vect_check_store_rhs to get the actual rhs and the

[PATCH 1/4] Fix SLP of masked loads

The following adjusts things to use the correct mask operand for the SLP of masked loads and gathers. Test coverage is from runtime fails of i386 specific AVX512 tests when enabling single-lane SLP. Bootstrap and regtest running on x86_64-unknown-linux-gnu. * tree-vect-stmts.cc

[PATCH] skip debug stmts when assigning locus discriminators

c-c++-common/goacc/kernels-loop-g.c has been failing (compare-debug) on i686-linux-gnu since r13-3172, because the implementation enabled debug stmts to cause discriminators to be assigned differently, and the discriminators are printed in the .gkd dumps that -fcompare-debug compares. This

[PATCH] libstdc++: optimize bit iterators assuming normalization [PR110807]

The representation of bit iterators, using a pointer into an array of words, and an unsigned bit offset into that word, makes for some optimization challenges: because the compiler doesn't know that the offset is always in a certain narrow range, beginning at zero and ending before the word

Revert: [PATCH] Power10: Add options to disable load and store vector pair.

I discovered a short coming in the patch I proposed to add -mno-load-vector-pair and -mno-store-vector-pair tuning options. I will submit a new patch shortly. | Date: Fri, 13 Oct 2023 19:41:13 -0400 | From: Michael Meissner | Subject: [PATCH] Power10: Add options to disable load and store

Re: PR111754

On Thu, 26 Oct 2023 at 09:43, Prathamesh Kulkarni wrote: > > On Thu, 26 Oct 2023 at 04:09, Richard Sandiford > wrote: > > > > Prathamesh Kulkarni writes: > > > On Wed, 25 Oct 2023 at 02:58, Richard Sandiford > > > wrote: > > >> > > >> Hi, > > >> > > >> Sorry the slow review. I clearly didn't

Re: [PATCH v2 0/3] libgfortran: empty array fixes

Le 07/11/2023 à 19:16, Harald Anlauf a écrit : Hi Mikael, this is OK. Thanks for the patches! Harald Patches pushed. Thanks for the (fruitful) review.

[PATCH] minimal support for xtheadv

From: XYenChi This patch is for support xtheadv. gcc/ChangeLog: 2023-11-08 Chen Yixuan * common/config/riscv/riscv-common.cc: Add xthead minimal support. gcc/config/ChangeLog: 2023-11-08 Chen Yixuan * riscv/riscv.opt: Add xthead minimal support. ---

Re: [PATCH] i386: Fix C99 compatibility issues in the x86-64 AVX ABI test suite

On Wed, Nov 08, 2023 at 03:55:17PM +0100, Florian Weimer wrote: > * gcc.target/x86_64/abi/avx/avx-check.h (main): Call > __builtin_printf instead of printf. > * gcc.target/x86_64/abi/avx/test_passing_m256.c > (fun_check_passing_m256_8_values): Add missing void return >

[PATCH] Fix SIMD clone SLP a bit more

The following fixes an omission, mangling the non-SLP and SLP simd-clone info. Bootstrap and regtest running on x86_64-unknown-linux-gnu. * tree-vect-stmts.cc (vectorizable_simd_clone_call): Record to the correct simd_clone_info. --- gcc/tree-vect-stmts.cc | 9 - 1 file

Re: testsuite: introduce hostedlib effective target

On Nov 5, 2023, Mike Stump wrote: > that, otherwise, I'll approve this version. FWIW, this version is not usable as is. Something went wrong in my testing, and several regressions only visible in hosted mode made to the version I posted, that adds some missing end-of-comment markers for the

[PATCH] RISC-V: Removed unnecessary sign-extend for vsetvl

Hi, This patch try to combine bellow two insns and then further remove unnecessary sign_extend operations. This optimization is borrowed from LLVM (https://godbolt.org/z/4f6v56xej): (set (reg:DI 134 [ _1 ]) (unspec:DI [ (const_int 19 [0x13]) (const_int 8

[PATCH] i386: Fix C99 compatibility issues in the x86-64 AVX ABI test suite

* gcc.target/x86_64/abi/avx/avx-check.h (main): Call __builtin_printf instead of printf. * gcc.target/x86_64/abi/avx/test_passing_m256.c (fun_check_passing_m256_8_values): Add missing void return type. * gcc.target/x86_64/abi/avx512f/avx512f-check.h

Re: [PATCH] Do not prepend target triple to -fuse-ld=lld,mold.

> On Nov 7, 2023, at 23:37, Richard Biener wrote: > > On Tue, 7 Nov 2023, Tatsuyuki Ishi wrote: > >>> On Oct 16, 2023, at 18:16, Richard Biener wrote: >>> >>> On Mon, 16 Oct 2023, Tatsuyuki Ishi wrote: >>> > On Oct 16, 2023, at 17:55, Richard Biener wrote: > > On

Re: testsuite: introduce hostedlib effective target

On Wed, 8 Nov 2023 at 15:48, Jonathan Wakely wrote: > > On Wed, 8 Nov 2023 at 15:30, Alexandre Oliva wrote: > > > > On Nov 7, 2023, Jonathan Wakely wrote: > > > > > An alternative approach for the g++ testsuite would be to provide a > > > set of dummy headers for the non-freestanding ones, so

[PATCH] testsuite: arg-pushing reqs -mno-accumulate-outgoing-args

gcc.target/i386/pr95126-m32-[34].c expect push instructions that are only present with -mno-accumulate-outgoing-args, so make that option explicit rather than dependent on tuning. Regstrapped on x86_64-linux-gnu, also tested with gcc-13 on i686- and x86_64-. Ok to install? for

[PATCH] testsuite: xfail scev-[35].c on ia32

These gimplefe tests never got the desired optimization on ia32, but they only started visibly failing when the representation of MEMs in dumps changed from printing 'symbol: a' to ''. The transformation is not considered profitable on ia32, that's why it doesn't take place. Maybe that's a bug

RE: [PATCH]AArch64: Use SVE unpredicated LOGICAL expressions when Advanced SIMD inefficient [PR109154]

> >> > + "&& TARGET_SVE && rtx_equal_p (operands[0], operands[1]) > >> > + && satisfies_constraint_ (operands[2]) > >> > + && FP_REGNUM_P (REGNO (operands[0]))" > >> > + [(const_int 0)] > >> > + { > >> > +rtx op1 = lowpart_subreg (mode, operands[1], > mode); > >> > +rtx op2 =

[PATCH] testsuite: adjust gomp test for x86 -m32

declare-target-3.C expects .quad for entries in offload_var_table, but the entries are pointer-wide, so 32-bit targets use .long instead. Accept both. Regstrapped on x86_64-linux-gnu, also tested with gcc-13 on i686- and x86_64-. Ok to install? for gcc/testsuite/ChangeLog *

RFA: make scan-assembler* ignore LTO sections (Was: Re: committed [RISC-V]: Harden test scan patterns)

On Fri, 29 Sept 2023 at 14:54, Jeff Law wrote: > ... Joern can you post a follow-up manual twiddle so > that other ports can follow your example and avoid this problem? > > THanks, > > jeff The attached patch makes the scan-assembler* directives ignore the LTO sections. Regression tested

Re: [PATCH][_Hashtable] Add missing destructor call

On Wed, 8 Nov 2023 at 05:39, François Dumont wrote: > > > On 07/11/2023 00:28, Jonathan Wakely wrote: > > On Mon, 6 Nov 2023 at 21:39, François Dumont wrote: > >> Noticed looking for other occasion to replace __try/__catch with RAII > >> helper. > >> > >> libstdc++: [_Hashtable] Add

Re: [PATCH] gcc.dg/Wmissing-parameter-type*: Test the intended warning

On 11/8/23 01:53, Florian Weimer wrote: gcc/testsuite/ChangeLog: * gcc.dg/Wmissing-parameter-type.c: Build with -std=gnu89 to trigger the -Wmissing-parameter-type warning and not the default -Wimplicit warning. Also match against -Wmissing-parameter-type.

[PATCH] tree-ssa-loop-ivopts : Add live analysis in regs used in decision making

tree-ssa-loop-ivopts : Add live analysis in regs used in decision making. Add live anaysis in regs used calculation in decision making of selecting ivopts candidates. 2023-11-08 Ajit Kumar Agarwal gcc/ChangeLog: * tree-ssa-loop-ivopts.cc (get_regs_used): New function.

Re: testsuite: introduce hostedlib effective target

On Nov 7, 2023, Jonathan Wakely wrote: > An alternative approach for the g++ testsuite would be to provide a > set of dummy headers for the non-freestanding ones, so that all the > hosted-only headers are provided by the testsuite itself, but consist > of a single line: > #error not available

Re: [PATCH] testsuite: adjust gomp test for x86 -m32

On Wed, Nov 08, 2023 at 12:56:44PM -0300, Alexandre Oliva wrote: > > declare-target-3.C expects .quad for entries in offload_var_table, but > the entries are pointer-wide, so 32-bit targets use .long instead. > Accept both. > > Regstrapped on x86_64-linux-gnu, also tested with gcc-13 on i686-

Re: [PATCH 1/7] ira: Refactor the handling of register conflicts to make it more general

Hi Richard, Thanks for taking the time to review the code. On 2023/11/8 15:57, Richard Biener wrote: On Wed, Nov 8, 2023 at 4:48 AM Lehua Ding wrote: This patch does not make any functional changes. It mainly refactor two parts: 1. The ira_allocno's objects field is expanded to an scalable

[PATCH] RISC-V: Eliminate unused parameter warning.

From: xuli The parameter orig_fndecl is not used, use anonymous parameters instead. ../.././gcc/gcc/config/riscv/riscv-c.cc: In function ‘bool riscv_check_builtin_call(location_t, vec, tree, tree, unsigned int, tree_node**)’: ../.././gcc/gcc/config/riscv/riscv-c.cc:207:11: warning: unused

Re: [PATCH] RISC-V: Eliminate unused parameter warning.

OK juzhe.zh...@rivai.ai From: Li Xu Date: 2023-11-08 17:09 To: gcc-patches CC: kito.cheng; palmer; juzhe.zhong; xuli Subject: [PATCH] RISC-V: Eliminate unused parameter warning. From: xuli The parameter orig_fndecl is not used, use anonymous parameters instead.

Re: [PATCH] Middle-end: Fix bug of induction variable vectorization for RVV

Sorry for wrong description on the log: After this patch, the IR is: _36 = .SELECT_VL (ivtmp_34, POLY_INT_CST [4, 4]); _22 = (int) _36; vect_cst__21 = [vec_duplicate_expr] _22; juzhe.zh...@rivai.ai From: Juzhe-Zhong Date: 2023-11-08 18:53 To: gcc-patches CC: richard.sandiford;

[PATCH 0/3] RISC-V: Support CORE-V XCVELW and XCVBI extensions

This patch series presents the comprehensive implementation of the ELW and BI extension for CORE-V. Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to ensure its correctness and compatibility with the existing codebase. However, your input, reviews, and suggestions are

[PATCH 1/3] RISC-V: Add support for XCVelw extension in CV32E40P

Spec: github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md Contributors: Mary Bennett Nandni Jamnadas Pietra Ferreira Charlie Keaney Jessica Mills Craig Blackmore Simon Cook Jeremy Bennett Helene Chelin gcc/ChangeLog: *

[PATCH 2/3] RISC-V: Update XCValu constraints to match other vendors

gcc/ChangeLog: * config/riscv/constraints.md: CVP2 -> CV_alu_pow2. * config/riscv/corev.md: Likewise. --- gcc/config/riscv/constraints.md | 15 --- gcc/config/riscv/corev.md | 4 ++-- 2 files changed, 10 insertions(+), 9 deletions(-) diff --git

[PATCH 3/3] RISC-V: Add support for XCVbi extension in CV32E40P

Spec: github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md Contributors: Mary Bennett Nandni Jamnadas Pietra Ferreira Charlie Keaney Jessica Mills Craig Blackmore Simon Cook Jeremy Bennett Helene Chelin gcc/ChangeLog: *

Re: [PATCH 5/5] aarch64: Add rsr128 and wsr128 ACLE tests

On 11/7/23 23:51, Richard Sandiford wrote: Victor Do Nascimento writes: Extend existing unit tests for the ACLE system register manipulation functions to include 128-bit tests. gcc/testsuite/ChangeLog: * gcc/testsuite/gcc.target/aarch64/acle/rwsr.c (get_rsr128): New.

Re: [V2 PATCH] Handle bitop with INTEGER_CST in analyze_and_compute_bitop_with_inv_effect.

On Wed, Nov 8, 2023 at 3:53 PM Richard Biener wrote: > > On Wed, Nov 8, 2023 at 2:18 AM Hongtao Liu wrote: > > > > On Tue, Nov 7, 2023 at 10:34 PM Richard Biener > > wrote: > > > > > > On Tue, Nov 7, 2023 at 2:03 PM Hongtao Liu wrote: > > > > > > > > On Tue, Nov 7, 2023 at 4:10 PM Richard

[Committed] RISC-V: Fix VSETVL VL check condition bug

When fixing the induction variable vectorization bug, notice there is a ICE bug in VSETVL PASS: 0x178015b rtl_check_failed_code1(rtx_def const*, rtx_code, char const*, int, char const*) ../../../../gcc/gcc/rtl.cc:770 0x1079cdd rhs_regno(rtx_def const*)

Re: PING^1 [PATCH v3] sched: Change no_real_insns_p to no_real_nondebug_insns_p [PR108273]

"Kewen.Lin" writes: > Hi, > > Gentle ping this: > > https://gcc.gnu.org/pipermail/gcc-patches/2023-October/634201.html Sorry for the lack of review on this. Personally, I've never looked at this part of code base in detail, so I don't think I can do a proper review. I'll try to have a look in

[avr,committed] Tweak IEEE double multiplication

Applied this patch that improves IEEE double multiplication. The old code consumed time for calling local helpers and to prepare arguments. Functions that use mul like expl or sinl are around 5%...9% faster now. The code size did not increase. Johann -- LibF7: Tweak IEEE double

Re: [PATCH] Improve C99 compatibility of gcc.dg/setjmp-7.c test

On Wed, Nov 08, 2023 at 11:19:10AM +0100, Florian Weimer wrote: > gcc/testsuite/ChangeLog: > > * gcc.dg/setjmp-7.c (_setjmp): Declare. Ok. Jakub

[PATCH] gcc.dg/Wmissing-parameter-type*: Test the intended warning

gcc/testsuite/ChangeLog: * gcc.dg/Wmissing-parameter-type.c: Build with -std=gnu89 to trigger the -Wmissing-parameter-type warning and not the default -Wimplicit warning. Also match against -Wmissing-parameter-type. * gcc.dg/Wmissing-parameter-type.c:

Re: [PATCH 0/7] ira/lra: Support subreg coalesce

Lehua Ding writes: > Hi, > > These patchs try to support subreg coalesce feature in > register allocation passes (ira and lra). Thanks a lot for the series. This is definitely something we've needed for a while. I probably won't be able to look at it in detail for a couple of weeks (and the

[PATCH] Middle-end: Fix bug of induction variable vectorization for RVV

PR: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112438 SELECT_VL result is not necessary always VF in non-final iteration. Current GIMPLE IR is wrong: # vect_vec_iv_.21_25 = PHI <_24(4), { 0, 1, 2, ... }(3)> ... _24 = vect_vec_iv_.21_25 + { POLY_INT_CST [4, 4], ... }; After this patch which

Re: [PATCH 5/5] aarch64: Add rsr128 and wsr128 ACLE tests

Christophe Lyon writes: > On 11/7/23 23:51, Richard Sandiford wrote: >> Victor Do Nascimento writes: >>> Extend existing unit tests for the ACLE system register manipulation >>> functions to include 128-bit tests. >>> >>> gcc/testsuite/ChangeLog: >>> >>> *

Re: [PATCH] LoongArch: Remove redundant barrier instructions before LL-SC loops

On Wed, 2023-11-08 at 09:49 +0800, chenglulu wrote: > > 在 2023/11/6 下午7:36, Xi Ruoyao 写道: > > This is isomorphic to the LLVM changes [1-2]. > > > > On LoongArch, the LL and SC instructions has memory barrier semantics: > > > > - LL: + > > - SC: + > > > > But the compare and swap operation

Re: [PATCH 1/3] tree-ssa-sink: do not sink to in front of setjmp

> Am 08.11.2023 um 10:04 schrieb Florian Weimer : > > * Alexander Monakov via Gcc-patches: > >> diff --git a/gcc/testsuite/gcc.dg/setjmp-7.c >> b/gcc/testsuite/gcc.dg/setjmp-7.c >> new file mode 100644 >> index 0..44b5bcbfa >> --- /dev/null >> +++ b/gcc/testsuite/gcc.dg/setjmp-7.c