On Thu, 1 Jun 2023, Patrick Palka wrote:
> During partial ordering, we want to look through dependent alias
> template specializations within template arguments and otherwise
> treat them as opaque in other contexts (see e.g. r7-7116-g0c942f3edab108
> and r11-7011-g6e0a231a4aa240). To that end
On Fri, Dec 15, 2023 at 4:43 AM Jonathan Wakely wrote:
> On Fri, 15 Dec 2023 at 01:17, Tim Song wrote:
> >
> > On Thu, Dec 14, 2023 at 6:05 PM Jonathan Wakely
> wrote:
> >> + inline void
> >> + vprint_unicode(ostream& __os, string_view __fmt, format_args __args)
> >> + {
> >> +
Alex Coplan writes:
> This is a v6 of the aarch64 load/store pair fusion pass, which
> addresses the feedback from Richard's last review here:
>
> https://gcc.gnu.org/pipermail/gcc-patches/2023-December/640539.html
>
> In particular this version implements the suggested changes which
> greatly
Enables assert that every typed instruction is associated with a
dfa reservation
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_sched_variable_issue): enable assert
Signed-off-by: Edwin Lu
---
gcc/config/riscv/riscv.cc | 2 --
1 file changed, 2 deletions(-)
diff --git
David Malcolm writes:
> Move a further 268 tests from gcc.dg/analyzer to c-c++-common/analyzer.
>
> Successfully bootstrapped & regrtested on x86_64-pc-linux-gnu.
> Pushed to trunk as r14-6564-gae034b9106fbdd.
This patch introduced 840 additional FAILs on i386-pc-solaris2.11, no
doubt more
Jakub Jelinek writes:
> Hi!
>
> While looking at a bitint ICE, I've noticed we don't optimize
> in f1 and f5 functions below the 2 casts into just one at GIMPLE,
> even when optimize it in convert_to_integer if it appears in the same
> stmt. The large match.pd simplification of two conversions
On Linux/x86_64,
8afdbcdd7abe1e3c7a81e07f34c256e7f2dbc652 is the first bad commit
commit 8afdbcdd7abe1e3c7a81e07f34c256e7f2dbc652
Author: Di Zhao
Date: Fri Dec 15 03:22:32 2023 +0800
Consider fully pipelined FMA in get_reassociation_width
caused
FAIL: gcc.dg/pr110279-2.c
On Mon, 11 Sep 2023, Patrick Palka wrote:
> On Thu, 1 Jun 2023, Patrick Palka wrote:
>
> > For a complex alias template-id, dependent_alias_template_spec_p returns
> > true if any template argument of the template-id is dependent. This
> > predicate indicates that substitution into the
On 15/12/2023 11:31, Lipeng Zhu wrote:
On 2023/12/14 23:50, Richard Earnshaw (lists) wrote:
On 09/12/2023 15:39, Lipeng Zhu wrote:
This patch try to introduce the rwlock and split the read/write to
unit_root tree and unit_cache with rwlock instead of the mutex to
increase CPU efficiency.
On 12/12/23 12:32, Mary Bennett wrote:
Spec:
github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md
Contributors:
Mary Bennett
Nandni Jamnadas
Pietra Ferreira
Charlie Keaney
Jessica Mills
Craig Blackmore
Simon Cook
Jeremy Bennett
This adds initial support for function multiversioning on aarch64 using
the target_version and target_clones attributes. This loosely follows
the Beta specification in the ACLE [1], although with some differences
that still need to be resolved (possibly as follow-up patches).
Existing function
On 12/14/23 17:14, Christoph Müllner wrote:
On Fri, Dec 15, 2023 at 12:36 AM Jeff Law wrote:
On 12/14/23 02:46, Christoph Müllner wrote:
On Tue, Jun 20, 2023 at 12:34 AM Jeff Law via Gcc-patches
wrote:
A handful of the scalar crypto instructions are supposed to take a
constant
On Fri, Dec 15, 2023 at 1:38 PM Jeff Law wrote:
>
>
>
> On 12/12/23 20:54, Palmer Dabbelt wrote:
> > I can't actually find anything in the ISA manual that makes Ztso imply
> > A. In theory the memory ordering is just a different thing that the set
> > of availiable instructions (ie, Ztso without
On Wed, 6 Dec 2023, Jonathan Wakely wrote:
> Any comments on this approach?
>
> -- >8 --
>
> This makes constexpr std::vector (mostly) work in Debug Mode. All safe
> iterator instrumentation and checking is disabled during constant
> evaluation, because it requires mutex locks and calls to
On 12/12/23 12:32, Mary Bennett wrote:
gcc/ChangeLog:
* config/riscv/constraints.md: CVP2 -> CV_alu_pow2.
* config/riscv/corev.md: Likewise.
---
Kito ack'd the V3 patch, so I went ahead and pushed this to the trunk.
jeff
On 12/12/23 20:24, Xiao Zeng wrote:
This patch would like to add new sub extension (aka Zvfbfmin) to the
-march= option. It introduces a new data type BF16.
Depending on different usage scenarios, the Zvfbfmin extension may
depend on 'V' or 'Zve32f'. This patch only implements dependencies
On 15/12/2023 15:34, Richard Sandiford wrote:
> Alex Coplan writes:
> > This is a v6 of the aarch64 load/store pair fusion pass, which
> > addresses the feedback from Richard's last review here:
> >
> > https://gcc.gnu.org/pipermail/gcc-patches/2023-December/640539.html
> >
> > In particular this
This patch adds support for the "target_version" attribute to the middle
end and the C++ frontend, which will be used to implement function
multiversioning in the aarch64 backend.
On targets that don't use the "target" attribute for multiversioning,
there is no conflict between the "target" and
On 12/12/23 20:54, Palmer Dabbelt wrote:
I can't actually find anything in the ISA manual that makes Ztso imply
A. In theory the memory ordering is just a different thing that the set
of availiable instructions (ie, Ztso without A would still imply TSO for
loads and stores). It also seems
On 12/14/23 14:32, Patrick O'Neill wrote:
The testcase for pr112773 started passing after r14-6472-g8501edba91e
which was before the actual fix. This patch adds -fno-vect-cost-model
which prevents the testcase from passing due to the vls change.
gcc/testsuite/ChangeLog:
*
Bootstrapped and regtested on x86_64-pc-linux-gnu with GLIBCXX_TESTSUITE_STDS=20
and RUNTESTFLAGS="--target_board=unix/-D_GLIBCXX_USE_CXX11_ABI=0".
-- >8 --
My previous patch (naively) assumed that a TREE_CODE of RECORD_TYPE or
UNION_TYPE was sufficient for optype to be considered a "class
On 12/12/23 12:32, Mary Bennett wrote:
Spec:
github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md
Contributors:
Mary Bennett
Nandni Jamnadas
Pietra Ferreira
Charlie Keaney
Jessica Mills
Craig Blackmore
Simon Cook
Jeremy Bennett
On 12/15/23 19:20, Nathaniel Shead wrote:
Bootstrapped and regtested on x86_64-pc-linux-gnu with GLIBCXX_TESTSUITE_STDS=20
and RUNTESTFLAGS="--target_board=unix/-D_GLIBCXX_USE_CXX11_ABI=0".
OK, thanks.
-- >8 --
My previous patch (naively) assumed that a TREE_CODE of RECORD_TYPE or
2023-12-16 03:27 Jeff Law wrote:
>
>
>
>On 12/12/23 20:24, Xiao Zeng wrote:
>> This patch would like to add new sub extension (aka Zvfbfmin) to the
>> -march= option. It introduces a new data type BF16.
>>
>> Depending on different usage scenarios, the Zvfbfmin extension may
>> depend on 'V'
On Sat, Dec 16, 2023 at 6:18 AM Andrew Carlotti wrote:
>
> This adds initial support for function multiversioning on aarch64 using
> the target_version and target_clones attributes. This loosely follows
> the Beta specification in the ACLE [1], although with some differences
> that still need to
This is a v6 of the aarch64 load/store pair fusion pass, which
addresses the feedback from Richard's last review here:
https://gcc.gnu.org/pipermail/gcc-patches/2023-December/640539.html
In particular this version implements the suggested changes which
greatly simplify the double list walk.
This patch does not create vector related insn reservations for
generic.md and sifive-7.md. It updates/creates insn reservations
for all non-vector typed insns
gcc/ChangeLog:
* config/riscv/generic-ooo.md (generic_ooo_sfb_alu): create/update
reservation
(generic_ooo_branch):
This patch copies the vector reservations from generic-ooo.md and
inserts them into generic.md and sifive.md. The vector pipelines are
necessary to avoid an ICE from the assert
gcc/ChangeLog:
* config/riscv/generic-ooo.md: syntax
* config/riscv/generic.md (pipe0): new reservation
This series is a prototype for adding all typed instructions to a dfa
scheduling pipeline.
I've been working on adding insn reservations for all typed instructions
to ensure all instructions are part of a dfa pipeline. I don't have a good
understanding of vector instruction latency, so I have
Due to recent middle-end cost model changes, now we can do more VLA SLP.
Fix these following regressions:
XPASS: gcc.target/riscv/rvv/autovec/partial/slp-1.c scan-assembler \\tvand
XPASS: gcc.target/riscv/rvv/autovec/partial/slp-1.c scan-assembler \\tvand
XPASS:
On Fri, Dec 15, 2023 at 2:25 AM haochen.jiang
wrote:
>
> On Linux/x86_64,
>
> 8afdbcdd7abe1e3c7a81e07f34c256e7f2dbc652 is the first bad commit
> commit 8afdbcdd7abe1e3c7a81e07f34c256e7f2dbc652
> Author: Di Zhao
> Date: Fri Dec 15 03:22:32 2023 +0800
>
> Consider fully pipelined FMA in
I pushed this obvious change.
Gerald
gcc:
* doc/install.texi (Specific) : Update nvptx-tools
Github link.
---
gcc/doc/install.texi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi
index c1128d9274c..fffad700af7
Gerald
---
htdocs/projects/cli.html | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/htdocs/projects/cli.html b/htdocs/projects/cli.html
index 394832b6..47ddb362 100644
--- a/htdocs/projects/cli.html
+++ b/htdocs/projects/cli.html
@@ -460,7 +460,7 @@ allowing the user to
We used a branch to load floating-point comparison results into GPR.
This is very slow when the branch is not predictable.
Implement movfcc so we can reload FCCmode into GPRs, FPRs, and MEM.
Then implement cstore4.
gcc/ChangeLog:
* config/loongarch/loongarch-tune.h
Hi!
On 2023-12-13T08:14:28+, Di Zhao OS wrote:
> --- /dev/null
> +++ b/gcc/testsuite/gcc.dg/pr110279-2.c
> @@ -0,0 +1,41 @@
> +/* PR tree-optimization/110279 */
> +/* { dg-do compile } */
> +/* { dg-options "-Ofast --param tree-reassoc-width=4 --param
> fully-pipelined-fma=1
Hi,
PR112995 exposed one issue in current try_replace_dest_reg
that the result rtx insn after replace_dest_with_reg_in_expr
is probably unable to match any constraints. Although there
are some checks on the changes onto dest or src of orig_insn,
none is performed on the EXPR_INSN_RTX.
This
>> bool indices_fit_selector = maybe_ge (vec_len, 2 << GET_MODE_BITSIZE
>> (GET_MODE_INNER (vmode)));
No, I think it will make us miss some optimization.
For example, for poly value [16,16] maybe_ge ([16,16], 65536) which makes us
missed merge optimization but
we definitely can do merge
On 12/15/23 13:16, juzhe.zh...@rivai.ai wrote:
>
>>> bool indices_fit_selector = maybe_ge (vec_len, 2 << GET_MODE_BITSIZE
>>> (GET_MODE_INNER (vmode)));
> No, I think it will make us miss some optimization.
>
> For example, for poly value [16,16] maybe_ge ([16,16], 65536) which makes us
>
Do you mean like this ?
/* We need to use precomputed mask for such situation and such mask
can only be computed in compile-time known size modes. */
bool indices_fit_selector_p
= maybe_ge (vec_len, 2 << GET_MODE_BITSIZE (GET_MODE_INNER (vmode)));
if (GET_MODE_BITSIZE
Oh. I think it should be renamed into not_fit.
Is this following make sense to you ?
/* We need to use precomputed mask for such situation and such mask
can only be computed in compile-time known size modes. */
bool indices_not_fit_selector_p
= maybe_ge (vec_len, 2 <<
Hi Jason!
I think you usually deal with these kind of GCC Git things? If not,
please let me know.
On 2023-10-26T10:21:18+0200, I wrote:
> First, I've pushed into GCC upstream Git branch devel/rust/libgrust-v2
> the "v2" libgrust changes as posted by Arthur, so that people can easily
> test this
On Fri, 15 Dec 2023 at 01:17, Tim Song wrote:
>
> On Thu, Dec 14, 2023 at 6:05 PM Jonathan Wakely wrote:
>> + inline void
>> + vprint_unicode(ostream& __os, string_view __fmt, format_args __args)
>> + {
>> +ostream::sentry __cerb(__os);
>> +if (__cerb)
>> + {
>> +
>> + const
Hi Juzhe,
in general looks OK.
> + /* We need to use precomputed mask for such situation and such mask
> + can only be computed in compile-time known size modes. */
> + if (GET_MODE_BITSIZE (GET_MODE_INNER (vmode)) == 8 && maybe_ge (vec_len,
> 256)
> + && !vec_len.is_constant ())
>
The following avoids creating a niter peeling epilog more consistently,
matching what peeling later uses for the skip_vector condition, in
particular when versioning is required which then also ensures the
vector loop is entered unless the epilog is vectorized. This should
ideally match
On 2023/12/14 23:50, Richard Earnshaw (lists) wrote:
On 09/12/2023 15:39, Lipeng Zhu wrote:
This patch try to introduce the rwlock and split the read/write to
unit_root tree and unit_cache with rwlock instead of the mutex to
increase CPU efficiency. In the get_gfc_unit function, the
On Thu, 14 Dec 2023, Jakub Jelinek wrote:
> Hi!
>
> Given what I saw in the aarch64/arm psABIs for BITINT_TYPE, as I said
> earlier I'm afraid we need to differentiate between the limb mode/precision
> specified in the psABIs (what is used to decide how it is actually passed,
> aligned or what
> Oh. I think it should be renamed into not_fit.
>
> Is this following make sense to you ?
>
> /* We need to use precomputed mask for such situation and such mask
> can only be computed in compile-time known size modes. */
> bool indices_not_fit_selector_p
> = maybe_ge (vec_len, 2
Do you mean :
/* We need to use precomputed mask for such situation and such mask
can only be computed in compile-time known size modes. */
bool indices_fit_selector_p
= GET_MODE_BITSIZE (GET_MODE_INNER (vmode)) > 8 || known_lt (vec_len, 256);
if (!indices_fit_selector_p &&
On 12/15/23 13:52, juzhe.zh...@rivai.ai wrote:
> Do you mean :
>
> /* We need to use precomputed mask for such situation and such mask
> can only be computed in compile-time known size modes. */
> bool indices_fit_selector_p
> = GET_MODE_BITSIZE (GET_MODE_INNER (vmode)) > 8 ||
This patch fixes the following FAILs in "full coverage" testing:
Running target
riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8/--param=riscv-autovec-preference=fixed-vlmax
FAIL: gcc.dg/vect/vect-strided-mult-char-ls.c -flto -ffat-lto-objects execution
LGTM.
Regards
Robin
Hi!
On 2023-12-14T15:26:38+0100, Tobias Burnus wrote:
> On 19.08.23 00:47, Julian Brown wrote:
>> This patch adds support for non-constant component offsets in "map"
>> clauses for OpenMP (and the equivalants for OpenACC) [...]
Should eventually also add some OpenACC test cases?
> LGTM with:
We don't allow SImode in FCC, so constraint z is never really used
here.
gcc/ChangeLog:
* config/loongarch/loongarch.md (movsi_internal): Remove
constraint z.
---
Bootstrapped and regtested on loongarch64-linux-gnu. Ok for trunk?
gcc/config/loongarch/loongarch.md | 6 +++---
Tested x86_64-linux and x86_64-w64-mingw. Pushed to trunk.
-- >8 --
Tim Song pointed out that although std::print behaves as a formatted
output function, it does "determine padding" using the stream's flags.
libstdc++-v3/ChangeLog:
* include/std/ostream (vprint_nonunicode,
Tested x86_64-linux and x86_64-w64-mingw. Pushed to trunk.
-- >8 --
Since we don't need to do anything special to print Unicode on
non-Windows targets, we might as well just use std::vprint_nonunicode to
implement std::vprint_unicode. Removing the duplicated code should
reduce code size in cases
Tested x86_64-linux and x86_64-w64-mingw. Pushed to trunk.
-- >8 --
libstdc++-v3/ChangeLog:
* src/c++23/print.cc (__write_to_terminal) [_WIN32]: If handle
does not refer to the console then just write to it using normal
file I/O.
* testsuite/27_io/print/2.cc
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