[RFC][PR70841] Reassoc fails to handle FP division

Hi, I tried to handle reassoc fails to handle FP division. I think the best way to do this is to do like what is done for MINUS_EXPR. I.e, convert the RDIV_EXPR to MULT_EXPR by (1/x) early and later in opt_rdiv_with_multiply, optimize it. Here is a patch that passes bootstrap and regression

Re: [RFC][PATCH][PR63586] Convert x+x+x+x into 4*x

Hi Richard, maybe instert_stmt_after will help here, I don't think you got the insertion logic correct, thus insert_stmt_after (mul_stmt, def_stmt) which I think misses GIMPLE_NOP handling. At least + if (SSA_NAME_VAR (op) != NULL huh? I suppose you could have tested

Re: [RFC][PATCH][PR40921] Convert x + (-y * z * z) into x - y * z * z

Hi Richard, + int last = ops.length () - 1; + bool negate_result = false; Do oe = ops.last (); Done. + if (rhs_code == MULT_EXPR + && ops.length () > 1 + && ((TREE_CODE (ops[last]->op) == INTEGER_CST and last.op

Re: [MIPS,committed] Update MIPS P5600 processor definition to avoid IMADD

On Wed, 4 May 2016, Matthew Fortune wrote: > diff --git a/gcc/config/mips/mips-cpus.def b/gcc/config/mips/mips-cpus.def > index 17034f2..5df9807 100644 > --- a/gcc/config/mips/mips-cpus.def > +++ b/gcc/config/mips/mips-cpus.def > @@ -44,10 +44,7 @@ MIPS_CPU ("mips4", PROCESSOR_R1, 4, 0) >

Re: [RS6000] Rewrite rs6000_frame_related to use simplify_replace_rtx

On Thu, May 05, 2016 at 06:49:04AM +0930, Alan Modra wrote: > > And it's a better name anyway? > > No, "real" seems silly to me. "patt" is a common idiom used in lots > of places for the pattern of an instruction. "patt" is used only once (in fwprop), everything else uses "pat". > What is

[C++ PATCH] PR c++/69855

Tested on Linux-PPC64. Comments very much welcomed on the change to g++.old-deja/g++.pt/crash3.C, I'm not at all sure what that test is trying to do; it looks like it may have never cared about the names of the local functions, but rather about the fact that the function bodies of the member

Re: [RS6000] TARGET_RELOCATABLE

On Wed, May 04, 2016 at 11:55:31AM -0500, Segher Boessenkool wrote: > On Wed, May 04, 2016 at 02:21:18PM +0930, Alan Modra wrote: > > Also, since flag_pic is set by -mrelocatable, a number of places that > > currently test TARGET_RELOCATABLE can be simplified. I also made > > -mrelocatable set

Re: Enabling -frename-registers?

On 05/04/2016 10:20 AM, Wilco Dijkstra wrote: > Also when people claim they can't see any benefit, did they check the > codesize difference on SPEC2006? > On AArch64 codesize reduced uniformly due to fewer moves (and in a few cases > significantly so). I expect > that to be true for other RISC

Re: Please include ada-hurd.diff upstream (try2)

Svante Signell, on Wed 04 May 2016 23:25:28 +0200, wrote: > On Wed, 2016-05-04 at 23:06 +0200, Samuel Thibault wrote: > > Svante Signell, on Wed 04 May 2016 19:43:27 +0200, wrote: > > > May I comment on Debian way of apt-get source gcc-*: Doing that > > > does > > > not unpack the sources, neither

Re: Please include ada-hurd.diff upstream (try2)

On Wed, 2016-05-04 at 23:06 +0200, Samuel Thibault wrote: > Svante Signell, on Wed 04 May 2016 19:43:27 +0200, wrote: > > May I comment on Debian way of apt-get source gcc-*: Doing that > > does > > not unpack the sources, neither does it apply the patches, you have > > to > > unpack and patch

Re: [RS6000] Rewrite rs6000_frame_related to use simplify_replace_rtx

On Wed, May 04, 2016 at 11:26:18AM -0500, Segher Boessenkool wrote: > On Wed, May 04, 2016 at 11:14:41AM +0930, Alan Modra wrote: > > * config/rs6000/rs6000.c (rs6000_frame_related): Rewrite. > > > - rtx real, temp; > > + rtx patt, repl; > > If you don't rename "real" here it is probably

Re: [C++ Patch] PR 68722

Agreed, I tend not to backport bugs on invalid code, definitely not if we already give a useful diagnostic. Jason On Wed, May 4, 2016 at 4:10 PM, Paolo Carlini wrote: > Hi again, > > On 12/04/2016 15:53, Jason Merrill wrote: >> >> Let's go with the first patch. > >

Re: Please include ada-hurd.diff upstream (try2)

Svante Signell, on Wed 04 May 2016 19:43:27 +0200, wrote: > May I comment on Debian way of apt-get source gcc-*: Doing that does > not unpack the sources, neither does it apply the patches, you have to > unpack and patch before you can change sources and update patches. Iv'e > patched the sources

[PATCH, i386]: Fix PR 70873 - 20% performance regression at 482.sphinx3 after r235442 with -O2 -m32 on Haswell.

Hello! This patch moves all TARGET_SSE_PARTIAL_REG_DEPENDENCY FP conversion splitters to a later split pass. Plus, the patch substantially cleans these and related patterns. The functionality of post-reload conversion splitters goes this way: - process FP conversions for

Fix dangling reference in comment

var_map_base_init is gone and all the machinery is now in tree-ssa-coalesce.c (and the 2 functions have explicit back references to gimple_can_coalesce_p). Tested on x86_64-suse-linux, applied on the mainline and 6 branch as obvious. 2016-05-04 Eric Botcazou

[PATCH 3/4] Extract deferred-location handling from jit

In order to faithfully load RTL dumps that contain references to source locations, the RTL frontend needs to be able to parse file and line information and turn then into location_t values. Unfortunately, the libcpp API makes it rather fiddly to create location_t values from a sequence of

[PATCH 0/4] RFC: RTL frontend

This patch kit introduces an RTL frontend, for the purpose of unit testing: primarly for unit testing of RTL passes, and possibly for unit testing of .md files. It's very much a work-in-progress; I'm posting it now to get feedback. I've successfully bootstrapped patches 1-3 of the kit on

[PATCH 2/4] Move name_to_pass_map into class pass_manager

The RTL frontend needs to be able to lookup passes by name. passes.c has global state name_to_pass_map (albeit static, scoped to passes.c), for use by enable_disable_pass. Move it to be a field of class pass_manager, and add a get_pass_by_name method. OK for trunk? gcc/ChangeLog: *

[PATCH 1/4] Make argv const char ** in read_md_files etc

This patch makes the argv param to read_md_files const, needed so that the RTL frontend can call it on a const char *. While we're at it, it similarly makes const the argv for all of the "main" functions of the various gen*. OK for trunk? gcc/ChangeLog: * genattr-common.c (main):

Re: [PATCH] Fix operand_equal_p hash checking (PR c++/70906, PR c++/70933)

On May 4, 2016 9:29:37 PM GMT+02:00, Jakub Jelinek wrote: >Hi! > >These 2 PRs were DUPed, yet they are actually different, but somewhat >related. >One of the ICEs is due to the OEP_ADDRESS_OF consistency checks that >both operand_equal_p and inchash::add_expr have (that want to

Re: [C++ Patch] PR 68722

Hi again, On 12/04/2016 15:53, Jason Merrill wrote: Let's go with the first patch. What about this one? Today I returned to it, and technically it still represents a regression in gcc-4_9-branch and gcc-5-branch, but personally I'd rather not backport the fix: in release-mode we just emit an

[PATCH] Handle also switch for -Wdangling-else

Hi! This patch let us warn about danling else even if there is a switch without {}s around the body. Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk? 2016-05-04 Jakub Jelinek * c-parser.c (c_parser_switch_statement): Add IF_P argument,

[PATCH] Improve min/max

Hi! AVX512BW has EVEX insns for these. Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk? 2016-05-04 Jakub Jelinek * config/i386/sse.md (*v8hi3, *v16qi3): Add avx512bw alternative. --- gcc/config/i386/sse.md.jj 2016-05-04

[PATCH] Improve whole vector right shift

Hi! In this case the situation is more complicated, because for V*HI we need avx512bw and avx512vl, while for V*SI only avx512vl is needed and both are in the same pattern. But we already have a pattern that does the right thing right after the "ashr3" - but as it is after it, the "ashr3" will

[PATCH] Improve *pmaddwd

Hi! As the testcase shows, we unnecessarily disallow xmm16+, even when we can use them for -mavx512bw. Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk? 2016-05-04 Jakub Jelinek * config/i386/sse.md (*avx2_pmaddwd, *sse2_pmaddwd): Use v

[PATCH] Improve vec extraction

Hi! While EVEX doesn't have vextracti128, we can use vextracti32x4; unfortunately without avx512dq we need to use full zmm input operand, but that shouldn't be a big deal when we hardcode 1 as immediate. Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk? 2016-05-04 Jakub

[PATCH] Improve vec_concatv?sf*

Hi! Another pair of define_insns. Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk? 2016-05-04 Jakub Jelinek * config/i386/sse.md (*vec_concatv2sf_sse4_1, *vec_concatv4sf): Use v instead of x in vex or maybe_vex alternatives, use

[PATCH] Improve other 13 define_insns

Hi! This patch tweaks more define_insns at once, again all the insns should be already in AVX512F or AVX512VL. Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk? 2016-05-04 Jakub Jelinek * config/i386/sse.md (sse_shufps_, sse_storehps,

[PATCH] Improve vec_interleave*

Hi! Another 3 define_insns that can handle xmm16+ operands. Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk? 2016-05-04 Jakub Jelinek * config/i386/sse.md (vec_interleave_lowv4sf, *vec_interleave_highv2df, *vec_interleave_lowv2df): Use

Re: [PATCH] Clean up vec_interleave* expanders

On Wed, May 4, 2016 at 9:40 PM, Jakub Jelinek wrote: > Hi! > > When looking for constraints that only have x's and not v's, these > useless constraints caught my search too. In define_expand, constraints > aren't really needed, they are needed only on define_insn* etc. > > So,

[PATCH] Clean up vec_interleave* expanders

Hi! When looking for constraints that only have x's and not v's, these useless constraints caught my search too. In define_expand, constraints aren't really needed, they are needed only on define_insn* etc. So, I'd like to kill these. Bootstrapped/regtested on x86_64-linux and i686-linux, ok

[PATCh] Improve sse_mov{hl,lh}ps

Hi! Another pair of define_insns where all the VEX insns have EVEX variant in AVX512VL. Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk? 2016-05-04 Jakub Jelinek * config/i386/sse.md (sse_movhlps, sse_movlhps): Use v instead of x in vex

[PATCH] Improve *avx_cvtp?2??256_2

Hi! Not sure how to easily construct a testcase for this (these insns are usually used for vectorization, and then it really depends on register pressure). But in any case, looking at documentation it seems all the used insns are available (generally even for further patches, what I'm looking for

[PATCH] Improve _fmadd__mask3

Hi! As the testcase can show, we should be using v constraint and generate better code that way. Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk? 2016-05-04 Jakub Jelinek * config/i386/sse.md (_fmadd__mask3): Use v constraint instead of

[PATCH] Fix operand_equal_p hash checking (PR c++/70906, PR c++/70933)

Hi! These 2 PRs were DUPed, yet they are actually different, but somewhat related. One of the ICEs is due to the OEP_ADDRESS_OF consistency checks that both operand_equal_p and inchash::add_expr have (that want to verify that we don't e.g. have ADDR_EXPR of ADDR_EXPR). operand_equal_p never

Re: Please include ada-hurd.diff upstream (try2)

> I.e. the proposed change below. Applied on mainline and 6 branch. Please post patches as attachments instead of plain text though, this avoids nasty surprises from mail readers. -- Eric Botcazou

Re: Enabling -frename-registers?

> I do not see that working unfortunately - Thumb-2 codesize increases by a > few percent even with -Os. This is primarily due to replacing a low > register with IP, which often changes a 16-bit instruction like: > > movsr2, #8 > > into a 32-bit one: > > mov ip, #8 > > This

Re: Please include ada-hurd.diff upstream (try2)

On Wed, 2016-05-04 at 18:43 +0200, Svante Signell wrote: > OnSamuel Thibault, on Wed 04 May 2016 17:29:48 +0200, wrote: > > > > > -   --  From: /usr/include/unistd.h __getpagesize or > > > getpagesize?? > > > -   function Get_Page_Size return int; > > > +   --  From:

Re: Enabling -frename-registers?

On Wed, May 04, 2016 at 12:11:04PM +0200, Bernd Schmidt wrote: > Given how many latent bugs it has shown up I think that alone would make > it valuable to have enabled at -O2. It is finding so many latent bugs simply because it is changing register allocation so much, and very aggressively.

[PATCH] tail merge ICE

This patch fixes an ICE Thomas observed in tree-ssa-tail-merge.c: On 05/03/16 06:34, Thomas Schwinge wrote: I'm also seeing the following regression for C and C++, libgomp.oacc-c-c++-common/loop-auto-1.c with -O2: source-gcc/libgomp/testsuite/libgomp.oacc-c-c++-common/loop-auto-1.c: In

Re: [RS6000] TARGET_RELOCATABLE

On Wed, May 04, 2016 at 02:21:18PM +0930, Alan Modra wrote: > For ABI_V4, -mrelocatable and -fPIC both generate position independent > code, with some extra "fixup" output for -mrelocatable. The > similarity of these two options has led to the situation where the > sysv4.h

Re: Please include ada-hurd.diff upstream (try2)

On Wed, 2016-05-04 at 17:34 +0200, Samuel Thibault wrote: > Samuel Thibault, on Wed 04 May 2016 17:29:48 +0200, wrote: > > The gcc-6 build failed. I see that one of the change is: > > > > -   --  From: /usr/include/unistd.h __getpagesize or getpagesize?? > > -   function Get_Page_Size return int;

[PATCH] add myself to MAINTAINERS

Hi, Having submitted my first patch, I need to add myself to MAINTAINERS. Index: MAINTAINERS === --- MAINTAINERS (revision 235841) +++ MAINTAINERS (working copy) @@ -560,6 +560,7 @@ Duncan Sands

Re: [RS6000] Rewrite rs6000_frame_related to use simplify_replace_rtx

On Wed, May 04, 2016 at 11:14:41AM +0930, Alan Modra wrote: > * config/rs6000/rs6000.c (rs6000_frame_related): Rewrite. > - rtx real, temp; > + rtx patt, repl; If you don't rename "real" here it is probably easier to read? And it's a better name anyway? > - if (REGNO (reg) ==

[PATCH] add reassociation width target function for power8

Hi, This patch enables TARGET_SCHED_REASSOCIATION_WIDTH for power8 and up. The widths returned are derived from testing with SPEC 2006 and some simple tests on power8. Bootstrapped and regtested on powerpc64le-unknown-linux-gnu, ok for trunk? 2016-05-04 Aaron Sawdey

Re: [patch] libstdc++/69703 ignore endianness in codecvt_utf8

On 20/04/16 18:40, Jonathan Wakely wrote: > On 19/04/16 19:07 +0100, Jonathan Wakely wrote: >> This was reported as a bug in the Filesystem library, but it's >> actually a problem in the codecvt_utf8 facet that it uses. > > The fix had a silly typo meaning it didn't work for big endian > targets,

Re: [PING][PATCH] New plugin event when evaluating a constexpr call

On 05/02/2016 03:28 PM, Andres Tiraboschi wrote: + constexpr_call_info call_info; + call_info.function = t; + call_info.call_stack = call_stack; + call_info.ctx = ctx; + call_info.lval_p = lval; + call_info.non_constant_p = non_constant_p; + call_info.overflow_p = overflow_p; +

Re: [PATCH], Add PowerPC ISA 3.0 vector d-form addressing

Hi Mike, On Tue, May 03, 2016 at 06:39:55PM -0400, Michael Meissner wrote: > With this patch, I enable -mlra if the user did not specify either -mlra or > -mno-lra on the command line, and -mcpu=power9 or -mpower9-dform-vector were > used. I also enabled -mvsx-timode if LRA was used, which also

Re: [PATCH] [FIX PR c/48116] -Wreturn-type does not work as advertised

On Mon, 11 Apr 2016, Prasad Ghangal wrote: > Hi! > > This is proposed patch for > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=48116 (-Wreturn-type does > not work as advertised) I think that this is actually a documentation bug and should be fixed by changing the documentation, not by

Re: Please include ada-hurd.diff upstream (try2)

> 2016-05-04 Samuel Thibault > > * s-osinte-gnu.ads: Make Get_Page_Size return int, and make it use > getpagesize instead of __getpagesize. > > --- a/src/gcc/ada/s-osinte-gnu.ads > +++ b/src/gcc/ada/s-osinte-gnu.ads > @@ -344,10 +344,9 @@ package

Re: [PATCH] Allow xmm16-xmm31 in sse2_movq128

On 03 May 13:28, Jakub Jelinek wrote: > Hi! > > Another insn where we can just unconditionally use v constraint instead of x > - for V2DImode HARD_REGNO_MODE_OK will only allow it for AVX512VL for the > ext regs, the insn is actually already available in AVX512F, but probably > not worth spending

Re: [PATCH] Better location info for "incomplete type" error msg (PR c/70756)

On Wed, May 4, 2016 at 9:00 AM, Marek Polacek wrote: > On Tue, May 03, 2016 at 08:05:47PM -0400, Jason Merrill wrote: >> Looks good. >> >> But I don't see a C++ testcase; can the test go into c-c++-common? > > Sadly, no. As of now, the patch doesn't improve things for C++

Re: C/C++ PATCH to add -Wdangling-else option

On Wed, May 04, 2016 at 03:39:19PM +, Joseph Myers wrote: > On Wed, 4 May 2016, Marek Polacek wrote: > > > On Tue, Apr 26, 2016 at 03:03:25PM +0200, Bernd Schmidt wrote: > > > On 04/26/2016 02:39 PM, Jakub Jelinek wrote: > > > > I support that change, and -Wparentheses will still enable this,

Re: C/C++ PATCH to add -Wdangling-else option

On Wed, 4 May 2016, Marek Polacek wrote: > On Tue, Apr 26, 2016 at 03:03:25PM +0200, Bernd Schmidt wrote: > > On 04/26/2016 02:39 PM, Jakub Jelinek wrote: > > > I support that change, and -Wparentheses will still enable this, it just > > > gives more fine-grained control and be in line with what

[PATCH] MIPS: Ensure that lo_sums do not contain an unaligned symbol

Hi, In MIPS (and similarly for other RISC architectures) to load an absolute address of an object requires a two instruction sequence: one instruction to load the high part of the object's address, and one instruction to load the low part of the object's address. Typically the result from

Re: Please include ada-hurd.diff upstream (try2)

Samuel Thibault, on Wed 04 May 2016 17:29:48 +0200, wrote: > The gcc-6 build failed. I see that one of the change is: > > - -- From: /usr/include/unistd.h __getpagesize or getpagesize?? > - function Get_Page_Size return int; > + -- From: /usr/include/i386-gnu/bits/shm.h __getpagesize or

Re: Please include ada-hurd.diff upstream (try2)

Hello Svante, The gcc-6 build failed. I see that one of the change is: - -- From: /usr/include/unistd.h __getpagesize or getpagesize?? - function Get_Page_Size return int; + -- From: /usr/include/i386-gnu/bits/shm.h __getpagesize or getpagesize?? + function Get_Page_Size return size_t;

Re: [RS6000] out-of-line exit register restore funcs

On Wed, May 04, 2016 at 01:45:28PM +0930, Alan Modra wrote: > This fixes the regression from gcc-4.5 for -m32 -Os shown by > gcc.target/powerpc/savres.c:s_r31. Bootstrap and regression tests > on powerpc64le-linux and powerpc64-linux in progress. OK assuming no > regressions? > > *

Re: [PATCH v2] gcov: Runtime configurable destination output

> On 04/29/16 11:08, Aaron Conole wrote: > > >Perhaps I've poorly explained what I want. I want to be able to pipe > >gcov error messages to a different file for post-processing / reporting > >elsewhere. I don't want them mixed with the application's messages. Do > >you think this kind of generic

Re: [PATCH v2] gcov: Runtime configurable destination output

On 04/29/16 11:08, Aaron Conole wrote: Perhaps I've poorly explained what I want. I want to be able to pipe gcov error messages to a different file for post-processing / reporting elsewhere. I don't want them mixed with the application's messages. Do you think this kind of generic flexibility

Fix regrename compare-debug issue

When scanning addresses inside a debug insn, we shouldn't use normal base/index classes. This shows as a compare-debug issue on Alpha, where INDEX_REG_CLASS is NO_REGS, and this prevented a chain from being renamed with debugging turned on. Uros has reported that this patch resolves the

Improve pure/const propagation across interposable function with non-interposable aliases

Hi, the API dealing with aliases is somewhow flawed by fact it makes difference between the main symbol (defining function) and its aliases. There is nothing special about the main symbol. This is fixed by this patch. Bootstrapped/regtested x86_64-linux, will commit it shortly. Honza

Re: [PATCH 12/18] haifa-sched.c: make insn_queue[] a vec

On 05/03/2016 02:41 PM, Trevor Saunders wrote: I guess the usual tool for that is contrib/compare-all-tests? is there a simpler one? Not sure. I have a collection of .i files (from building things like gcc and the kernel with -save-temps) and a script that compiles them all, then I just use

Re: Enabling -frename-registers?

Bernd Schmidt wrote: > On 05/04/2016 03:25 PM, Ramana Radhakrishnan wrote: >> On ARM / AArch32 I haven't seen any performance data yet - the one place we >> are concerned >> about the impact is on Thumb2 code size as regrename may end up >> inadvertently putting more >> things in high

Re: C, C++: Fix PR 69733 (bad location for ignored qualifiers warning)

On 04/25/2016 10:18 PM, Joseph Myers wrote: On Fri, 22 Apr 2016, Bernd Schmidt wrote: +/* Returns the smallest location != UNKNOWN_LOCATION in LOCATIONS, + considering only those c_declspec_words found in LIST, which + must be terminated by cdw_number_of_elements. */ + +static location_t

[MIPS, committed] microMIPS testsuite cleanup

2016-05-04 Kwok Cheung Yeung * gcc.target/mips/mips16-attributes.c: Skip if -mmicromips flag is present. Index: gcc.target/mips/mips16-attributes.c === ---

Re: [PATCH][genrecog] Fix warning about potentially uninitialised use of label

On 05/03/2016 10:28 AM, Kyrill Tkachov wrote: After experimenting a bit, I note that the warning goes away when I compile with -O2. In the cross compiler build I'm doing genrecog.c is compiler with -O1, which exhibits the warning. So I suppose DOM/VRP does catch, but only at the appropriate

[PING*2][PATCH] DWARF: add abstract origin links on lexical blocks DIEs

Ping for the patch submitted at . It applies just fine on the current trunk and still bootstrapps and regtests successfuly on x86_64-linux. Thank you in advance, -- Pierre-Marie de Rodat

Re: Enabling -frename-registers?

On Wed, May 4, 2016 at 2:37 PM, Bernd Schmidt wrote: > On 05/04/2016 03:25 PM, Ramana Radhakrishnan wrote: >> >> On ARM / AArch32 I haven't seen any performance data yet - the one >> place we are concerned about the impact is on Thumb2 code size as >> regrename may end up

Re: Enabling -frename-registers?

On 05/04/2016 03:25 PM, Ramana Radhakrishnan wrote: On ARM / AArch32 I haven't seen any performance data yet - the one place we are concerned about the impact is on Thumb2 code size as regrename may end up inadvertently putting more things in high registers. In theory at least

Re: [arm-embedded][PATCH, GCC/ARM, 2/3] Error out for incompatible ARM multilibs

On Friday 29 April 2016 16:07:23 Kyrill Tkachov wrote: > > Ok for trunk. > Thanks, > Kyrill Committed with the following obvious fix: > > >>> diff --git a/gcc/config.gcc b/gcc/config.gcc > >>> index 59aee2c..be3c720 100644 > >>> --- a/gcc/config.gcc > >>> +++ b/gcc/config.gcc > >>> @@

Re: Enabling -frename-registers?

On 04/05/16 11:26, Eric Botcazou wrote: >> Given how many latent bugs it has shown up I think that alone would make >> it valuable to have enabled at -O2. > > It might be worthwhile to test it on embedded architectures because modern > x86 > and PowerPC processors are probably not very

Re: C/C++ PATCH to add -Wdangling-else option

On Tue, Apr 26, 2016 at 03:03:25PM +0200, Bernd Schmidt wrote: > On 04/26/2016 02:39 PM, Jakub Jelinek wrote: > > I support that change, and -Wparentheses will still enable this, it just > > gives more fine-grained control and be in line with what clang does. > > > > Bernd, how much are you

[RS6000] Stop regrename twiddling with split-stack prologue

Bootstrap and regression tested powerpc64le-linux. Fixes 771 Go testsuite regressions. OK to apply everywhere? The alternative of adding all parameter regs used by cfun to the __morestack CALL_INSN_FUNCTION_USAGE and uses for cfun return value regs seems overkill when all we need to do is

[MIPS,committed] Update MIPS P5600 processor definition to avoid IMADD

The P5600 processor has a penalty for using integer multiply-add similar to the 74k so mark it to avoid the instruction by default. Committed as r235873. Matthew gcc/ * config/mips/mips-cpus.def (p5600): Avoid IMADD by default. Clean up p5600 comments. --- gcc/ChangeLog

Re: [RS6000] Align .toc section

On Wed, May 4, 2016 at 1:07 AM, Alan Modra wrote: > Lack of any .toc section alignment causes kexec and kdump failure > when linking without the usual linker script. This of course is > really a kexec-tools error, now fixed, but it is also true that .toc > ought to always be

Re: [PATCH] Better location info for "incomplete type" error msg (PR c/70756)

On Tue, May 03, 2016 at 08:05:47PM -0400, Jason Merrill wrote: > Looks good. > > But I don't see a C++ testcase; can the test go into c-c++-common? Sadly, no. As of now, the patch doesn't improve things for C++ (?). Seems we'd need to pass better locations down to pointer_int_sum /

Re: [RS6000] Simplify sysv4.h TARGET_TOC

On Wed, May 4, 2016 at 1:28 AM, Alan Modra wrote: > We can use the TARGET_* defines here. There isn't any reason to use > the underlying variable and masks. (The only reason I'm aware of to > use them is when a target config file redefines some TARGET_* macro, > say to 0 or 1,

Re: [RS6000] Correct PIC_OFFSET_TABLE_REGNUM

On Wed, May 4, 2016 at 1:30 AM, Alan Modra wrote: > Leaving this as r30 results in pic_offset_table_rtx of (reg 30) > for -m64, which is completely bogus. Various rtl analysis predicate > functions treat pic_offset_table_rtx specially.. > > Bootsrapped etc. OK to apply? > >

[PATCH] Move BIT_FIELD_REF folding to match.pd

Bootstrapped and tested on x86_64-unknown-linux-gnu, applied. Richard. 2016-05-04 Richard Biener * match.pd: Add BIT_FIELD_REF canonicalizations and vector constructor simplifications. * fold-const.c (fold_ternary_loc): Remove duplicate

Re: [PATCH 0/3] Simplify the simple_return handling

On 05/04/2016 02:10 AM, Segher Boessenkool wrote: Is this sufficient explanation, is it okay with the fprintf's fixed? Yeah, I suppose. From looking at some of the examples I have here I think there's still room for doubt whether all the alignment choices make perfect sense, but it's

[patch] libstdc++/70940 Start fixing polymorphic memory resources

This fixes the first errors noted in the PR, so that resource_adaptor doesn't rely on anything that isn't guaranteed by the Allocator requirements, and __null_memory_resource::do_is_equal doesn't have a missing return. More work is needed to solve the alignment bugs, which I'll work on soon.

RE: [PATCH : RL78] Disable interrupts during hardware multiplication routines

Hi Nick, I have modified and updated this patch as per your comments. Apologies, as it has taken me awhile for me to get back to this. https://gcc.gnu.org/ml/gcc-patches/2016-01/msg00702.html >> +/* Structure for G13 MDUC registers. */ struct mduc_reg_type { >> + unsigned int address; >> +

Re: Enabling -frename-registers?

> Given how many latent bugs it has shown up I think that alone would make > it valuable to have enabled at -O2. It might be worthwhile to test it on embedded architectures because modern x86 and PowerPC processors are probably not very sensitive to this kind of tweaks. -- Eric Botcazou

Re: Update GCC 6 release page

On Tue, 3 May 2016, Damian Rouson wrote: > The patch below expands the list of new Fortran support for the GCC 6 > Release Series Changes, New Features, Fixes page at > .https://gcc.gnu.org/gcc-6/changes.html. Please let me know > whether this is acceptable and will be applied. Based on FY's

Re: Enabling -frename-registers?

On 05/04/2016 12:03 PM, Eric Botcazou wrote: The IBM LTC team has tested the benefit of -frename-registers at -O2 and sees no net benefit for PowerPC -- some benchmarks improve slightly but others degrade slightly (a few percent). You mentioned no overall benefit for x86. Although you

Re: Enabling -frename-registers?

> The IBM LTC team has tested the benefit of -frename-registers at -O2 > and sees no net benefit for PowerPC -- some benchmarks improve > slightly but others degrade slightly (a few percent). You mentioned > no overall benefit for x86. Although you mentioned benefit for > Itanium, it is not a

Re: [testuite,AArch64] Make scan for 'br' more robust

On 4 May 2016 at 10:43, Kyrill Tkachov wrote: > > Hi Christophe, > > > On 02/05/16 12:50, Christophe Lyon wrote: >> >> Hi, >> >> I've noticed a "regression" of AArch64's noplt_3.c in the gcc-6-branch >> because my validation script adds the branch name to

Re: Enabling -frename-registers?

On Wed, May 04, 2016 at 11:08:47AM +0200, Bernd Schmidt wrote: > On 05/04/2016 11:05 AM, Alan Modra wrote: > >I agree it's good to find these things.. Another nasty bug to add to > >the list is complete breakage of gccgo on powerpc64le. I see register > >renaming around the prologue call to

Re: Enabling -frename-registers?

On 05/04/2016 11:05 AM, Alan Modra wrote: I agree it's good to find these things.. Another nasty bug to add to the list is complete breakage of gccgo on powerpc64le. I see register renaming around the prologue call to __morestack, which trashes function arguments. How does this come about,

Re: Enabling -frename-registers?

On Wed, May 04, 2016 at 12:52:47AM +0200, Bernd Schmidt wrote: > I must say I find the argumentation about the fallout not compelling. It's a > normal consequence of development work, and by enabling it at -O2, we have > found: > * a Linux kernel bug > * a rs6000 testsuite bug > * some i386.md

[Ping ^ 2] Re: [ARM] Add support for overflow add, sub, and neg operations

Ping. Previous Patch posted here: https://gcc.gnu.org/ml/gcc-patches/2016-03/msg01472.html

Re: [testuite,AArch64] Make scan for 'br' more robust

Hi Christophe, On 02/05/16 12:50, Christophe Lyon wrote: Hi, I've noticed a "regression" of AArch64's noplt_3.c in the gcc-6-branch because my validation script adds the branch name to gcc/REVISION. As a result scan-assembler-times "br" also matched "gcc-6-branch", hence the failure. The

Re: Enabling -frename-registers?

On Wed, May 4, 2016 at 12:52 AM, Bernd Schmidt wrote: > On 05/03/2016 11:26 PM, David Edelsohn wrote: >> >> Optimizations enabled by default at -O2 should show an overall net >> benefit -- that is the general justification that we have used in the >> past. I request that

Re: [RFC] Update gmp/mpfr/mpc minimum versions

On Tue, 3 May 2016, Bernd Edlinger wrote: > On 28.04.2016 09:09, Richard Biener wrote: > > > > As said elsewhere the main reason for all of this is to make the > > in-tree builds work better for newer archs that are not happy with > > the versions provided by download_prerequesites. This should

Re: Fix tree-inlinine ICE with uninitializer return value

On Tue, 3 May 2016, Jan Hubicka wrote: > Hi, > the code path handling the case where callee is missing return statement but > calle > statement has LHS is broken in tree-inline since anonymous SSA_NAMEs was > introduced. > This code is not not used because all those inlines are disabled by >

[SH][committed] Add support for additional SH2A post-inc/pre-dec addressing modes

Hi, The attached patch adds support for the following SH2A addressing modes: mov.b @-Rm,R0 mov.w @-Rm,R0 mov.l @-Rm,R0 mov.b R0,@Rn+ mov.w R0,@Rn+ mov.l R0,@Rn+ The patch also tweaks the post-inc/pre-dec addressing mode usage on non

Re: Update GCC 6 release page

> The patch below expands the list of new Fortran support for the GCC 6 Release > Series Changes, New Features, Fixes page at > .https://gcc.gnu.org/gcc-6/changes.html. Please let me know whether this is > acceptable and will be applied. Looks OK to me. I think you can apply, and if someone

Update GCC 6 release page

The patch below expands the list of new Fortran support for the GCC 6 Release Series Changes, New Features, Fixes page at .https://gcc.gnu.org/gcc-6/changes.html. Please let me know whether this is acceptable and will be applied. Damian --- original.html 2016-05-03 22:25:23.0