Re: [PATCH] rs6000: Make the ctr* patterns allow ints in vector regs (PR71763)

Whoops, left off a bit: > 2016-07-06 Segher Boessenkool > > PR target/70098 > PR target/71763 > * config/rs6000/rs6000.md (*ctr_internal1, *ctr_internal2, > *ctr_internal5, *ctr_internal6): * config/rs6000/rs6000.md

[PATCH] rs6000: Make the ctr* patterns allow ints in vector regs (PR71763)

Similar to PR70098, which is about integers in floating point registers, we can have the completely analogous problem with vector registers as well now that we allow integers in vector registers. So, this patch solves it in the same way. This only works for targets with direct move. To recap:

Re: [Driver] Add support for -fuse-ld=lld

On Mon, Jul 04, 2016 at 09:36:52PM +0200, Markus Trippelsdorf wrote: > On 2016.07.04 at 10:08 -0700, H.J. Lu wrote: > > On Sun, Jul 3, 2016 at 9:38 PM, Davide Italiano > > wrote: > > > On Thu, Jun 23, 2016 at 9:11 PM, Davide Italiano > > > wrote: >

Re: [PATCH 0/9] remove some manual memory management

On Thu, Jun 30, 2016 at 12:33:24PM +0200, Bernd Schmidt wrote: > On 06/29/2016 02:26 PM, tbsaunde+...@tbsaunde.org wrote: > > patches individually bootstrapped and regtested on x86_64-linux-gnu, ok? > > I think these all look sensible. ChangeLogs ought to have slightly more > information than

Re: [PATCH 0/6] remove some usage of rtx_{insn,expr}_list

On Fri, Jul 01, 2016 at 03:34:51PM +0200, Bernd Schmidt wrote: > On 06/21/2016 04:47 PM, Trevor Saunders wrote: > > On Mon, Jun 20, 2016 at 06:52:35PM +0200, Bernd Schmidt wrote: > > > > So that's a second more in real time - was the machine very busy at the > > > time > > > you ran these tests

Re: [PATCH, rs6000] Fix PR target/71733, ICE with -mcpu=power9 -mno-vsx

On Wed, Jul 06, 2016 at 05:01:38PM -0500, Peter Bergner wrote: > On 7/6/16 2:19 PM, Michael Meissner wrote: > >On Tue, Jul 05, 2016 at 09:26:50PM -0500, Peter Bergner wrote: > >>- rs6000_isa_flags &= ~OPTION_MASK_P9_VECTOR; > >>+ rs6000_isa_flags &= ~(OPTION_MASK_P9_VECTOR > >>+

Re: [v3 PATCH] Initial implementation of std::any.

On 07/07/16 00:57 +0300, Ville Voutilainen wrote: Tested on Linux-x64. 2016-07-07 Ville Voutilainen Implement std::any. This is not yet a C++17-conforming implementation, but just a copy of std::experimental::any with the proper namespace and C++17

Re: [PATCH] c/71552 - Confusing error for incorrect struct initialization

On 07/06/2016 03:55 PM, Jeff Law wrote: On 06/30/2016 04:38 PM, Martin Sebor wrote: On 06/20/2016 08:52 AM, Joseph Myers wrote: On Sat, 18 Jun 2016, Martin Sebor wrote: The attached patch slightly changes the order in which initializers are checked for type compatibility to issue the same

Re: [PATCH] c++/60760 - arithmetic on null pointers should not be allowed in constant expressions

On 06/23/2016 03:36 PM, Jason Merrill wrote: On 06/20/2016 10:17 PM, Martin Sebor wrote: + && tree_int_cst_equal (lhs, null_pointer_node) + && !tree_int_cst_equal (rhs, integer_zero_node)) Not integer_zerop? +"invalid conversion involving a null pointer"); ... +

Re: Improve insert/emplace robustness to self insertion

On 06/07/16 21:46 +0200, François Dumont wrote: On 05/07/2016 12:47, Jonathan Wakely wrote: On 04/07/16 15:55 +0100, Jonathan Wakely wrote: I'm getting nervous about the smart insertion trick to avoid making a copy, I have a devious testcase in mind which will break with that change. I'll

Re: [PATCH, rs6000] Fix PR target/71733, ICE with -mcpu=power9 -mno-vsx

On 7/6/16 2:19 PM, Michael Meissner wrote: On Tue, Jul 05, 2016 at 09:26:50PM -0500, Peter Bergner wrote: - rs6000_isa_flags &= ~OPTION_MASK_P9_VECTOR; + rs6000_isa_flags &= ~(OPTION_MASK_P9_VECTOR + | OPTION_MASK_P9_DFORM_VECTOR); } Note, this should

[v3 PATCH] Initial implementation of std::any.

Tested on Linux-x64. 2016-07-07 Ville Voutilainen Implement std::any. This is not yet a C++17-conforming implementation, but just a copy of std::experimental::any with the proper namespace and C++17 flagging. Proper conformance to C++17 will follow.

Re: [PATCH] c/71552 - Confusing error for incorrect struct initialization

On 06/30/2016 04:38 PM, Martin Sebor wrote: On 06/20/2016 08:52 AM, Joseph Myers wrote: On Sat, 18 Jun 2016, Martin Sebor wrote: The attached patch slightly changes the order in which initializers are checked for type compatibility to issue the same error for static initializers of

Re: [PATCH] Prevent LTO wrappers to process a recursive execution

On 06/23/2016 02:23 AM, Martin Liška wrote: On 06/23/2016 06:57 AM, Jeff Law wrote: Is this still something you want to pursue? It looks pretty reasonable and one could make an argument that it's a good idea in and of itself. jeff Yeah, I would like to install the patch :) Can I take your

Re: [PATCH] remove unused CTOR_LISTS_DEFINED_EXTERNALLY macro

On 06/27/2016 06:19 AM, tbsaunde+...@tbsaunde.org wrote: From: Trevor Saunders Hi, The last target to use this was i386-interix, so since that is gone we don't need this anymore. bootstrapped and regtested on x86-linux-gnu, ok? Trev libgcc/ChangeLog: 2016-06-27

Re: Improve insert/emplace robustness to self insertion

On 05/07/2016 12:47, Jonathan Wakely wrote: On 04/07/16 15:55 +0100, Jonathan Wakely wrote: I'm getting nervous about the smart insertion trick to avoid making a copy, I have a devious testcase in mind which will break with that change. I'll share the testcase later today. Here's a testcase

Re: [PATCH 2/2] gcc/genrecog: Don't warn for missing mode on special predicates

* Richard Sandiford [2016-07-04 09:47:20 +0100]: > Andrew Burgess writes: > > +/* Return true if OPERAND is a MATCH_OPERAND using a special predicate > > + function. */ > > + > > +static bool > > +special_predicate_operand_p (rtx

Re: [PATCH, rs6000] Fix PR target/71733, ICE with -mcpu=power9 -mno-vsx

On Tue, Jul 05, 2016 at 09:26:50PM -0500, Peter Bergner wrote: > The following patch fixes a bug where we do not disable POWER9 vector dform > addressing when we compile for POWER9 but without VSX support. This > manifested > itself with us trying to use dform addressing with altivec

[PATCH] simplify-rtx.c: start adding selftests (v2)

On Sun, 2016-07-03 at 18:12 +0100, Richard Sandiford wrote: > David Malcolm writes: > > This patch starts adding selftests to simplify-rtx.c, to ensure > > that > > RTL expressions are simplified as we expect. > > > > It adds a new ASSERT_RTX_EQ macro that checks for pointer

Re: [PATCH, rs6000] Fix PR target/71733, ICE with -mcpu=power9 -mno-vsx

On 7/6/16 12:53 PM, David Edelsohn wrote: On Tue, Jul 5, 2016 at 10:26 PM, Peter Bergner wrote: The following patch fixes a bug where we do not disable POWER9 vector dform addressing when we compile for POWER9 but without VSX support. This manifested itself with us

Re: [v3 PATCH] Add a new header for diagnosing the use of C++17 facilities in pre-C++17 modes.

On 06/07/16 20:11 +0300, Ville Voutilainen wrote: Add a new header for diagnosing the use of C++17 facilities in pre-C++17 modes. * include/bits/c++17_warning.h:New. Urgh, the test in the header is completely wrong. Fixed patch attached. OK for trunk.

Re: [PATCH, rs6000] Fix PR target/71733, ICE with -mcpu=power9 -mno-vsx

On Tue, Jul 5, 2016 at 10:26 PM, Peter Bergner wrote: > The following patch fixes a bug where we do not disable POWER9 vector dform > addressing when we compile for POWER9 but without VSX support. This > manifested > itself with us trying to use dform addressing with

Go patch committed: Implement escape analysis tag phase

This patch by Chris Manghane implements the tag phase in escape analysis. Escape analysis is still not enabled by default. Bootstrapped and ran Go testsuite on x86_64-pc-linux-gnu. Committed to mainline. Ian Index: gcc/go/gofrontend/MERGE

Re: [PATCH PR c/71699] Handle pointer arithmetic in nonzero tree checks

On 07/05/2016 12:41 PM, Richard Biener wrote: On Fri, Jul 1, 2016 at 3:10 PM, Manish Goregaokar wrote: Added a test: Ok if this passed bootstrap/regtest. + return flag_delete_null_pointer_checks +&& (tree_expr_nonzero_warnv_p (op0, strict_overflow_p) +

Re: [v3 PATCH] Add a new header for diagnosing the use of C++17 facilities in pre-C++17 modes.

On 6 July 2016 at 17:44, Ville Voutilainen wrote: > 2016-07-06 Ville Voutilainen > > Add a new header for diagnosing the use of C++17 facilities > in pre-C++17 modes. > * include/bits/c++17_warning.h:New. Urgh, the test

Re: [PATCH, ARM 6/7, ping1] Add support for CB(N)Z and (U|S)DIV to ARMv8-M Baseline

On Friday 20 May 2016 14:22:48 Kyrill Tkachov wrote: > Hi Thomas, > > > Hmm, I'm not a fan of this change. arm_print_operand_punct_valid_p is an > implementation of a target hook that is used to validate user-provided > inline asm as well and is therefore the right place to reject such invalid

Re: Determine more IVs to be non-overflowing

> > Yeah, I think the other comment should be adjusted accordingly. I > > didn't remember we have that one extra bit either ... ;) (given wide-ints > > have unsigned variants of ops I wonder if it is really necessary, but who > > knows - the wide-int rep w/o a sign is really sth odd and I blame

Re: [PATCH, libgcc/ARM 1a/6] Fix Thumb-1 only == ARMv6-M & Thumb-2 only == ARMv7-M assumptions

On Fri, Jun 17, 2016 at 6:21 PM, Thomas Preudhomme wrote: > On Wednesday 01 June 2016 10:00:52 Ramana Radhakrishnan wrote: >> Please fix up the macros, post back and redo the test. Otherwise this >> is ok from a quick read. > > What about the updated patch in

Re: [PATCH, libgcc/ARM 1/6] Fix Thumb-1 only == ARMv6-M & Thumb-2 only == ARMv7-M assumptions

On Mon, Jun 27, 2016 at 5:51 PM, Thomas Preudhomme wrote: > Hi Ramana, > > On Wednesday 01 June 2016 10:00:52 Ramana Radhakrishnan wrote: >> >> From here down to >> >> > -#if ((__ARM_ARCH__ > 5) && !defined(__ARM_ARCH_6M__)) \ >> > -||

Re: [PATCH][ARM] Add support for some ARMv8-A cores to driver-arm.c

On Wed, Jun 22, 2016 at 10:38 AM, Kyrill Tkachov wrote: > Hi all, > > This patch adds entries to the arm_cpu_table in driver-arm.c to enable it to > perform native CPU detection > on some aarch32 ARMv8-A systems. The cores added are Cortex-A32, Cortex-A35, >

Re: [AArch64] Fix simd intrinsics bug on float vminnm/vmaxnm

On 6 July 2016 at 17:44, Kyrill Tkachov wrote: > Hi all, > > > On 06/07/16 16:29, James Greenhalgh wrote: >> >> On Wed, Jul 06, 2016 at 02:11:51PM +0100, Jiong Wang wrote: >>> >>> The current vmaxnm/vminnm float intrinsics are implemented using >>>

Re: [AArch64] Fix simd intrinsics bug on float vminnm/vmaxnm

Hi all, On 06/07/16 16:29, James Greenhalgh wrote: On Wed, Jul 06, 2016 at 02:11:51PM +0100, Jiong Wang wrote: The current vmaxnm/vminnm float intrinsics are implemented using __builtin_aarch64_smax/min which are mapping to backend patterns using smin/smax rtl operators. However as

Re: [AArch64] Fix simd intrinsics bug on float vminnm/vmaxnm

On 6 July 2016 at 17:29, James Greenhalgh wrote: > On Wed, Jul 06, 2016 at 02:11:51PM +0100, Jiong Wang wrote: >> The current vmaxnm/vminnm float intrinsics are implemented using >> __builtin_aarch64_smax/min which are mapping to backend patterns >> using smin/smax rtl

Re: [AArch64] Fix simd intrinsics bug on float vminnm/vmaxnm

On Wed, Jul 06, 2016 at 02:11:51PM +0100, Jiong Wang wrote: > The current vmaxnm/vminnm float intrinsics are implemented using > __builtin_aarch64_smax/min which are mapping to backend patterns > using smin/smax rtl operators. However as documented in rtl.def > > "Further, if both operands

[v3 PATCH] Add a new header for diagnosing the use of C++17 facilities in pre-C++17 modes.

2016-07-06 Ville Voutilainen Add a new header for diagnosing the use of C++17 facilities in pre-C++17 modes. * include/bits/c++17_warning.h:New. diff --git a/libstdc++-v3/include/bits/c++17_warning.h b/libstdc++-v3/include/bits/c++17_warning.h new

[PATCH v2] x86: allow to suppress default clobbers added to asm()s

While it always seemed wrong to me that there's no way to avoid the default "flags" and "fpsr" clobbers, the regression the fix for PR/60663 introduced (see PR/63637) makes it even more desirable to have such a mechanism: This way, at least asm()s with a single output and no explicit clobbers

[PATCH] Fix assembler arguments for -m16

At the moment the -m16 option only passes the "--32" parameter to the assembler on glibc OSes, while on other OSes the assembler is called without any specific flag. This is wrong and causes the assembler to fail. Fix it by adding support for the -m16 option to x86-64.h. 2016-07-06 Roger Pau

Re: [patch] Fix type merging deficiency during WPA

On Wed, Jul 6, 2016 at 12:44 PM, Richard Biener wrote: > On Wed, Jul 6, 2016 at 12:21 PM, Richard Biener > wrote: >> On Wed, Jul 6, 2016 at 11:33 AM, Eric Botcazou wrote: I see. I think the solution is to

Re: [PATCH][ARM][Testsuite] Fix prototype in vst1Q_laneu64-1.c

On 6 July 2016 at 15:04, Wilco Dijkstra wrote: > Fix prototype in vst1Q_laneu64-1.c to unsigned char* so it passes. > > Committed as trivial fix. > > ChangeLog > 2016-07-06 Wilco Dijkstra > > gcc/testsuite/ > *

[Ada] Extra precision in the evaluation of non-static expressions

This patch prevents the use of arbitrary-precision computations when an expression consists of known numeric literals but one of them is not static by the rules of the language but happens to be known to the compiler through data-flow. The patch introduces a conversion to a machine number for the

[Ada] Spurious error on withed Ghost unit

This patch modifies the front end to prevent the generation of ALI and object files as well as bypass the back end and suppress any errors related to code generation when the compilation unit is ignored Ghost. -- Source -- -- ignore.adc pragma Assertion_Policy (Ghost

Re: [PATCH PR71518] Adjust misalign for outer loops also.

On Wed, Jul 6, 2016 at 2:58 PM, Yuri Rumyantsev wrote: > Hi All, > > Here is a simple patch which add missed misalign adjustment for outer loop. > > Bootstrapping and regression testing did not show any new failures. > > Is it OK for trunk? Ok. Richard. > ChangeLog: >

Re: -fopt-info handling

On Wed, Jul 6, 2016 at 2:25 PM, Ulrich Drepper wrote: > On Tue, Jul 5, 2016 at 6:06 AM, Richard Biener > wrote: >> I don't think all-all is a useful default. "optimized" may be though. > > I relied on old documentation installed on one of my

Re: [PATCH] Allow fwprop to undo vectorization harm (PR68961)

On Tue, 5 Jul 2016, Richard Sandiford wrote: > Richard Biener writes: > > On Sun, 3 Jul 2016, Richard Sandiford wrote: > > > >> Richard Biener writes: > >> > On Wed, 15 Jun 2016, Richard Sandiford wrote: > >> > > >> >> Richard Biener

[AArch64] Fix simd intrinsics bug on float vminnm/vmaxnm

The current vmaxnm/vminnm float intrinsics are implemented using __builtin_aarch64_smax/min which are mapping to backend patterns using smin/smax rtl operators. However as documented in rtl.def "Further, if both operands are zeros, or if either operand is NaN, then it is unspecified which

[PATCH][ARM][Testsuite] Fix prototype in vst1Q_laneu64-1.c

Fix prototype in vst1Q_laneu64-1.c to unsigned char* so it passes. Committed as trivial fix. ChangeLog 2016-07-06 Wilco Dijkstra gcc/testsuite/ * gcc.target/arm/vst1Q_laneu64-1.c (foo): Use unsigned char*. --- diff --git

[PATCH PR71518] Adjust misalign for outer loops also.

Hi All, Here is a simple patch which add missed misalign adjustment for outer loop. Bootstrapping and regression testing did not show any new failures. Is it OK for trunk? ChangeLog: 2016-07-06 Yuri Rumyantsev PR tree-optimization/71518 * tree-vect-data-refs.c

Re: [v3 PATCH] Implement LWG 2451

On 06/07/16 00:44 +0300, Ville Voutilainen wrote: Implement LWG 2451, optional should 'forward' T's implicit conversions. * include/experimental/optional (__is_optional_impl, __is_optional): New. (optional()): Make constexpr and default. (optional(_Up&&), optional(const

Re: [PATCH][vectorizer][2/2] Hook up mult synthesis logic into vectorisation of mult-by-constant

On 06/07/16 13:31, Rainer Orth wrote: Hi Kyrill, On 05/07/16 12:24, Rainer Orth wrote: Marc Glisse writes: On Tue, 5 Jul 2016, Kyrill Tkachov wrote: As for testing I've bootstrapped and tested the patch on aarch64 and x86_64 with synth_shift_p in

[Ada] Missing abort deferral on controlled aggregate component assignment

This patch adds an abort defer / undefer pair around the initialization statements of a controlled aggregate component as dictated by 9.8 11. -- Source -- -- aggregates.ads with Ada.Finalization; use Ada.Finalization; package Aggregates is type Ctrl is new

[Ada] Spurious error on container instantiation with predicated array type

This patch fixes a spurious type error in a predicate function created within an operation in an instantiation of a container package, when the element type is an unconstrained array with a predicate. The following must compile quietly gcc -c gpr2-project-registry-attribute.adb --- with

[Ada] Warning on fixed-point actual types with user-defined operators

This patch adds aa warning when a formal fixed point type is instantiated with a type that has a user-defined arithmetic operations, but the generic has no corresponding formal functions. This is worth a warning because of the special semantics of fixed-point operators, in particular multiplying

Re: [PATCH][vectorizer][2/2] Hook up mult synthesis logic into vectorisation of mult-by-constant

Hi Kyrill, > On 05/07/16 12:24, Rainer Orth wrote: >> Marc Glisse writes: >> >>> On Tue, 5 Jul 2016, Kyrill Tkachov wrote: >>> As for testing I've bootstrapped and tested the patch on aarch64 and x86_64 with synth_shift_p in vect_synth_mult_by_constant hacked to

Re: -fopt-info handling

On Tue, Jul 5, 2016 at 6:06 AM, Richard Biener wrote: > I don't think all-all is a useful default. "optimized" may be though. I relied on old documentation installed on one of my system. Apparently the default changed to optimized-optall. So, no change to the

Re: [PATCH v2] Allocate constant size dynamic stack space in the prologue

There's one thing I don't quite understand and which seems to have changed since v1: On 07/04/2016 02:19 PM, Dominik Vogt wrote: @@ -1099,8 +1101,10 @@ expand_stack_vars (bool (*pred) (size_t), struct stack_vars_data *data) /* If there were any, allocate space. */ if

Re: [PATCHv2, ARM, libgcc] New aeabi_idiv function for armv6-m

On 01/07/16 14:40, Ramana Radhakrishnan wrote: > > > On 13/10/15 18:01, Andre Vieira wrote: >> This patch ports the aeabi_idiv routine from Linaro Cortex-Strings >> (https://git.linaro.org/toolchain/cortex-strings.git), which was contributed >> by ARM under Free BSD license. >> >> The new

Re: [patch] Fix type merging deficiency during WPA

On Wed, Jul 6, 2016 at 12:21 PM, Richard Biener wrote: > On Wed, Jul 6, 2016 at 11:33 AM, Eric Botcazou wrote: >>> I see. I think the solution is to perform cgraph/varpool merging >>> before attempting to read in >>> the global decl stream.

Re: [PATCH PR71734] Add missed check that reference defined inside loop.

On Wed, Jul 6, 2016 at 11:50 AM, Yuri Rumyantsev wrote: > Richard, > > I pointed out in the commentary that REF is defined inside loop and > this check is related to this statement. Should I clarify it? > > + /* We consider REF defined in LOOP as independent if at least 2

Re: [patch] Fix type merging deficiency during WPA

On Wed, Jul 6, 2016 at 11:33 AM, Eric Botcazou wrote: >> I see. I think the solution is to perform cgraph/varpool merging >> before attempting to read in >> the global decl stream. IIRC Micha had (old) patches for this. > > How can you merge varpool nodes if you haven't

Re: Determine more IVs to be non-overflowing

> On Wed, 6 Jul 2016, Jan Hubicka wrote: > > > > Jan Hubicka writes: > > > > > > > Bootstrapped/regtested x86_64-linux, OK? > > > > > > > > * gcc.dg/tree-ssa/scev-14.c: new testcase. > > > > > > FAIL: gcc.dg/tree-ssa/scev-14.c scan-tree-dump-not ivopts "Overflowness >

Re: Determine more IVs to be non-overflowing

On Wed, 6 Jul 2016, Jan Hubicka wrote: > > Jan Hubicka writes: > > > > > Bootstrapped/regtested x86_64-linux, OK? > > > > > > * gcc.dg/tree-ssa/scev-14.c: new testcase. > > > > FAIL: gcc.dg/tree-ssa/scev-14.c scan-tree-dump-not ivopts "Overflowness > > wrto loop

Re: Determine more IVs to be non-overflowing

> Jan Hubicka writes: > > > Bootstrapped/regtested x86_64-linux, OK? > > > > * gcc.dg/tree-ssa/scev-14.c: new testcase. > > FAIL: gcc.dg/tree-ssa/scev-14.c scan-tree-dump-not ivopts "Overflowness wrto > loop niter:\tOverflow" Aha, this is wrong version of testcase. The

Re: [PATCH PR71734] Add missed check that reference defined inside loop.

Richard, I pointed out in the commentary that REF is defined inside loop and this check is related to this statement. Should I clarify it? + /* We consider REF defined in LOOP as independent if at least 2 loop + iterations are not dependent. */ 2016-07-06 12:38 GMT+03:00 Richard Biener

Re: [PATCH PR71734] Add missed check that reference defined inside loop.

On Tue, Jul 5, 2016 at 4:56 PM, Yuri Rumyantsev wrote: > Hi All, > > Here is a simple fix to cure regressions introduced by my fix for > 70729. Patch also contains minor changes in test found by Jakub. > > Bootstrapping and regression testing did not show any new failures. > >

Re: [patch] Fix type merging deficiency during WPA

> I see. I think the solution is to perform cgraph/varpool merging > before attempting to read in > the global decl stream. IIRC Micha had (old) patches for this. How can you merge varpool nodes if you haven't merged types? > But I wonder why we don't tree-merge 'n' here (from my C example)

Re: [patch] Fix type merging deficiency during WPA

On Wed, Jul 6, 2016 at 9:56 AM, Eric Botcazou wrote: >> So this is sth like (invalid C) >> >> t.h >> --- >> int n; >> struct X { int x[n]; }; >> >> t1.c >> -- >> #include "t.h" >> struct X x; >> t2.c >> -- >> #include "t.h" >> struct X x; >> >> ? > > Essentially yes, but

Re: Determine more IVs to be non-overflowing

Jan Hubicka writes: > Bootstrapped/regtested x86_64-linux, OK? > > * gcc.dg/tree-ssa/scev-14.c: new testcase. FAIL: gcc.dg/tree-ssa/scev-14.c scan-tree-dump-not ivopts "Overflowness wrto loop niter:\tOverflow" $ grep Overflowness scev-14.c.155t.ivopts Overflowness

Re: Determine more IVs to be non-overflowing

Richard Biener writes: > On Tue, 5 Jul 2016, Jan Hubicka wrote: > >> > On Tue, 5 Jul 2016, Richard Biener wrote: >> > >> > >given widest_int has only precision of TImode on x86_64? >> > >> > Is that the case? The comments say: >> > >> > It is really finite precision

Re: [PATCH][AArch64] Improve Cortex-A53 integer scheduler

On 05/07/16 16:00, Wilco Dijkstra wrote: > This patch improves the accuracy of the Cortex-A53 integer scheduler, > resulting in performance gains across a wide range of benchmarks. > > OK for commit? > OK. R. > ChangeLog: > 2016-07-05 Wilco Dijkstra > > *

Re: [BUILDROBOT] Selftest failed for i686-wrs-vxworks

On Thu, 2016-06-30 16:09:23 -0400, David Malcolm wrote: > On Thu, 2016-06-30 at 08:38 -0400, Nathan Sidwell wrote: > > > I haven't given it any additional manual testing so far. It's > > > pre-installation though. Maybe I'd just set WIND_BASE to some > > > arbitrary value,

Re: [patch] Fix type merging deficiency during WPA

> So this is sth like (invalid C) > > t.h > --- > int n; > struct X { int x[n]; }; > > t1.c > -- > #include "t.h" > struct X x; > t2.c > -- > #include "t.h" > struct X x; > > ? Essentially yes, but with a single definition for 'n' and references to it. > It's not obvious from the fix (which I

Re: Use iv_can_overflow_p in ivopts

On Tue, 5 Jul 2016, Jan Hubicka wrote: > Hi, > this patch makes ivopts to use iv_can_overflow_p on its candidates. This helps > to determine if candidate wraps in case it is not directly originating from IV > variable (i.e. it is derived IV or artificial one). For those we can not use > type

Re: Determine more IVs to be non-overflowing

On Tue, 5 Jul 2016, Jan Hubicka wrote: > > On Tue, 5 Jul 2016, Richard Biener wrote: > > > > >given widest_int has only precision of TImode on x86_64? > > > > Is that the case? The comments say: > > > > It is really finite precision math where the precision is 4 times the > > size of

[Committed] S/390: Fix vecinit expansion.

The fallback routine in the S/390 vecinit expander did not check whether each of the initializer elements is a proper general_operand. Since revision r236582 the expander is invoked also with e.g. symbol refs with an odd addend resulting in invalid insns. Fixed by forcing the element into a