Re: [RS6000] cost SLOW_UNALIGNED_ACCESS

On Tue, Aug 02, 2016 at 10:31:33AM -0500, Segher Boessenkool wrote: > On Wed, Aug 03, 2016 at 12:05:07AM +0930, Alan Modra wrote: > > As noted in the last patch, rs6000_rtx_costs ought to cost slow > > unaligned mems. This stops combine merging loads/stores with a > > mode-changing SET subreg, if

Re: [RS6000] Remove negative from option help strings

On Tue, Aug 02, 2016 at 10:09:15AM -0500, Segher Boessenkool wrote: > On Wed, Aug 03, 2016 at 12:00:09AM +0930, Alan Modra wrote: > > If -m/-mno- were printed when displaying help then it > > would be appropriate to show "Use/do not use" and similar, but we > > don't see any mention of -mno-: The

[openacc] add a warning for non-contiguous data clauses

OpenACC requires that fortran array pointers must represent contiguous arrays. As of now, the fortran FE in trunk treats non-contiguous array pointers as an errors, at least for explicit data clauses. This patch relaxes this errors to warnings for two reasons: 1. A lot of existing code don't

[PATCH] Teach VRP to truncate the case ranges of a switch

VRP currently has functionality to eliminate case labels that lie completely outside of the switch operand's value range. This patch complements this functionality by teaching VRP to also truncate the case label ranges that partially overlap with the operand's value range. Bootstrapped and

Re: [PATCH] accept flexible arrays in struct in unions (c++/71912 - [6/7 regression])

It could be raised with WG14 for clarification or even proposed as a change but given existing practice I don't think it would be likely to gain committee support, or worth trying. It seems simpler and, IMO, more useful for portability to do what others do, at least in the potentially

Re: [RFC][IPA-VRP] Early VRP Implementation

Hi Richard, Thanks for the review. On 28/07/16 21:34, Richard Biener wrote: On Thu, Jul 28, 2016 at 9:35 AM, kugan wrote: Hi Richard, Thanks for the review. It seems that in your pop_value_range you assume you only pop one range per BB - while that's

Re: [PATCH] accept flexible arrays in struct in unions (c++/71912 - [6/7 regression])

On Tue, Aug 2, 2016 at 5:00 PM, Martin Sebor wrote: >>>struct S1 { >>> struct S2 { int i, a[]; } s2; >>> union U { int x; } u; >>>}; >>> >>> that need to be treated differently from this one: >>> >>>union U1 { >>> struct S { int i, a[]; } s; >>>

Go patch committed: add escape analysis debugging

This patch by Chris Manghane adds debugging to the escape analysis code. This debugging is designed to generate the same sort of output as the gc Go compiler, for easier comparison of results. Escape analysis is still not enabled by default. Bootstrapped and ran Go testsuite on

Re: [PATCH] accept flexible arrays in struct in unions (c++/71912 - [6/7 regression])

struct S1 { struct S2 { int i, a[]; } s2; union U { int x; } u; }; that need to be treated differently from this one: union U1 { struct S { int i, a[]; } s; union U2 { int x; } u2; }; Ah, I'm thinking of the following field as u/u2 rather than x. Why does it

patch to fix PR72778

The following patch fixes https://gcc.gnu.org/bugzilla/show_bug.cgi?id=72778 The patch was bootstrapped on x86-64. Committed as rev. 23900 Index: ChangeLog === --- ChangeLog (revision 238999) +++ ChangeLog (working copy)

Re: [PATCH, rs6000] Switch the rs6000 port over to LRA

On Tue, Aug 02, 2016 at 03:38:10PM -0500, Peter Bergner wrote: > On 8/2/16 3:30 PM, David Edelsohn wrote: > >>> * config/rs6000/rs6000.c (rs6000_option_override_internal): Make > >>> LRA > >>> the default for the rs6000 port. > > > >Okay. > > > >Do we eventually want to remove the

Re: [PATCH, rs6000] Switch the rs6000 port over to LRA

On 8/2/16 3:30 PM, David Edelsohn wrote: * config/rs6000/rs6000.c (rs6000_option_override_internal): Make LRA the default for the rs6000 port. Okay. Do we eventually want to remove the switch? I think we want to keep it for at least one release, so we can fall back to reload in

Re: [PATCH, rs6000] Switch the rs6000 port over to LRA

On Tue, Aug 2, 2016 at 4:20 PM, Segher Boessenkool wrote: > On Tue, Aug 02, 2016 at 03:17:45PM -0500, Peter Bergner wrote: >> Now that Vlad has fixed PR69847, which was the last problem holding the >> rs6000 port from switching from reload to LRA, we are ready to flip

Re: [PATCH] Fix wrong code on aarch64 due to paradoxical subreg

On 08/02/2016 06:46 PM, Segher Boessenkool wrote: On Tue, Aug 02, 2016 at 09:21:34AM -0600, Jeff Law wrote: However I think there are more paradoxical subregs generated all over, but the aarch64 insv code pattern did trigger more hidden bugs than any other port. It is certainly unfortunate

Re: [PATCH, rs6000] Switch the rs6000 port over to LRA

On Tue, Aug 02, 2016 at 03:17:45PM -0500, Peter Bergner wrote: > Now that Vlad has fixed PR69847, which was the last problem holding the > rs6000 port from switching from reload to LRA, we are ready to flip the > switch. > > Is the following ok once bootstrap/regtesting on both LE and BE > (32 &

[PATCH, rs6000] Switch the rs6000 port over to LRA

Now that Vlad has fixed PR69847, which was the last problem holding the rs6000 port from switching from reload to LRA, we are ready to flip the switch. Is the following ok once bootstrap/regtesting on both LE and BE (32 & 64 regtesting) comes out clean? Peter * config/rs6000/rs6000.c

Re: [PATCH,rs6000] Add built-in function support Power9 binary floating point operations

On Tue, Aug 02, 2016 at 03:03:42PM -0500, Pat Haugen wrote: > On 07/29/2016 10:47 AM, Kelvin Nilsen wrote: > > + "xsxexpdp %0,%x1" > > + [(set_attr "type" "fp")]) > > Type should be 'integer'. It has VSX regs as input, integer is worse than fpsimple here, I think? Or vecsimple, that seems

Re: [PATCH,rs6000] Add built-in function support Power9 binary floating point operations

On 07/29/2016 10:47 AM, Kelvin Nilsen wrote: > + "xsxexpdp %0,%x1" > + [(set_attr "type" "fp")]) Type should be 'integer'. > + "xsxsigdp %0,%x1" > + [(set_attr "type" "fp")]) 'integer' > + "xsiexpdp %x0,%1,%2" > + [(set_attr "type" "fp")]) 'fpsimple' > + "xscmpexpdp %0,%x1,%x2" > +

[PATCH] Fix std::wstring allocator tests

I had checks for defined(_GLIBCXX_USE_WCHAR_T) in these tests, which aren't needed because the testsuite skips directories called wchar_t if wide characters aren't supported. Some tests were also testing char not wchar_t! * testsuite/21_strings/basic_string/allocator/wchar_t/copy.cc:

[PATCH] Improve comments on check_v3_target_filesystem_ts

* testsuite/lib/libstdc++.exp (check_v3_target_filesystem_ts): Improve comments. Tested powerpc64-linux, committed to trunk. I'll backport this to the bgcc-5 and gcc-6 branches too. commit 7a49164cf103621d270b43f60e3f7695464e443c Author: Jonathan Wakely

[PATCH] Move dg-error directives to relevant lines

A few more tests that use hardcoded dg-error line numbers, but could use implied ones. * testsuite/19_diagnostics/error_code/operators/bool_neg.cc: Move dg-error to relevant line. * testsuite/19_diagnostics/error_condition/operators/bool_neg.cc: Likewise.

[PATCH] adjust spelling of constant expression in C++ diagnostics

My recently committed patch for c++/60760 triggered test suite failures in ILP32 mode due to a couple of problems: 1) The test assumed that (void*)1 will appear in GCC diagnostics as 1ul, which is correct in LP64 but not in ILP32. 2) GCC is inconsistent in how it spells "constant expression."

Re: patch to fix PR69847

On Tue, Aug 2, 2016 at 9:09 AM, Vladimir Makarov wrote: > The following patch is for > > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=69847 > > The patch implements an invariant inheritance and some hard reg assignment > improvements in LRA. Actually I tried several

Re: [PATCH] c++/60760 - arithmetic on null pointers should not be allowed in constant expressions

On 08/02/2016 12:34 AM, Thomas Schwinge wrote: Hi! On Wed, 6 Jul 2016 16:20:44 -0600, Martin Sebor wrote: PR c++/60760 - arithmetic on null pointers should not be allowed in constant expressions PR c++/71091 - constexpr reference bound to a null pointer dereference

Re: [PATCH] Fix wrong code on aarch64 due to paradoxical subreg

On 08/02/2016 11:46 AM, Richard Biener wrote: But we love to exploit undefined behavior elsewhere, too. Now the init-regs pass comes to my mind again (papering over issues elsewhere).. True. I just haven't seen that the don't care bits created by paradoxical subregs has actually been all that

Re: [RS6000] power8 unaligned fp load/store

On Wed, Aug 03, 2016 at 12:07:32AM +0930, Alan Modra wrote: > According to the POWER8 Processor User’s Manual and some > experimentation on power8 hardware, unaligned fp load/store on power8 > does not invoke the alignment interrupt. Thus SLOW_UNALIGNED_ACCESS > should not return true for these

Re: [PATCH] Fix wrong code on aarch64 due to paradoxical subreg

On August 2, 2016 5:21:34 PM GMT+02:00, Jeff Law wrote: >On 08/01/2016 05:31 PM, Segher Boessenkool wrote: >> Hi, >> >> On Mon, Aug 01, 2016 at 06:52:54PM +, Bernd Edlinger wrote: >>> On 08/01/16 19:54, Jeff Law wrote: Looks like you've probably nailed it. It'll be

Re: [PATCH] Fix wrong code on aarch64 due to paradoxical subreg

On Tue, Aug 02, 2016 at 09:21:34AM -0600, Jeff Law wrote: > >>However I think there are more paradoxical subregs generated all over, > >>but the aarch64 insv code pattern did trigger more hidden bugs than > >>any other port. It is certainly unfortunate that the major source > >>of paradoxical

patch to fix PR69847

The following patch is for https://gcc.gnu.org/bugzilla/show_bug.cgi?id=69847 The patch implements an invariant inheritance and some hard reg assignment improvements in LRA. Actually I tried several approaches to implement this. This patch is what worked best (a compromise between

Re: Create multiple directory through fixinc.in script.

On 08/02/2016 12:28 AM, mbilal wrote: Hi Jeff, On 01/08/2016 21:07, Jeff Law wrote: On 08/01/2016 08:55 AM, mbilal wrote: Hi, This patch fixes the mkheaders directory creation. It failed to create the multiple multilib directory on some cases. e.g For i686-pc-linux-gnu target config, I have

Re: [RS6000] cost SLOW_UNALIGNED_ACCESS

On Wed, Aug 03, 2016 at 12:05:07AM +0930, Alan Modra wrote: > As noted in the last patch, rs6000_rtx_costs ought to cost slow > unaligned mems. This stops combine merging loads/stores with a > mode-changing SET subreg, if the load/store in the subreg mode would > be slow. Costing slow mems at

Re: [PATCH] Fix wrong code on aarch64 due to paradoxical subreg

On 08/01/2016 05:31 PM, Segher Boessenkool wrote: Hi, On Mon, Aug 01, 2016 at 06:52:54PM +, Bernd Edlinger wrote: On 08/01/16 19:54, Jeff Law wrote: Looks like you've probably nailed it. It'll be interesting see if there's any fallout (though our RTL optimizer testing is pretty weak, so

Re: [RS6000] Force source of fix_truncsi2 to reg

On Wed, Aug 03, 2016 at 12:02:54AM +0930, Alan Modra wrote: > So this patch isn't a particularly good solution to pr71680, but > a) force_reg for an operand that must be a reg is 100% safe, and > b) it's good to expose more combine opportunities. I'm not sure it actually does fix the PR. But the

Re: [RS6000] Remove negative from option help strings

On Wed, Aug 03, 2016 at 12:00:09AM +0930, Alan Modra wrote: > If -m/-mno- were printed when displaying help then it > would be appropriate to show "Use/do not use" and similar, but we > don't see any mention of -mno-: The help info is printed > against -m so IMO it should say what -m does. Many

Re: [PATCH PR71734] Add missed check that reference defined inside loop.

Hi Richard, Did you have a chance to look at this patch? Thanks. 2016-07-29 17:00 GMT+03:00 Yuri Rumyantsev : > Hi Richard. > > It turned out that the fix proposed by you does not work for liggomp > tests simd3 and simd4. > The reason is that we can't change safelen value

Re: [RS6000] Delete duplicate code

On Tue, Aug 02, 2016 at 11:58:37PM +0930, Alan Modra wrote: > This removes the duplicate (TARGET_POWERPC64 && size == 16) block. > Bootstrapped and regression tested powerpc64le-linux. That looks okay, thanks, Segher

[RS6000] power8 unaligned fp load/store

According to the POWER8 Processor User’s Manual and some experimentation on power8 hardware, unaligned fp load/store on power8 does not invoke the alignment interrupt. Thus SLOW_UNALIGNED_ACCESS should not return true for these accesses. It so happens that we already have an undocumented switch

[RS6000] cost SLOW_UNALIGNED_ACCESS

As noted in the last patch, rs6000_rtx_costs ought to cost slow unaligned mems. This stops combine merging loads/stores with a mode-changing SET subreg, if the load/store in the subreg mode would be slow. Costing slow mems at 100 insns is just an order of magnitude estimate. (The alignment

[RS6000] Force source of fix_truncsi2 to reg

This is a hack I tried to avoid having to poke at lra code for pr71680.. The idea of adding force_reg here was that it removes subregs from fix_trunc, emitting the subreg mode conversion in a separate set insn. That avoids the underlying lra issue, by virtue of combine merging the SF subreg with

[RS6000] Remove negative from option help strings

If -m/-mno- were printed when displaying help then it would be appropriate to show "Use/do not use" and similar, but we don't see any mention of -mno-: The help info is printed against -m so IMO it should say what -m does. * config/rs6000/rs6000.opt: Remove negatives from help strings

[RS6000] Delete duplicate code

This removes the duplicate (TARGET_POWERPC64 && size == 16) block. Bootstrapped and regression tested powerpc64le-linux. * config/rs6000/rs6000.c (rs6000_secondary_reload_direct_move): Delete duplicated code. diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c

[PATCH] Fix ICE on invalid variable template instantiation (PR c++/72759)

This patch fixes PR c++/72759. The problem seems to be that when instantiating a variable template, we fail to propagate error_mark_node when its template arguments are erroneous, and we instead build a bogus TEMPLATE_ID_EXPR which later confuses check_initializer(). Does this look OK to commit

[Patch AArch64 Obvious] Fix Bootstrap for my mistake in r238977

Hi, I deleted an 'f' halfway through a line when applying r238977. Not sure how I managed it, but it was entirely my fault. Fixed in the obvious way. Thanks, James --- 2016-02-08 James Greenhalgh * config/aarch64/arm_neon.h (vminnm_f64): Add back missing

Re: [PATCH] Math special functions testsuite cleanup

On 02/08/16 14:31 +0100, Jonathan Wakely wrote: This latest set of patches for the testsuite are for the maths special functions. This test for was defining __STDCPP_WANT_MATH_SPEC_FUNCS__ so it was testing the functions in namespace std, not std::tr1. I assume that's just a mistake (Ed?) and

[PATCH, LRA] PR71680, Reload of slow mems

This is a patch for a problem in lra, triggered by the rs6000 backend not allowing SImode in floating point registers. First, some analysis. pr71680.c -m64 -mcpu=power8 -O1 -mlra, ira output showing two problem insns. (insn 7 5 26 3 (set (reg:SI 159 [ a ]) (mem/c:SI (reg/f:DI 158) [1 a+0

[PATCH] Skip C tests if test flags include C++ options

There are two C files in the libstdc++ testsuite, this skips them when -std=gnu++NN or similar appears in the options, to avoid FAILs due to cc1: warning: command line option ‘-std=c++11’ is valid for C++/ObjC++ but not for C * testsuite/18_support/bad_exception/23591_thread-1.c: Skip

[PATCH] Math special functions testsuite cleanup

This latest set of patches for the testsuite are for the maths special functions. This test for was defining __STDCPP_WANT_MATH_SPEC_FUNCS__ so it was testing the functions in namespace std, not std::tr1. I assume that's just a mistake (Ed?) and so have removed it. This allows the test to be

Re: RFA: new pass to warn on questionable uses of alloca() and VLAs

On 08/01/2016 04:35 PM, Joseph Myers wrote: On Tue, 19 Jul 2016, Aldy Hernandez wrote: + // Do not warn on VLAs occurring in a loop, since VLAs are + // guaranteed to be cleaned up when they go out of scope. + // That is, there is a corresponding __builtin_stack_restore +

Re: [ARM][PATCH] Add support for overflow add, sub, and neg operations

Hi Michael, On 2 August 2016 at 11:25, Kyrill Tkachov wrote: > Hi Michael, > > > On 02/08/16 09:13, Michael Collison wrote: >> >> Hi, >> >> This patch improves code generations for builtin arithmetic overflow >> operations for the arm backend. As an example for a

Re: [patch,avr] PR70677: Use -fno-caller-saves for avr

Georg-Johann Lay writes: > On 02.08.2016 06:50, Senthil Kumar Selvaraj wrote: >> >> Denis Chertykov writes: >> >>> 2016-08-01 15:17 GMT+03:00 Georg-Johann Lay : Problem with -fcaller-saves is that there are situations where it triggers an expensive frame just to store a

Re: [PATCH] Update libstdc++ baseline symbols

Hi Jonathan, > I need to bump the library version to libstdc++.so.6.0.23 so we need > updated baselines for the 6.0.22 version, which this patch provides. > > I've only generated new baselines for x86 (not including x32) and ppc, > so could target maintainers (or anyone with suitable targets

Re: [patch,avr] PR70677: Use -fno-caller-saves for avr

On 02.08.2016 06:50, Senthil Kumar Selvaraj wrote: Denis Chertykov writes: 2016-08-01 15:17 GMT+03:00 Georg-Johann Lay : Problem with -fcaller-saves is that there are situations where it triggers an expensive frame just to store a variable around a function call even though

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[PATCH] Skip scan-assembler test when -flto is used

Testing with -flto revealed a scan-assembler test that fails. * testsuite/29_atomics/atomic_flag/test_and_set/explicit-hle.cc: Skip test if -flto used. Tested x86_64-linux, committed to trunk. commit 8d3c6b7714a521ae5aff7843a4187679d94f4176 Author: Jonathan Wakely

[PATCH] Support using -flto with libstdc++ testsuite

Richi noticed that using -flto in the testsuite fails badly. It turns out to be because the support files in libtestc++.a get built with -flto, but then ar and ranlib don't know what to do with those LTO objects. We investigated how to pass the LTO plugin to ar and ranlib but the simplest

Re: [PATCH] Add more Aarch64 NEON intrinsics

On Mon, Aug 01, 2016 at 12:12:03PM +0100, Tamar Christina wrote: > Hi all, > > This patch adds the following NEON intrinsics to the ARM Aarch64 GCC: > > * vmaxnm_f64 > * vminnm_f64 > * vmax_f64 > * vmin_f64 > > Some refactoring was done as well to remove some superfluous UNSPECS > and iterators

Re: [ARM][PATCH] Add support for overflow add, sub, and neg operations

Hi Michael, On 02/08/16 09:13, Michael Collison wrote: Hi, This patch improves code generations for builtin arithmetic overflow operations for the arm backend. As an example for a simple test case such as: int fn3 (int x, int y, int *ovf) { int res; *ovf = __builtin_sadd_overflow (x,

[ARM][PATCH] Add support for overflow add, sub, and neg operations

Hi, This patch improves code generations for builtin arithmetic overflow operations for the arm backend. As an example for a simple test case such as: int fn3 (int x, int y, int *ovf) { int res; *ovf = __builtin_sadd_overflow (x, y, ); return res; } Current trunk at -O2 generates fn3:

Re: [PATCH] c++/60760 - arithmetic on null pointers should not be allowed in constant expressions

Hi! On Wed, 6 Jul 2016 16:20:44 -0600, Martin Sebor wrote: > PR c++/60760 - arithmetic on null pointers should not be allowed in constant > expressions > PR c++/71091 - constexpr reference bound to a null pointer dereference >accepted > > [...] > *

Re: Create multiple directory through fixinc.in script.

Hi Jeff, On 01/08/2016 21:07, Jeff Law wrote: On 08/01/2016 08:55 AM, mbilal wrote: Hi, This patch fixes the mkheaders directory creation. It failed to create the multiple multilib directory on some cases. e.g For i686-pc-linux-gnu target config, I have following 'fixinc_list' for multilibs.