[PATCH PR96357][GCC][AArch64]: could not split insn UNSPEC_COND_FSUB with AArch64 SVE

Hi, Problem is related to that operand 4 (In original pattern *cond_sub_any_const) is no longer the same as operand 1, and so the pattern doesn't match the split condition. Pattern *cond_sub_any_const is being split by this patch into two separate patterns: * Pattern *cond_sub_relaxed_const now

Re: [PATCH][testsuite, nvptx] Add effective target sync_int_long_stack

On Aug 12, 2020, at 6:57 AM, Tom de Vries wrote: > > The nvptx target currently doesn't support effective target sync_int_long, > although it has support for 32-bit and 64-bit atomic. > > When enabling sync_int_long for nvptx, we run into a failure in > gcc.dg/pr86314.c: > ... > nvptx-run:

Re: [PATCH] rs6000: Rename instruction xvcvbf16sp to xvcvbf16spn

On 8/18/20 1:34 PM, Segher Boessenkool wrote: > On Tue, Aug 18, 2020 at 01:30:53PM -0500, Peter Bergner wrote: >> The xvcvbf16sp mnemonic, which was just added in ISA 3.1 has been renamed >> to xvcvbf16spn, to make it consistent with the other non-signaling conversion >> instructions which all end

Re: [PATCH v2] rs6000: ICE when using an MMA type as a function param or return value [PR96506]

On 8/13/20 4:27 PM, Segher Boessenkool wrote: > Anyway, okay for trunk and backports. Thanks! Ok, I committed this to trunk and waited a few days and then pushed this to GCC 10 release branch too. Thanks! Peter

Re: [PATCH 4/4][PR target/88808]Enable bitwise operator for AVX512 masks.

On Mon, Aug 17, 2020 at 6:08 PM Uros Bizjak wrote: > > On Fri, Aug 14, 2020 at 10:26 AM Hongtao Liu wrote: > > > > Enable operator or/xor/and/andn/not for mask register, kxnor is not > > enabled since there's no corresponding instruction for general > > registers. > > > > gcc/ > > PR

Re: [PATCH 2/4][PR target/88808]Enable bitwise operator for AVX512 masks.

On Mon, Aug 17, 2020 at 5:34 PM Uros Bizjak wrote: > > On Fri, Aug 14, 2020 at 10:24 AM Hongtao Liu wrote: > > > > Enable direct move between masks and gprs in pass_reload with > > consideration of cost model. > > > > Changelog > > gcc/ > > * config/i386/i386.c

Re: [PATCH 2/4][PR target/88808]Enable bitwise operator for AVX512 masks.

On Wed, Aug 19, 2020 at 10:17 AM Hongtao Liu wrote: > > On Mon, Aug 17, 2020 at 5:34 PM Uros Bizjak wrote: > > > > On Fri, Aug 14, 2020 at 10:24 AM Hongtao Liu wrote: > > > > > > Enable direct move between masks and gprs in pass_reload with > > > consideration of cost model. > > > > > >

Re: [PATCH 1/4][PR target/88808]Enable bitwise operator for AVX512 masks.

On Mon, Aug 17, 2020 at 5:20 PM Uros Bizjak wrote: > > On Fri, Aug 14, 2020 at 10:22 AM Hongtao Liu wrote: > > > > Hi: > > First, since avx512 masks involve both vector isa and general part, > > so i add both maintainers to the maillist. > > > > I'm doing this in 4 steps: > > 1 - Add cost

[committed] analyzer: consider initializers for globals [PR96651]

PR analyzer/96651 reports a false positive in which a global that can't have been touched yet is checked in "main". The analyzer fails to reject code paths in which the initial value of the global makes the path condition impossible. This patch detects cases where the code path begins at the

[committed] analyzer: fix ICE with negative bit offsets [PR96648]

PR analyzer/96648 reports an ICE within get_field_at_bit_offset due to a negative bit offset, arising due to pointer arithmetic. This patch replaces an assertion with handling for this case, fixing the ICE. Successfully bootstrapped & regrtested on x86_64-pc-linux-gnu. Pushed to master as

Re: [PATCH] rs6000: Add builtins for fegetround, feclearexcept and feraiseexcept [PR94193]

Hi! On Fri, Aug 14, 2020 at 07:54:23PM -0300, Raoni Fassina Firmino via Gcc-patches wrote: > So, this patch adds new rs6000 expand optimizations for fegetround and > for some calls to feclearexcept and feraiseexcept. All of them C99 > functions from fenv.h And the fenv.h implementation can then

Re: [PATCH] Fortran : rejected f0.d edit descriptor PR96436

On 8/17/20 12:31 AM, Mark Eggleston wrote: Please find attached a patch for PR96436. OK to commit? Looks good to me.  Thanks for fixing this. Regards, Jerry

Re: [PATCH v2] libgcc: Use `-fasynchronous-unwind-tables' for LIB2_DIVMOD_FUNCS

On 06/08/2020 14:04, Maciej W. Rozycki via Gcc-patches wrote: > Complement commit b932f770f70d ("x86_64 frame unwind info"), SVN r46374, > , and replace > `-fexceptions -fnon-call-exceptions' with `-fasynchronous-unwind-tables' > in

[PATCH] i386: Add c99 runtime requirement to math optimisation tests

A number of i386 math optimisation tests are looking assembly instructions that are only emitted when the compiler knows the target has a C99 libm available. Since targets like *-elf may not have such a libm, a C99 runtime requirement is added to these tests. Tested on x86-elf and x86_64-elf

[PATCH] testsuite: require c99 runtime for trigonometric optimisation tests

A number of optimisation that simplify trigonometric expressions are only performed when the compiler knows the target has a C99 libm available. Since targets like *-elf may not have such a libm, a C99 runtime requirement is added to these tests. Tested on x86-elf and x86_64-elf hosted on

[PATCH] i386: Cleanup i386/i386elf.h and align it's return convention with the SVR4 ABI

As observed a number of years ago in the following thread, i386/i386elf.h has not been kept up to date: https://gcc.gnu.org/pipermail/gcc/2013-August/209981.html This patch does the following cleanup: 1. The return convention now follows the i386 and x86_64 SVR4 ABIs again. As discussed in

c++: alias template template_info setting

During the construction of alias templates we can alter its template_info. This is really weird, because that's morally immutable data. In this case it's ok, but let's not create a duplicate template_info, and add asserts to make sure it is changing in exactly the way we expect. Needless to

Re: [EXTERNAL] Re: [Patch 1/5] rs6000, Add 128-bit sign extension support

On Thu, Aug 13, 2020 at 06:53:56PM -0500, will schmidt wrote: > On Thu, 2020-08-13 at 17:55 -0500, Segher Boessenkool wrote: > > > As long as there are no issues defining the builtins for 3.0 here. > > > AFAIK they are not documented in ISA 3.0. This is a happy accident > > > that these ISA 3.1

Re: [RFC PATCH v1 1/1] PPC64: Implement POWER Architecture Vector Function ABI.

On Tue, Aug 18, 2020 at 07:14:19PM +, GT wrote: > > That sounds like libmvec? > > > > I still don't know what this is. > > Yes, it is libmvec. > > Now look at what GCC does to the code in Examples 1 and 2 at this link: > https://sourceware.org/glibc/wiki/libmvec > > x86_64 added

[PATCH 2/2] c++: Rewrite members for all deduction guides. [PR96199]

After the last patch, it occurred to me that we could run into the specialization issue with non-alias deduction guides as well, so this patch extends the rewriting to C++17 mode. Doing this revealed that we weren't properly pushing into class scope for normalization. Tested x86_64-pc-linux-gnu,

[PATCH 1/2] c++: Handle enumerator in C++20 alias CTAD. [PR96199]

To form a deduction guide for an alias template, we substitute the template arguments from the pattern into the deduction guide for the underlying class. In the case of B(A1), that produces B(A1::X>) -> B. But since an enumerator doesn't have its own template info, and B is a dependent scope,

[PATCH, committed] PR fortran/96613,96686 - Fix type/kind issues, temporaries evaluating MIN/MAX

There was another issue (PR96686) with MIN/MAX for character arguments of different kind. Character arguments to MIN/MAX are a Fortran 2003 feature, so there is no real reason to have a new GNU extension, and no related legacy code. Instead of ICEing, we now unconditionally generate an error

[committed] [OG10] Backport OpenMP-related patches

Hello I have now backported a number of OpenMP-related patches from master to devel/omp/gcc-10. These are: - Fortran: Fix character-kind=4 substring resolution (PR95837) (commit f48bffe70cba310461ec19ffcd07c573a6b86575) - libgomp.fortran/struct-elem-map-1.f90: Add char kind=4 tests (commit

[committed] rs6000: unaligned VSX in memcpy/memmove expansion

I've modified slightly per Will & Segher's comments, re-regstrapped and posting what I've actually committed. Aaron This patch adds a few new instructions to inline expansion of memcpy/memmove. Generation of all these are controlled by the option -mblock-ops-unaligned-vsx which is set on by

Re: [RFC PATCH v1 1/1] PPC64: Implement POWER Architecture Vector Function ABI.

‐‐‐ Original Message ‐‐‐ On Monday, August 17, 2020 5:28 PM, Segher Boessenkool wrote: > On Mon, Aug 17, 2020 at 05:44:46PM +, GT wrote: > > > > This is about the Power binding to some OpenMP API, right? It has > > > nothing to do with "vector" or "ABI" -- we have vectors already,

[committed] use byte_representation instead of string_constant (PR 96670)

The recent enhancement to memchr/memcmp folding introduced two bugs (that I know of). The attached patch fixes the one where a call to the string_constant function that would previously be guaranteed to succeed now fails as a result of the function only handling strings and not other types. The

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Re: [PATCH] rs6000: Rename instruction xvcvbf16sp to xvcvbf16spn

On Tue, Aug 18, 2020 at 01:30:53PM -0500, Peter Bergner wrote: > The xvcvbf16sp mnemonic, which was just added in ISA 3.1 has been renamed > to xvcvbf16spn, to make it consistent with the other non-signaling conversion > instructions which all end with "n". The only use of this instruction is in

[PATCH] rs6000: Rename instruction xvcvbf16sp to xvcvbf16spn

The xvcvbf16sp mnemonic, which was just added in ISA 3.1 has been renamed to xvcvbf16spn, to make it consistent with the other non-signaling conversion instructions which all end with "n". The only use of this instruction is in an MMA conversion built-in function, so there is little to no

Re: [PATCH] libstdc++: testsuite: Address random failure in pthread_create() [PR54185]

On 18/08/20 11:20 -0400, Lewis Hyatt wrote: On Tue, Aug 18, 2020 at 09:43:31AM +0100, Jonathan Wakely wrote: On 13/08/20 18:15 -0400, Lewis Hyatt via Libstdc++ wrote: > Hello- > > The attached patch was discussed briefly on PR 54185 here: > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=54185#c14

[PING][PATCH v2] libgcc: Use `-fasynchronous-unwind-tables' for LIB2_DIVMOD_FUNCS

On Thu, 6 Aug 2020, Maciej W. Rozycki wrote: > Complement commit b932f770f70d ("x86_64 frame unwind info"), SVN r46374, > , and replace > `-fexceptions -fnon-call-exceptions' with `-fasynchronous-unwind-tables' > in LIB2_DIVMOD_FUNCS

Re: [PATCH] arm: Require MVE memory operand for destination of vst1q intrinsic

On Thu, Aug 13, 2020 at 2:18 PM Joe Ramsay wrote: > > From: Joe Ramsay > > Hi, > > Previously, the machine description patterns for vst1q accepted a generic > memory > operand for the destination, which could lead to an unrecognised builtin when > expanding vst1q* intrinsics. This change fixes

Re: [Patch] Fortran: Add 'device_type' clause to OpenMP's declare target

Hi Tobias, I am not deep in OMP dev, i.e., not at all, but this does not make sense to me: @@ -2397,6 +2401,22 @@ mio_symbol_attribute (symbol_attribute *attr) == OMP_REQ_ATOMIC_MEM_ORDER_RELAXED) MIO_NAME (ab_attribute) (AB_OMP_REQ_MEM_ORDER_RELAXED, attr_bits);

Re: [Patch, fortran, coarray] Fix obvious typo in co_broadcast's argument assembly

Hi Tobias, On Tue, 18 Aug 2020 19:14:30 +0200 Tobias Burnus wrote: > On 8/18/20 7:04 PM, Andre Vehreschild wrote: > > > attached patch fixes an obvious typo in the routine gathering arguments for > > co_broadcast(). See pr94958 for a detailed analysis, please. > > LGTM – except that I do

Re: [Patch, fortran, coarray] Fix obvious typo in co_broadcast's argument assembly

On 8/18/20 7:04 PM, Andre Vehreschild wrote: attached patch fixes an obvious typo in the routine gathering arguments for co_broadcast(). See pr94958 for a detailed analysis, please. LGTM – except that I do not like the ChangeLog entry. It sounds like a mispelling in terms of a comment or

Re: PING: Fwd: [PATCH 2/2] Decouple adjust_range_from_scev from vr_values and value_range_equiv.

On 8/18/20 12:38 PM, Aldy Hernandez wrote: And here's the patch without the sanity check. Aldy That diff was difficult to read.. I had to apply the patch to really follow it :-P Anyway, yeah, this looks better.  effectively, you have   1) left the input range "vr" range merging in

[Patch, fortran, coarray] Fix obvious typo in co_broadcast's argument assembly

Hi all, attached patch fixes an obvious typo in the routine gathering arguments for co_broadcast(). See pr94958 for a detailed analysis, please. Regtests ok on FC31/x86_64. Will commit as obvious on Thursday, if no one objects. Regards, Andre -- Andre Vehreschild * Email: vehre ad gmx

Re: [PATCH] AArch64: Add if condition in aarch64_function_value [PR96479]

qiaopeixin writes: > Hi Richard, > > Thanks for the review and explanation. > > The previous fix adding if condition of TARGET_FLOAT does crash glibc-2.29. > > I checked the past log of writing the function aarch64_init_cumulative_args, > and did not find the reason why Alan Lawrence added

Re: [PATCH] doc: add return type for functions in gimple.texi

Hu Jiangping writes: > This patch add the return type for some functions in gimple.texi, > to make the context unified. OK for trunk? LGTM, thanks. Pushed to master. Richard > > Tested on x86_64. > > Regards! > Hujp > > --- > gcc/doc/gimple.texi | 6 +++--- > 1 file changed, 3 insertions(+),

Re: PING: Fwd: [PATCH 2/2] Decouple adjust_range_from_scev from vr_values and value_range_equiv.

And here's the patch without the sanity check. Aldy diff --git a/gcc/vr-values.c b/gcc/vr-values.c index fe51a6faeb8..9b21441dff3 100644 --- a/gcc/vr-values.c +++ b/gcc/vr-values.c @@ -1006,7 +1006,7 @@ vr_values::extract_range_from_comparison (value_range_equiv *vr, overflow. */ static

Re: [PATCH] improve memcmp and memchr constant folding (PR 78257)

On 8/15/20 8:19 AM, Christophe Lyon wrote: Hi Martin, On Sat, 15 Aug 2020 at 01:14, Martin Sebor via Gcc-patches wrote: On 8/13/20 11:44 AM, Martin Sebor wrote: On 8/13/20 10:21 AM, Jeff Law wrote: On Fri, 2020-07-31 at 17:55 -0600, Martin Sebor via Gcc-patches wrote: The folders for

Re: PING: Fwd: [PATCH 2/2] Decouple adjust_range_from_scev from vr_values and value_range_equiv.

On 8/17/20 5:59 PM, Andrew MacLeod wrote: On 8/17/20 6:04 AM, Aldy Hernandez wrote: On 8/14/20 7:16 PM, Andrew MacLeod wrote: On 8/14/20 12:05 PM, Aldy Hernandez wrote: I made some minor changes to the function comments. gcc/ChangeLog: * vr-values.c (check_for_binary_op_overflow):

Re: [PATCH] arm: Add +nomve and +nomve.fp options to -mcpu=cortex-m55

On 10/08/2020 15:21, Joe Ramsay wrote: > From: Joe Ramsay > > Hi, > > This patch rearranges feature bits for MVE and FP to implement the > following flags for -mcpu=cortex-m55. > > - +nomve:equivalent to armv8.1-m.main+fp.dp+dsp. > - +nomve.fp: equivalent to armv8.1-m.main+mve+fp.dp

[committed] update native_encode_expr description

I committed the change below updating and completing the description of the native_encode_expr function. Martin diff --git a/gcc/fold-const.c b/gcc/fold-const.c index 9fc4c2a06fb..7c4d1eff215 100644 --- a/gcc/fold-const.c +++ b/gcc/fold-const.c @@ -7875,11 +7875,12 @@ native_encode_string

Re: [PATCH][GCC-10 Backport] arm: Enable no-writeback vldr.16/vstr.16.

On 05/08/2020 10:28, Joe Ramsay wrote: > From: Joe Ramsay > > Hi, > > There was previously no way to specify that a register operand cannot > have any writeback modifiers, and as a result the argument to vldr.16 > and vstr.16 could be erroneously output with post-increment. This > change adds a

Re: [PATCH] middle-end: Fix PR middle-end/85811: Introduce tree_expr_maybe_nan_p et al.

On Mon, 17 Aug 2020, Segher Boessenkool wrote: > Ah, so "When both arguments are NaNs, the return value should be a qNaN" > means the QNaN corresponding to eother x or y. I see, thanks! Yes. (The precise choice of NaN result given a NaN input is the subject of various "should"s, in 6.2.3 NaN

Re: [committed] i386: Rewrite restore_stack_nonlocal expander [PR96536].

On Tue, Aug 18, 2020 at 5:42 PM Uros Bizjak wrote: > > -fcf-protection code in restore_stack_nonlocal uses a branch based on > a clobber result. The patch adds missing compare and completely > rewrites the expander to use high-level functions in RTL construction. Backported gcc-10 version

[committed] i386: Rewrite restore_stack_nonlocal expander [PR96536].

-fcf-protection code in restore_stack_nonlocal uses a branch based on a clobber result. The patch adds missing compare and completely rewrites the expander to use high-level functions in RTL construction. 2020-08-18 Uroš Bizjak gcc/ChangeLog: PR target/96536 * config/i386/i386.md

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Re: [PATCH] libstdc++: testsuite: Address random failure in pthread_create() [PR54185]

On Tue, Aug 18, 2020 at 09:43:31AM +0100, Jonathan Wakely wrote: > On 13/08/20 18:15 -0400, Lewis Hyatt via Libstdc++ wrote: > > Hello- > > > > The attached patch was discussed briefly on PR 54185 here: > > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=54185#c14 > > The test case for this PR

Re: [PATCH] Add cold attribute to one time construction APIs

On 18/08/20 15:35 +0100, Jonathan Wakely wrote: On 17/08/20 18:15 +, Aditya K via Libstdc++ wrote: This would help compiler optimize local static objects. Added changelog. Please don't :-) GCC patch policies always said NOT to change the ChangeLog in the patch, because the ChangeLog

Re: [PATCH] Add cold attribute to one time construction APIs

On 17/08/20 18:15 +, Aditya K via Libstdc++ wrote: This would help compiler optimize local static objects. Added changelog. Please don't :-) GCC patch policies always said NOT to change the ChangeLog in the patch, because the ChangeLog files change so rapidly that it means by the time

Re: [PATCH v2] C-SKY: Support -mfloat-abi=hard.

Hi, Good points :) Jojo 在 2020年8月18日 +0800 AM10:40，Cooper Qu ，写道： > Hi Jojo, > > Nowhere is this rule directly stated. But there are indent options > showed in > https://www.gnu.org/prep/standards/html_node/Formatting.html#Formatting > corresponding to recommendations of C formatting

[committed] libstdc++: Remove redundant copying of std::async arguments [PR 69724]

As was previously done for std::thread, this removes an unnecessary copy of an rvalue of type thread::_Invoker. Instead of creating the rvalue and then moving that into the shared state, the member of the shared state is initialized directly from the forwarded callable and bound arguments. This

c++: Move hidden-lambda entity lookup checking

Hidden lambda entities only occur in block and class scopes. There's no need to check for them on every lookup. So moving that particular piece of validation to lookup_name_1, which cares. Also reordered the namespace and type checking, as that is also simpler. gcc/cp/ *

[PATCH] RX add control register PC

Hello, The following patch is adding the PC control register. It also updates the __builtin_rx_mvfc() function, since according to the documentation, the PC register cannot be specified as dest. The regression was tested with the following command: make -k check-gcc

Re: [PATCH] vxworks: Fix GCC selftests for *-wrs-vxworks7-* targets

Hi Iain, > On 18 Aug 2020, at 13:45, Iain Buclaw wrote: > > Attached is the change as per your proposal. > > * config/vxworks.h (VXWORKS_ADDITIONAL_CPP_SPEC): Replace -nostdinc > with -fself-tests. > #undef VXWORKS_ADDITIONAL_CPP_SPEC > #define VXWORKS_ADDITIONAL_CPP_SPEC

Re: [PATCH] AArch64: Add if condition in aarch64_function_value [PR96479]

On Tue, 18 Aug 2020 at 05:38, qiaopeixin wrote: > > Hi Richard, > > Thanks for the review and explanation. > > The previous fix adding if condition of TARGET_FLOAT does crash glibc-2.29. > > I checked the past log of writing the function aarch64_init_cumulative_args, > and did not find the

Re: [PATCH] vxworks: Fix GCC selftests for *-wrs-vxworks7-* targets

Excerpts from Olivier Hainque's message of August 18, 2020 10:01 am: > Hello Iain, > >> On 17 Aug 2020, at 10:08, Iain Buclaw wrote: >> >> Hi, >> >> Currently when building a cross-compiler targeting arm-wrs-vxworks7, the >> selftests fail unless the VSB_DIR environment variable is set. > >>

Re: [PATCH v2] options: Make --help= to emit values post-overrided

"Kewen.Lin" writes: > * opts-global.c (decode_options): Call target_option_override_hook > before it prints for --help=*. OK, thanks. Richard > diff --git a/gcc/opts-global.c b/gcc/opts-global.c > index b1a8429dc3c..69fe2b4f3b1 100644 > --- a/gcc/opts-global.c > +++

Re: [PATCH] aarch64: Don't generate invalid zero/sign-extend syntax

Richard Sandiford wrote: Alex Coplan writes: Note that an obvious omission here is that this patch does not touch the mult patterns such as *add__mult_. I found that I couldn't hit these patterns with C code since multiplications by powers of two always get turned into shifts by earlier RTL

[PATCH v2] options: Make --help= to emit values post-overrided

Hi Segher, on 2020/8/15 上午6:01, Segher Boessenkool wrote: > Hi! > > On Fri, Aug 14, 2020 at 01:42:24PM +0800, Kewen.Lin wrote: >>> I think personally I'd prefer an option (3): call >>> target_option_override_hook directly in decode_options, >>> if help_option_arguments is nonempty. Like you

[PATCH 3/4 v2] ivopts: Consider cost_step on different forms during unrolling

Hi Bin, > I see, it's similar to the auto-increment case where cost should be > recorded only once. So this is okay given 1) fine predicting > rtl-unroll is likely impossible here; 2) the patch has very limited > impact. > Really appreciate your time and patience! I extended the previous

Re: [PATCH] libstdc++: testsuite: Address random failure in pthread_create() [PR54185]

On 13/08/20 18:15 -0400, Lewis Hyatt via Libstdc++ wrote: Hello- The attached patch was discussed briefly on PR 54185 here: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=54185#c14 The test case for this PR sometimes fails due to random failures in pthread_create() that are not related to the

Re: [PATCH] aarch64: Don't generate invalid zero/sign-extend syntax

Alex Coplan writes: > Note that an obvious omission here is that this patch does not touch the > mult patterns such as *add__mult_. I found > that I couldn't hit these patterns with C code since multiplications by > powers of two always get turned into shifts by earlier RTL passes. If > there's a

Re: [PATCH] vxworks: Fix GCC selftests for *-wrs-vxworks7-* targets

Hello Iain, > On 17 Aug 2020, at 10:08, Iain Buclaw wrote: > > Hi, > > Currently when building a cross-compiler targeting arm-wrs-vxworks7, the > selftests fail unless the VSB_DIR environment variable is set. > The same !nostdinc condition is used for VXWORKS_ADDITIONAL_CPP_SPEC. > > OK for

[committed] d: Fix ICE Segmentation fault during RTL pass: expand on armhf/armel/s390x

Hi, This patch fixes an ICE that occurred when RTL was expanding D front-end generated code. Now DECL_BY_REFERENCE is only ever set if the return type is TREE_ADDRESSABLE. Regstrapped on x86_64-linux-gnu{-m64,-m32,-mx32} configurations, committed to mainline and backported to releases/gcc-10.

[PATCH]Adjust testcase.

Hi: Rewriting testcase with cpp source file, then compare operator could be used directly for vector, this would avoid impact of vectorizer. gcc/testsuite/ChangeLog: PR target/96667 * gcc.target/i386/avx512bw-pr96246-1.c: Moved to... *

*PING* / Re: [Patch] Fortran: Add 'device_type' clause to OpenMP's declare target

On 8/7/20 5:03 PM, Tobias Burnus wrote: This patch adds the device_type(any|nohost|host) clause for 'omp declare target' to Fortran. In OpenMP 5.0, it has no effect on variables but only on procedures – in TR8 (and later), it also affects variables. This patch adds this clause to either –

Re: [PATCH 3/3] Power10: Add tests for PCREL_OPT support.

[PATCH 3/3] Power10: Add tests for PCREL_OPT support. These are the tests for the PCREL_OPT support. gcc/testsuite/ 2020-08-18 Michael Meissner * gcc.target/powerpc/pcrel-opt-inc-di.c: New PCREL_OPT test. * gcc.target/powerpc/pcrel-opt-ld-df.c: New PCREL_OPT test. *

Re: [PATCH 2/3] Power10: Add PCREL_OPT store support.

[PATCH 2/3] Power10: Add PCREL_OPT store support. This patch adds support for optimizing power10 stores to an external variable to eliminate loading the address of the variable, and then doing a subsequent store using that address. I have built compilers with and without these set of 3 patches

Re: [PATCH 1/3] Power10: Add PCREL_OPT load support

[PATCH 1/3] Power10: Add PCREL_OPT load support. This patch adds support for optimizing power10 loads of an external variable to eliminate loading the address of the variable, and then doing a subsequent load using that address. I have built compilers with and without these set of 3 patches

[PATCH 0/3] Power10 PCREL_OPT support

The ELF-v2 ISA 3.1 support for Power10 has relocations to optimize cases where the code is references an external variable in only one location. This patch is similar to the optimizations that the linker already does to optimize TOC accesses. I will be submitting 3 patches as follow-ups to this

Re: [PATCH]Don't use pinsr for struct initialization.

On Tue, Aug 18, 2020 at 4:23 AM Hongtao Liu wrote: > > On Fri, Aug 14, 2020 at 5:57 PM Uros Bizjak wrote: > > > > On Fri, Aug 14, 2020 at 8:03 AM Hongtao Liu wrote: > > > > > > Hi: > > > For struct initialization, when it fits in a TImode, gcc will use > > > pinsr insn which causes poor