Re: [PATCH] combine: Fix simplify_comparison AND handling for WORD_REGISTER_OPERATIONS targets [PR109040]

On Mon, Apr 10, 2023 at 1:13 PM Hongtao Liu wrote: > > On Sun, Apr 9, 2023 at 9:15 AM Jeff Law via Gcc-patches > wrote: > > > > > > > > On 4/6/23 05:37, Jakub Jelinek wrote: > > > On Thu, Apr 06, 2023 at 12:51:20PM +0200, Eric Botcazou wrote: > > >>> If we want to fix it in the combiner, I think

Re: [PATCH] combine: Fix simplify_comparison AND handling for WORD_REGISTER_OPERATIONS targets [PR109040]

On Sun, Apr 9, 2023 at 9:15 AM Jeff Law via Gcc-patches wrote: > > > > On 4/6/23 05:37, Jakub Jelinek wrote: > > On Thu, Apr 06, 2023 at 12:51:20PM +0200, Eric Botcazou wrote: > >>> If we want to fix it in the combiner, I think the fix would be following. > >>> The optimization is about > >>>

[PATCH] RISC-V: avoid splitting small constant in i_extrabit pattern

From: Sinan Lin there is no need to split an xori/ori with an small constant. take the test case `int foo(int idx) { return idx|3; }` as an example, rv64im_zba generates: ori a0,a0,3 ret but, rv64im_zba_zbs generates: ori a0,a0,1 ori a0,a0,2

[PATCH] RISC-V: Allow LMUL = 2 auto-vectorization for zve32*

From: Juzhe-Zhong Since VNx1SI mode is nunits = [1,1] which will create ICE in Loop vectorizer of GCC. We disabled it. The current condition allows VNx4SI which LMUL = 4. We should be able to enable VNx2SI too. This patch is to enable auto-vectorization for VNx2SImode. gcc/ChangeLog: *

[PATCH] RISC-V: Fix EEW = 64 predicate

From: Juzhe-Zhong For EEW = 64 RVV operation, we use TARGET_MIN_VLEN > 32 to predicate such operations. This is incorrect. Since -march=rv*zve32*_zvl64b will make TARGET_MIN_VLEN = 64 which is not allowing EEW = 64 operations according to RVV ISA. Instead, we should use

Re: [PATCH v3] RISC-V: Fix regression of -fzero-call-used-regs=all

> > Do you need to save/restore the vector configuration before and after > > clearing the vector registers?If so, that seems to be missing. If > > not, it seems like a comment explaining why would be useful. > > I'll add some comments in the code and want to explain here first. > We need not

[PATCH v4] RISC-V: Fix regression of -fzero-call-used-regs=all

From: Yanzhang Wang This patch registers a riscv specific function to TARGET_ZERO_CALL_USED_REGS instead of default in targhooks.cc. It will clean gpr and vector relevant registers. PR 109104 gcc/ChangeLog: * config/riscv/riscv-protos.h (emit_hard_vlmax_vsetvl): *

RE: [PATCH v3] RISC-V: Fix regression of -fzero-call-used-regs=all

Thanks Jeff's comment. > Presumably the difficulty here is we need to find a suitable hard > register so that we can emit the vsetvl. Yes. We use the GPR which has been flagged in the need_zeroed_regs to hold the vl. There should be one GPR we can use, otherwise, will throw an exception. > Do

[PATCH] testsuite: update requires for powerpc/float128-cmp2-runnable.c

Hi, In this test case (float128-cmp2-runnable.c), the instruction xscmpexpqp is used to support a few builtins e.g. __builtin_vsx_scalar_cmp_exp_qp_eq on _Float128. This instruction handles the whole 128bits of the vector, and it is guarded by [ieee128-hw]. So, we may update the testcase to

[PATCH] gcc-13: Mention Intel AMX-COMPLEX ISA support and revise march support

Hi all, This patch mentions Intel AMX-COMPLEX ISA support in GCC 13. Also it revises the march support according to newly released Intel Architecture Instruction Set Extensions and Future Features. Ok for trunk? BRs, Haochen --- htdocs/gcc-13/changes.html | 10 +- 1 file changed, 9

New Swedish PO file for 'gcc' (version 13.1-b20230212)

Hello, gentle maintainer. This is a message from the Translation Project robot. A revised PO file for textual domain 'gcc' has been submitted by the Swedish team of translators. The file is available at: https://translationproject.org/latest/gcc/sv.po (This file,