[PATCH] x86: make VPTERNLOG* usable on less than 512-bit operands with just AVX512F

There's no reason to constrain this to AVX512VL, as the wider operation is not usable for more narrow operands only when the possible memory source is a non-broadcast one. This way even the scalar copysign3 can benefit from the operation being a single-insn one (leaving aside moves which the

[PATCH] x86: make better use of VBROADCASTSS / VPBROADCASTD

... in vec_dupv4sf / *vec_dupv4si. The respective broadcast insns are never longer (yet sometimes shorter) than the corresponding VSHUFPS / VPSHUFD, due to the immediate operand of the shuffle insns balancing the need for VEX3 in the broadcast ones. When EVEX encoding is required the broadcast

[PATCH] x86: add Bk and Br to comment list B's sub-chars

gcc/ * config/i386/constraints.md: Mention k and r for B. --- a/gcc/config/i386/constraints.md +++ b/gcc/config/i386/constraints.md @@ -162,7 +162,9 @@ ;; g GOT memory operand. ;; m Vector memory operand ;; c Constant memory operand +;; k TLS address that allows insn using

[PATCH] x86/AVX512: use VMOVDDUP for broadcast to V2DF

Like is already the case for the AVX/AVX2 form, VMOVDDUP - acting on double precision floating values - is more appropriate to use here, and it can also result in shorter insn encodings when source is memory or %xmm0...%xmm7, and no masking is applied (in allowing a 2-byte VEX prefix then instead

Re: [PATCH v5 6/6] libstdc++: make std::is_object dispatch to new built-in traits

On Tue, Jun 13, 2023 at 10:10 PM François Dumont wrote: > > > On 13/06/2023 00:22, Ken Matsui via Libstdc++ wrote: > > This patch gets std::is_object to dispatch to new built-in traits, > > __is_function, __is_reference, and __is_void. > > > > libstdc++-v3/ChangeLog: > > *

Re: [PATCH v5 6/6] libstdc++: make std::is_object dispatch to new built-in traits

On 13/06/2023 00:22, Ken Matsui via Libstdc++ wrote: This patch gets std::is_object to dispatch to new built-in traits, __is_function, __is_reference, and __is_void. libstdc++-v3/ChangeLog: * include/std/type_traits (is_object): Use new built-in traits, __is_function,

[PATCH] RISC-V: Use merge approach to optimize vector permutation

From: Juzhe-Zhong This patch is to optimize the permuation case that is suiteable use merge approach. Consider this following case: typedef int8_t vnx16qi __attribute__((vector_size (16))); #define MASK_16 0, 17, 2, 19, 4, 21, 6, 23, 8, 25, 10, 27, 12, 29, 14, 31 void __attribute__

Re: [PATCH] rs6000: replace '(const_int 0)' to 'unspec:BLK [(const_int 0)]' for stack_tie

Hi, Segher Boessenkool writes: > Hi! > > As I said in a reply to the original patch: not okay. Sorry. Thanks a lot for your comments! I'm also thinking about other solutions: 1. "set (mem/c:BLK (reg/f:DI 1 1) (const_int 0 [0])" This is the existing pattern. It may be read as an action

Re: [PATCH] rs6000: replace '(const_int 0)' to 'unspec:BLK [(const_int 0)]' for stack_tie

Hi Segher, David, David Edelsohn writes: > On Tue, Jun 13, 2023 at 2:16 PM Segher Boessenkool > wrote: >> >> Hi! >> >> On Tue, Jun 13, 2023 at 10:15:49AM +0800, Jiufu Guo wrote: >> > David Edelsohn writes: >> > > >> > > This definitely seems to be a better solution. >> > > >> > > The

Re: [RFC] Add stdckdint.h header for C23

On 6/12/23 23:28, Jakub Jelinek via Libc-alpha wrote: On Mon, Jun 12, 2023 at 09:51:02PM +, Joseph Myers wrote: On Sat, 10 Jun 2023, Jakub Jelinek via Gcc-patches wrote: I have looked at gnulib stdckdint.h and they are full of workarounds for various compilers, EDG doesn't do this, clang

Re: [PATCH v1] RISC-V: Align the predictor style for define_insn_and_split

LGTM. juzhe.zh...@rivai.ai From: pan2.li Date: 2023-06-14 10:15 To: gcc-patches CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang; kito.cheng Subject: [PATCH v1] RISC-V: Align the predictor style for define_insn_and_split From: Pan Li This patch is considered as the follow

[PATCH v1] RISC-V: Align the predictor style for define_insn_and_split

From: Pan Li This patch is considered as the follow up of the below PATCH. https://gcc.gnu.org/pipermail/gcc-patches/2023-June/621347.html We aligned the predictor style for the define_insn_and_split suggested by Kito. To avoid potential issues before we hit. Signed-off-by: Pan Li

[PATCH, V6] Fix power10 fusion and -fstack-protector, PR target/105325

This patch fixes an issue where if you use the -fstack-protector and -mcpu=power10 options and you have a large stack frame, the GCC compiler will generate a LWA instruction with a large offset. Unlike the previous versions of this patch, I dug into it, and I found it was much more complex that I

Re: [PATCH] rs6000: replace '(const_int 0)' to 'unspec:BLK [(const_int 0)]' for stack_tie

Hi, Xi Ruoyao writes: > On Tue, 2023-06-13 at 20:23 +0800, Jiufu Guo via Gcc-patches wrote: > >> Compare with previous version, this addes ChangeLog and removes >> const_anchor parts. >> https://gcc.gnu.org/pipermail/gcc-patches/2023-June/621356.html. > > [Off topic] > > const_anchor is just

[PATCH] [x86] Use x instead of v for alternative 2 (v, BH) in mov_internal.

Since there's no evex version for vpcmpeq ymm, ymm, ymm. Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}. Ready to push to trunk and backport to GCC13. gcc/ChangeLog: PR target/110227 * config/i386/sse.md (mov_internal>): Use x instead of v for alternative 2

Re: [PATCH 1/4] rs6000: build constant via li;rotldi

Hi, David Edelsohn writes: > On Mon, Jun 12, 2023 at 11:30 PM Jiufu Guo wrote: >> >> >> Hi David, >> >> David Edelsohn writes: >> > On Wed, Jun 7, 2023 at 9:55 PM Jiufu Guo wrote: >> > >> > Hi, >> > >> > This patch checks if a constant is possible to be rotated to/from a >> > positive

Re: [PATCH v1] RISC-V: Bugfix for vec_init repeating auto vectorization in RV32

>> unsigned int elen = TARGET_VECTOR_ELEN_64 ? 64 : 32; Add comment here to demonstrate why you pick up elen to set the LIMIT. I understand: 1. -march=zve32* ===> ELEN = 32 -march=zve64* ===> ELEN = 64 2. both vmv.v.x/vmv.s.x is restrict to the ELEN For example, When ELEN=32

[PATCH v1] RISC-V: Bugfix for vec_init repeating auto vectorization in RV32

From: Pan Li This patch would like to fix one bug exported by RV32 test case multiple_rgroup_run-2.c. The mask should be restricted by elen in vector, and the condition between the vmv.s.x and the vmv.v.x should take inner_bits_size rather than constants. Passed both the rv32 and rv64 riscv/rvv

[PATCH] LoongArch: Set default alignment for functions and labels with -mtune

The LA464 micro-architecture is sensitive to alignment of code. The Loongson team has benchmarked various combinations of function, the results [1] show that 16-byte label alignment together with 32-byte function alignment gives best results in terms of SPEC score. Add a mtune-based table-driven

Re: [PATCH v3] i386: Allow -mlarge-data-threshold with -mcmodel=large

On Mon, Jun 12, 2023 at 11:16 PM Jan Beulich wrote: > On 13.06.2023 05:28, Fangrui Song wrote: > > --- /dev/null > > +++ b/gcc/testsuite/gcc.target/i386/large-data.c > > @@ -0,0 +1,13 @@ > > +/* { dg-do compile } */ > > +/* { dg-require-effective-target lp64 } */ > > +/* { dg-options "-O2

[pushed] c/c++: use positive tone in missing header notes [PR84890]

Quoting "How a computer should talk to people" (as quoted in "Concepts Error Messages for Humans"): "Various negative tones or actions are unfriendly: being manipulative, not giving a second chance, talking down, using fashionable slang, blaming. We must not seem to blame the person. We should

Fix templated conversion operator demangling

I came across this when working on the conversion operator deduction fix. We'd successfully demangle an instantiation of 'template operator X & ()', but fail for 'template operator X ()'. The demangle printer was trying to specially handle the instantiation in the latter case -- seeing the

Re: [PATCH] Fortran: fix passing of zero-sized array arguments to procedures [PR86277]

Hi Steve, On 6/13/23 19:45, Steve Kargl via Gcc-patches wrote: On Mon, Jun 12, 2023 at 11:12:45PM +0200, Harald Anlauf via Fortran wrote: Dear all, the attached - actually rather small - patch is the result of a rather intensive session with Mikael in an attempt to fix the situation that we

Re: [PATCH] Fix note_defect3 function

Hi Jeff, Thank you for your response. Regarding the divtab.cc file, I actually came across it by accident while working on another task. I didn't have a specific reason for investigating the file, but I noticed the issue and thought it was worth bringing to your attention. Thank you for taking

Re: [PATCH] rs6000: replace '(const_int 0)' to 'unspec:BLK [(const_int 0)]' for stack_tie

On Tue, Jun 13, 2023 at 2:16 PM Segher Boessenkool wrote: > > Hi! > > On Tue, Jun 13, 2023 at 10:15:49AM +0800, Jiufu Guo wrote: > > David Edelsohn writes: > > > > > > This definitely seems to be a better solution. > > > > > > The TARGET_CONST_ANCHOR change should not be part of this patch.

Re: [PATCH] RISC-V: Save and restore FCSR in interrupt functions to avoid program errors.

On Tue, 13 Jun 2023 10:41:00 PDT (-0700), gcc-patches@gcc.gnu.org wrote: On 6/13/23 00:41, Jin Ma wrote: gcc/ChangeLog: * config/riscv/riscv.cc (riscv_compute_frame_info): Allocate frame for FCSR. (riscv_for_each_saved_reg): Save and restore FCSR in interrupt functions.

[wwwdocs] gcc-14/changes.html + projects/gomp/: GCC 14 OpenMP update

First update for OpenMP changes that made it into GCC 14. Wording, technical and other comments are welcome as always. I intent to commit the attached patch tomorrow. Tobias PS: There were a bunch of other useful changes, but those "only" improved and fixed features already supported or added

[patch] OpenMP: Set default-device-var with OMP_TARGET_OFFLOAD=mandatory

I intent to commit this tomorrow, unless there are comments. It does as it says (see commit log): It initializes default-device-var to the value using the algorithm described in OpenMP 5.2, which depends on whether OMP_TARGET_OFFLOAD=mandatory was set. NOTE: With -foffload=disable there is no

Re: [PATCH] rs6000: replace '(const_int 0)' to 'unspec:BLK [(const_int 0)]' for stack_tie

Hi! As I said in a reply to the original patch: not okay. Sorry. But some comments on this patch: On Tue, Jun 13, 2023 at 08:23:35PM +0800, Jiufu Guo wrote: > + && XINT (SET_SRC (set), 1) == UNSPEC_TIE > + && XVECEXP (SET_SRC (set), 0, 0) == const0_rtx); This makes it required

Re: [PATCH] rs6000: replace '(const_int 0)' to 'unspec:BLK [(const_int 0)]' for stack_tie

Hi! On Tue, Jun 13, 2023 at 10:15:49AM +0800, Jiufu Guo wrote: > David Edelsohn writes: > > > > This definitely seems to be a better solution. > > > > The TARGET_CONST_ANCHOR change should not be part of this patch. Also > > there is no ChangeLog for the patch. > > Thanks a lot for your quick

[commited] Remove a couple mudflap remnants

I happened to be digging into the specs to understand a build failure and spotted mflib and mfwrap. Those were used by the mudflap system which we ripped out years ago and we just missed these. I verified x86 still bootstraps after removing these bits. Pushed to the trunk as obvious, Jeff

[r14-1712 Regression] FAIL: gcc.target/i386/sse2-packuswb-1.c execution test on Linux/x86_64

On Linux/x86_64, 921b841350c4fc298d09f6c5674663e0f4208610 is the first bad commit commit 921b841350c4fc298d09f6c5674663e0f4208610 Author: Kyrylo Tkachov Date: Mon Jun 12 11:42:29 2023 +0100 simplify-rtx: Implement constant folding of SS_TRUNCATE, US_TRUNCATE caused FAIL:

Re: [PATCH] Fortran: fix passing of zero-sized array arguments to procedures [PR86277]

On Mon, Jun 12, 2023 at 11:12:45PM +0200, Harald Anlauf via Fortran wrote: > Dear all, > > the attached - actually rather small - patch is the result of a > rather intensive session with Mikael in an attempt to fix the > situation that we did not create proper temporaries when passing >

Re: [PATCH] RISC-V: Save and restore FCSR in interrupt functions to avoid program errors.

On 6/13/23 00:41, Jin Ma wrote: gcc/ChangeLog: * config/riscv/riscv.cc (riscv_compute_frame_info): Allocate frame for FCSR. (riscv_for_each_saved_reg): Save and restore FCSR in interrupt functions. * config/riscv/riscv.md (riscv_frcsr): New patterns.

[committed] Remove sh5media divtab code

Spurred by Akari Takahashi's patch to config/sh/divtab.cc, this removes divtab.cc completely. divtab.cc was used to calculate a division table for the sh5 media processor. GCC dropped support for that (unmanufactured) chip back in 2016 and this file simply got missed AFAICT. Pushed to

Re: [PATCH] Add __builtin_iseqsig()

ping > Hi, > > (It took me a while to get back to this.) > > This is a new and improved version of the patch at > https://gcc.gnu.org/pipermail/gcc-patches/2022-October/602932.html > It addresses the comment from Joseph that FE_INVALID should really be tested > in the case of both quiet and

[committed] i386: Fix up whitespace in assembly

Hi! I've noticed that standard_sse_constant_opcode emits some spurious whitespace around tab, that isn't something which is done for any other instruction and looks wrong. Bootstrapped/regtested on x86_64-linux and i686-linux, committed to trunk as obvious. 2023-06-13 Jakub Jelinek

[PATCH] libcpp: Diagnose #include after failed __has_include [PR80753]

Hi! As can be seen in the testcase, we don't diagnose #include/#include_next of a non-existent header if __has_include/__has_include_next is done for that header first. The problem is that we normally error the first time some header is not found, but in the _cpp_FFK_HAS_INCLUDE case obviously

Re: [PATCH] vect: Vectorize via libfuncs

On 6/13/23 09:55, Andrew Stubbs wrote: Subject: [PATCH] vect: Vectorize via libfuncs From: Andrew Stubbs Date: 6/13/23, 09:55 To: "gcc-patches@gcc.gnu.org" This patch allows vectorization when operators are available as libfuncs, rather that only as insns. This will be useful for

Re: [PATCH] RISC-V: Basic VLS code gen for RISC-V

On 6/12/23 17:39, juzhe.zhong wrote: I take this work which is very important for VLA SLP too.  I will support VLS after I finish VLA SLP. OK. I think I'll mark Kito's patch as dropped and we'll wait for your implementation in this space. jeff

[x86 PATCH] Convert ptestz of pandn into ptestc.

This patch is the next instalment in a set of backend patches around improvements to ptest/vptest. A previous patch optimized the sequence t=pand(x,y); ptestz(t,t) into the equivalent ptestz(x,y), using the property that ZF is set to (X) == 0. This patch performs a similar transformation,

[PATCH] vect: Vectorize via libfuncs

This patch allows vectorization when operators are available as libfuncs, rather that only as insns. This will be useful for amdgcn where we plan to vectorize loops that contain integer division or modulus, but don't want to generate inline instructions for the division algorithm every time.

[PATCH, OpenACC 2.7] Implement self clause for compute constructs

Hi Thomas, This patch implements the compiler side for the 'self' clause for compute constructs: parallel, kernels, and serial. As you know, the actual "local device" device type for libgomp is not yet implemented, so the libgomp side is basically just a simple duplicate of what host-fallback

Re: [RFC] Add stdckdint.h header for C23

On Tue, 13 Jun 2023, Jakub Jelinek via Gcc-patches wrote: > Yeah, having say __builtin_{clz,ctz,ffs,popcount,parity} variants which would > be typegeneric and would allow say any normal integral or _BitInt type > (or just unsigned versions thereof?) would be useful. Even without _BitInt > we

Re: [ping] driver: Forward '-lgfortran', '-lm' to offloading compilation

On Tue, 13 Jun 2023, Thomas Schwinge wrote: > Hi! > > On 2023-06-05T14:25:18+0200, I wrote: > > OK to push the attached > > "driver: Forward '-lgfortran', '-lm' to offloading compilation"? > > (We didn't have a PR open for that, or did we?) > > Ping. OK. -- Joseph S. Myers

RE: [PATCH v2] machine descriptor: New compact syntax for insn and insn_split in Machine Descriptions.

Hi All, Updated patch with feedback addressed. Bootstrapped Regtested on aarch64-none-linux-gnu and no issues. Any feedback? Thanks, Tamar gcc/ChangeLog: * gensupport.cc (class conlist, add_constraints, add_attributes, skip_spaces, expect_char, preprocess_compact_syntax,

Re: [RFC] Add stdckdint.h header for C23

On Tue, Jun 13, 2023 at 03:10:48PM +, Joseph Myers wrote: > > So why does C2X say > > Recommended practice > > It is recommended to produce a diagnostic message if type2 or type3 are > > not suitable integer types, or if *result is not a modifiable lvalue of > > a suitable integer type. > > ?

Re: [PATCH] ipa: Self-DCE of uses of removed call LHSs (PR 108007)

Ping. Thanks, Martin On Fri, May 12 2023, Martin Jambor wrote: > Hi, > > PR 108007 is another manifestation where we rely on DCE to clean-up > after IPA-SRA and if the user explicitely switches DCE off, IPA-SRA > can leave behind statements which are fed uninitialized values and > trap, even

Re: [RFC] Add stdckdint.h header for C23

On Tue, 13 Jun 2023, Jakub Jelinek via Gcc-patches wrote: > There is always the possibility to have the header co-owned by both > the compiler and C library, limits.h style. > Just > #if __has_include_next() > # include_next > #endif > perhaps guarded with some macro at the end of the GCC

RE: [PATCH] RISC-V: Remove duplicate `#include "riscv-vector-switch.def"`

Committed, thanks Juzhe. Pan -Original Message- From: Gcc-patches On Behalf Of juzhe.zh...@rivai.ai Sent: Tuesday, June 13, 2023 6:56 PM To: 丁乐华 ; gcc-patches Subject: Re: [PATCH] RISC-V: Remove duplicate `#include "riscv-vector-switch.def"` Send V2 patch with changelog. Thanks.

Re: [PATCH] modula2: Fix bootstrap

On Wed, Jun 07, 2023 at 09:42:22AM +0100, Andre Vieira (lists) wrote: > I do need those includes and sorry I broke your bootstrap it didn't show up > on my aarch64-unknown-linux-gnu bootstrap, I'm guessing the rules there were > just run in a different order. Glad you were able to fix it :)

RE: [PATCH] RISC-V: Add comments of some functions

Committed, thanks Jeff. Pan -Original Message- From: Gcc-patches On Behalf Of Jeff Law via Gcc-patches Sent: Tuesday, June 13, 2023 10:06 PM To: juzhe.zh...@rivai.ai; gcc-patches@gcc.gnu.org Cc: kito.ch...@gmail.com; kito.ch...@sifive.com; pal...@dabbelt.com; pal...@rivosinc.com;

Re: [PATCH] RISC-V: Implement vec_set and vec_extract.

On 6/13/23 00:50, Robin Dapp wrote: I suggest we implement vector calling convention even though it is not ratified yet. We can allow calling convention to be enabled only when --param=riscv-autovec-preference=fixed-vlmax. We have such issue:

Re: [PATCH V2] RISC-V: Support RVV VLA SLP auto-vectorization

On 6/12/23 20:27, juzhe.zh...@rivai.ai wrote: Ok. https://gcc.gnu.org/pipermail/gcc-patches/2023-June/thread.html I have add comments as you suggested. Thanks. With those changes I think the main patch here (RVV VLA SLP

Re: [PATCH] RISC-V: Add comments of some functions

On 6/12/23 20:26, juzhe.zh...@rivai.ai wrote: From: Juzhe-Zhong gcc/ChangeLog: * config/riscv/riscv-v.cc (rvv_builder::single_step_npatterns_p): Add comment. (shuffle_generic_patterns): Ditto. (expand_vec_perm_const_1): Ditto. OK. Thanks! jeff

RE: [PATCH V3] RISC-V: Add more SLP tests

Committed, thanks Jeff. Pan -Original Message- From: Gcc-patches On Behalf Of Jeff Law via Gcc-patches Sent: Tuesday, June 13, 2023 9:26 PM To: juzhe.zh...@rivai.ai; gcc-patches@gcc.gnu.org Cc: kito.ch...@gmail.com; kito.ch...@sifive.com; pal...@dabbelt.com; pal...@rivosinc.com;

RE: [PATCH] RISC-V: Fix bug of VLA SLP auto-vectorization

Committed, thanks Jeff. Pan -Original Message- From: Gcc-patches On Behalf Of Jeff Law via Gcc-patches Sent: Tuesday, June 13, 2023 9:30 PM To: Robin Dapp ; juzhe.zh...@rivai.ai; gcc-patches@gcc.gnu.org Cc: kito.ch...@gmail.com; kito.ch...@sifive.com; pal...@dabbelt.com;

Ping * 2 : Fwd: [V9][PATCH 1/2] Handle component_ref to a structre/union field including flexible array member [PR101832]

Hi, I’d like to ping this patch again for the Middle-end approval (on gcc/tree-object-size.cc change). This is an important patch to Linux Kernel security. The patch has addressed all the comments and suggestions raised during the review process. The C FE, Doc changes has been approved. Most

Re: [PATCH] Fix note_defect3 function

On 6/12/23 21:18, Akari Takahashi via Gcc-patches wrote: Hello, I've noticed an issue with the note_defect3 function and have prepared a patch to fix it. The function is missing a return statement, which is causing undefined behavior. This patch adds the missing return statement, ensuring

Re: [PATCH 1/4] rs6000: build constant via li;rotldi

On Mon, Jun 12, 2023 at 11:30 PM Jiufu Guo wrote: > > > Hi David, > > David Edelsohn writes: > > On Wed, Jun 7, 2023 at 9:55 PM Jiufu Guo wrote: > > > > Hi, > > > > This patch checks if a constant is possible to be rotated to/from a > > positive > > or negative value from "li". If so, we

Re: [PATCH] RISC-V: Fix bug of VLA SLP auto-vectorization

On 6/13/23 06:16, Robin Dapp wrote: Hi Juzhe, LGTM. You could also add the aarch64 test disclaimer here again, but no need for a V2. Agreed. jeff

Re: [PATCH V3] RISC-V: Add more SLP tests

On 6/13/23 05:38, juzhe.zh...@rivai.ai wrote: From: Juzhe-Zhong gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/partial/slp-10.c: New test. * gcc.target/riscv/rvv/autovec/partial/slp-11.c: New test. * gcc.target/riscv/rvv/autovec/partial/slp-13.c: New

[PATCH] Add -Wmissing-variable-declarations [PR65213].

Resolves: PR c/65213 - Extend -Wmissing-declarations to variables [i.e. add -Wmissing-variable-declarations] gcc/c-family/ChangeLog: PR c/65213 * c.opt (-Wmissing-variable-declarations): New option. gcc/c/ChangeLog: PR c/65213 * c-decl.cc (start_decl): Handle

Re: [PATCH] rs6000: replace '(const_int 0)' to 'unspec:BLK [(const_int 0)]' for stack_tie

On Tue, 2023-06-13 at 20:23 +0800, Jiufu Guo via Gcc-patches wrote: > Compare with previous version, this addes ChangeLog and removes > const_anchor parts. > https://gcc.gnu.org/pipermail/gcc-patches/2023-June/621356.html. [Off topic] const_anchor is just broken now. See

[PATCH] rs6000: replace '(const_int 0)' to 'unspec:BLK [(const_int 0)]' for stack_tie

Hi, For stack_tie, currently below insn is generated: (insn 15 14 16 3 (parallel [ (set (mem/c:BLK (reg/f:DI 1 1) [1 A8]) (const_int 0 [0])) ]) "/home/guojiufu/temp/gdb.c":13:3 922 {stack_tie} (nil)) It is "set (mem/c:BLK (reg/f:DI 1 1) (const_int 0

[PATCH] Fix memory leak in loop header copying

Bootstrapped and tested on x86_64-unknown-linux-gnu, pushed. * tree-ssa-loop-ch.cc (ch_base::copy_headers): Free loop BBs. --- gcc/tree-ssa-loop-ch.cc | 1 + 1 file changed, 1 insertion(+) diff --git a/gcc/tree-ssa-loop-ch.cc b/gcc/tree-ssa-loop-ch.cc index 7fdef3bb11a..22252bee135

Re: Re: [PATCH V3] RISC-V: Add more SLP tests

Ok. After floating-point binary. I will do floating-point ternary. I think you do conversion next (widen floating point, float to int, int to float). It seems that we almost done most of the part autovec patterns in RISC-V port. What else we can do? My second middle-end patch (LEN_MASK _*

Re: [PATCH] RISC-V: Fix bug of VLA SLP auto-vectorization

Hi Juzhe, LGTM. You could also add the aarch64 test disclaimer here again, but no need for a V2. Regards Robin

[pushed] c++: mutable temps in rodata

Tested x86_64-pc-linux-gnu, applying to trunk. -- 8< -- If the type of a temporary has mutable members, we can't set TREE_READONLY on the VAR_DECL; this is parallel to the check in cp_apply_type_quals_to_decl. gcc/cp/ChangeLog: * tree.cc (build_target_expr): Check TYPE_HAS_MUTABLE_P.

Re: [PATCH V3] RISC-V: Add more SLP tests

Hi Juzhe, thanks, works for me as is. I just hope somebody is going to take on the task of making different LMUL SLP variants "scannable" at some point because it would definitely increase our test coverage with these tests. (Or split the tests manually and not iterate over LMUL) Regards Robin

[PATCH V3] RISC-V: Add more SLP tests

From: Juzhe-Zhong gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/partial/slp-10.c: New test. * gcc.target/riscv/rvv/autovec/partial/slp-11.c: New test. * gcc.target/riscv/rvv/autovec/partial/slp-13.c: New test. *

RE: [PATCH v5] RISC-V: Add vector psabi checking.

Committed v6 with riscv.exp and rvv.exp passed, thanks Kito. Pan -Original Message- From: Li, Pan2 Sent: Monday, June 12, 2023 8:49 PM To: Kito Cheng ; Wang, Yanzhang Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai Subject: RE: [PATCH v5] RISC-V: Add vector psabi checking. Sure

Re: [PATCH] middle-end, i386: Pattern recognize add/subtract with carry [PR79173]

On Tue, Jun 13, 2023 at 08:40:36AM +, Richard Biener wrote: > I suspect re-association can wreck things even more here. I have > to say the matching code is very hard to follow, not sure if > splitting out a function matching > >_22 = .{ADD,SUB}_OVERFLOW (_6, _5); >_23 =

Re: [ping] Add 'libgomp.{,oacc-}fortran/fortran-torture_execute_math.f90'

On 13.06.23 12:42, Thomas Schwinge wrote: On 2023-06-05T14:18:48+0200, I wrote: OK to push the attached "Add 'libgomp.{,oacc-}fortran/fortran-torture_execute_math.f90'"? Subject: [PATCH] Add 'libgomp.{,oacc-}fortran/fortran-torture_execute_math.f90' gcc/testsuite/ *

Re: [PATCH] New finish_compare_by_pieces target hook (for x86).

On Mon, Jun 12, 2023 at 4:04 PM Roger Sayle wrote: > > > The following simple test case, from PR 104610, shows that memcmp () == 0 > can result in some bizarre code sequences on x86. > > int foo(char *a) > { > static const char t[] = "0123456789012345678901234567890"; > return

Re: [PATCH V2] RISC-V: Remove duplicate `#include "riscv-vector-switch.def"`

LGTM. Thanks. Will merge it soon. Thank you for such a prompt reply.

Re: [PATCH V2] RISC-V: Remove duplicate `#include "riscv-vector-switch.def"`

LGTM. Thanks. Will merge it soon. juzhe.zh...@rivai.ai From: Lehua Ding Date: 2023-06-13 18:59 To: gcc-patches; juzhe.zhong Subject: [PATCH V2] RISC-V: Remove duplicate `#include "riscv-vector-switch.def"` Hi, This patch remove the duplicate `#include "riscv-vector-switch.def"` statement

[PATCH V2] RISC-V: Remove duplicate `#include "riscv-vector-switch.def"`

Hi, This patch remove the duplicate `#include "riscv-vector-switch.def"` statement and add #undef for ENTRY and TUPLE_ENTRY macros later. Best, Lehua gcc/ChangeLog: * config/riscv/riscv-v.cc (struct mode_vtype_group): Remove duplicate #include. (ENTRY): Undef.

Re: [PATCH] RISC-V: Remove duplicate `#include "riscv-vector-switch.def"`

Send V2 patch with changelog. Thanks. juzhe.zh...@rivai.ai From: Lehua Ding Date: 2023-06-13 18:53 To: gcc-patches; juzhe.zhong Subject: [PATCH] RISC-V: Remove duplicate `#include "riscv-vector-switch.def"` Hi, This patch remove the duplicate `#include "riscv-vector-switch.def"` statement

[PATCH] RISC-V: Remove duplicate `#include "riscv-vector-switch.def"`

Hi, This patch remove the duplicate `#include "riscv-vector-switch.def"` statement and add #undef for ENTRY and TUPLE_ENTRY macros later. Best, Lehua --- gcc/config/riscv/riscv-v.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/gcc/config/riscv/riscv-v.cc

[ping] driver: Forward '-lgfortran', '-lm' to offloading compilation

Hi! On 2023-06-05T14:25:18+0200, I wrote: > OK to push the attached > "driver: Forward '-lgfortran', '-lm' to offloading compilation"? > (We didn't have a PR open for that, or did we?) Ping. Grüße Thomas - Siemens Electronic Design Automation GmbH; Anschrift: Arnulfstraße

[ping] Add 'libgomp.{, oacc-}fortran/fortran-torture_execute_math.f90'

Hi! On 2023-06-05T14:18:48+0200, I wrote: > OK to push the attached > "Add 'libgomp.{,oacc-}fortran/fortran-torture_execute_math.f90'"? Ping. Grüße Thomas - Siemens Electronic Design Automation GmbH; Anschrift: Arnulfstraße 201, 80634 München; Gesellschaft mit beschränkter

[PATCH V2] RISC-V: Add more SLP tests

From: Juzhe-Zhong gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/partial/slp-10.c: New test. * gcc.target/riscv/rvv/autovec/partial/slp-11.c: New test. * gcc.target/riscv/rvv/autovec/partial/slp_run-10.c: New test. *

Re: Re: [PATCH] RISC-V: Add more SLP tests

>> as the tests are mostly directly from aarch64's testsuite I would >> advise comments on where they were taken from as well as a TODO that >> they should become common tests for a specific target selector >> (vect_scalable_supported or something). Ok. >> (How about some assembly checks for

[PATCH] c++: Fix ICE with parameter pack of decltype(auto) [PR103497]

(Another) ping. https://gcc.gnu.org/pipermail/gcc-patches/2023-April/616465.html On Sat, Apr 22, 2023 at 04:25:13PM +1000, Nathaniel Shead wrote: > Bootstrapped and tested on x86_64-pc-linux-gnu. > > -- 8< -- > > This patch raises an error early when the decltype(auto) specifier is > used as a

[PATCH] c++: Report invalid id-expression in decltype [PR100482]

(Another) ping. On Sun, Apr 30, 2023 at 12:00:05PM +1000, Nathaniel Shead wrote: > This patch ensures that any errors raised by finish_id_expression when > parsing a decltype expression are properly reported, rather than > potentially going ignored and causing invalid code to be accepted. > > We

[PATCH v2 0/3] c++: Track lifetimes in constant evaluation [PR70331,...]

(Another) ping. I also have some more changes on top of this patch set as well if this looks good as it is. https://gcc.gnu.org/pipermail/gcc-patches/2023-March/614811.html Thanks! On Wed, Mar 29, 2023 at 01:32:55PM +1100, Nathaniel Shead wrote: > This is an update of the patch series at >

Re: [PATCH] RISC-V: Add more SLP tests

Hi Juzhe, as the tests are mostly directly from aarch64's testsuite I would advise comments on where they were taken from as well as a TODO that they should become common tests for a specific target selector (vect_scalable_supported or something). How about some assembly checks for the non-run

[committed] libgomp/testsuite: Add requires-unified-addr-1.{c,f90} [PR109837]

Add a testcase for "omp requires unified_address" as we hadn't one. The feature itself worked since the beginning (hardware + implementation wise); that the devices report 'omp requires unified_address' as supported is newer: for nvptx since r13-3460-g131d18e928a3ea and for GCN since

[PATCH] RISC-V: Fix bug of VLA SLP auto-vectorization

From: Juzhe-Zhong Sorry for producing bugs in the previous VLA SLP patch. Consider this following permutation: _85 = VEC_PERM_EXPR <{ 99, 17, ... }, { 11, 80, ... }, { 0, POLY_INT_CST [4, 4], 1, POLY_INT_CST [5, 4], 2, POLY_INT_CST [6, 4], ... }>; The correct result should be: _85 = { 99, 11,

Re: [PATCH 4/4] rs6000: build constant via li/lis;rldic

Hi David, Thanks for your valuable comments! David Edelsohn writes: > > On Wed, Jun 7, 2023 at 9:56 PM Jiufu Guo wrote: > > Hi, > > This patch checks if a constant is possible to be built by "li;rldic". > We only need to take care of "negative li", other forms do not need to check. >

[PATCH][committed] arm: Extend -mtp= arguments

Hi all, After discussing the -mtp= option with Arm's LLVM developers we'd like to extend the functionality of the option somewhat. There are actually 3 system registers that can be accessed for the thread pointer in aarch32: tpidrurw, tpidruro, tpidrprw. They are all read through the CP15

[PATCH] RISC-V: Add more SLP tests

From: Juzhe-Zhong gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/partial/slp-10.c: New test. * gcc.target/riscv/rvv/autovec/partial/slp-11.c: New test. * gcc.target/riscv/rvv/autovec/partial/slp_run-10.c: New test. *

[PATCH][committed] aarch64: Extend -mtp= arguments

Hi all, After discussing the -mtp= option with Arm's LLVM developers we'd like to extend the functionality of the option somewhat. First of all, there is another TPIDR register that can be used to read the thread pointer: TPIDRRO_EL0 (which can also be accessed by AArch32 under another name) so

[PATCHv3, rs6000] Add two peephole2 patterns for mr. insn

Hi, This patch adds two peephole2 patterns which help convert certain insn sequences to "mr." instruction. These insn sequences can't be combined in combine pass. Compared to last version, it changes the new mode iterator name from "Q" to "WORD". Bootstrapped and tested on powerpc64-linux

Re: [PATCH] c, c++: Accept __builtin_classify_type (typename)

On 6/12/23 15:57, Jakub Jelinek wrote: Hi! As mentioned in my stdckdint.h mail, __builtin_classify_type has a problem that argument promotion (the argument is passed to ... prototyped builtin function) means that certain type classes will simply never appear. I think it is too late to change

[PATCH] middle-end/110232 - fix native interpret of vector

The following fixes native interpretation of a buffer as boolean vector with bit-precision elements such as AVX512 vectors. The check whether the buffer covers the whole vector was broken for bit-precision elements and the following instead implements it based on the vector type size.

[PATCH] Fix disambiguation against .MASK_LOAD

Alias analysis was treating .MASK_LOAD as storing a full vector which means we disambiguate against decls of smaller than vector size. This complements the previous patch handling .MASK_STORE and fixes runtime execution FAILs of gfortran.dg/matmul_3.f90 and gfortran.dg/inline_sum_2.f90 when using

Re: [PATCH] middle-end, i386: Pattern recognize add/subtract with carry [PR79173]

On Tue, 6 Jun 2023, Jakub Jelinek wrote: > Hi! > > The following patch introduces {add,sub}c5_optab and pattern recognizes > various forms of add with carry and subtract with carry/borrow, see > pr79173-{1,2,3,4,5,6}.c tests on what is matched. > Primarily forms with 2 __builtin_add_overflow or

Re: [PATCH] Add MinGW option -mcrtdll= for choosing C RunTime DLL library

在 2023/6/13 14:29, Pali Rohár 写道: Of course, just I'm not sure where to put the new paragraph. At the beginning? Or after the text? What do you think? Maybe just in front of 'This option is available for MinGW targets.' Also you may reword it as you like. -- Best regards, LIU Hao

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