Re: [PATCH] ubsan: Add workaround for missing bitint libubsan support for shifts [PR112941]

On Thu, 21 Dec 2023, Jakub Jelinek wrote: > Hi! > > libubsan still doesn't support bitints, so ubsan contains a workaround and > emits value 0 and TK_Unknown kind for those. If shift second operand has > the large/huge _BitInt type, this results in internal errors in libubsan > though, so the

Re: [PATCH] lower-bitint: Avoid nested casts in muldiv/float operands [PR112941]

On Thu, 21 Dec 2023, Jakub Jelinek wrote: > Hi! > > Multiplication/division/modulo/float operands are handled by libgcc calls > and so need to be passed as array of limbs with precision argument, > using handle_operand_addr. That code can't deal with more than one cast, > so the following patch

Re: omp: Fix simdclone arguments with veclen lower than simdlen [PR113040]

On Wed, 20 Dec 2023, Andre Vieira (lists) wrote: > This patch fixes an issue introduced by: > commit ea4a3d08f11a59319df7b750a955ac613a3f438a > Author: Andre Vieira > Date: Wed Nov 1 17:02:41 2023 + > > omp: Reorder call for TARGET_SIMD_CLONE_ADJUST > > The problem was that after

[PATCH] ubsan: Add workaround for missing bitint libubsan support for shifts [PR112941]

Hi! libubsan still doesn't support bitints, so ubsan contains a workaround and emits value 0 and TK_Unknown kind for those. If shift second operand has the large/huge _BitInt type, this results in internal errors in libubsan though, so the following patch provides a temporary workaround for that

[PATCH] lower-bitint: Avoid nested casts in muldiv/float operands [PR112941]

Hi! Multiplication/division/modulo/float operands are handled by libgcc calls and so need to be passed as array of limbs with precision argument, using handle_operand_addr. That code can't deal with more than one cast, so the following patch avoids merging those cases. .MUL_OVERFLOW calls use

Re: [PATCH 1/3][RFC] RISC-V: Add non-vector types to pipelines

On 12/20/23 15:11, Edwin Lu wrote:   (define_insn_reservation "generic_xfer" 3     (and (eq_attr "tune" "generic") -   (eq_attr "type" "mfc,mtc,fcvt,fmove,fcmp")) +   (eq_attr "type" "mfc,mtc,fcvt,fmove,fcmp,cbo"))     "alu") cbo is probably closer to a load/store than it is a

Re: [Patchv3, rs6000] Clean up pre-checkings of expand_block_compare

Hi, on 2023/12/21 09:37, HAO CHEN GUI wrote: > Hi, > This patch cleans up pre-checkings of expand_block_compare. It does > 1. Assert only P7 above can enter this function as it's already guard > by the expand. > 2. Remove P7 processor test as only P7 above can enter this function and > P7 LE is

Re: [Patch, rs6000] Call library for block memory compare when optimizing for size

Hi Haochen, on 2023/12/20 16:56, HAO CHEN GUI wrote: > Hi, > This patch call library function for block memory compare when it's > optimized for size. > > Bootstrapped and tested on x86 and powerpc64-linux BE and LE with no > regressions. Is this OK for trunk? > > Thanks > Gui Haochen > >

[PATCH 2/2 FYI] -finline-stringops: drop obsolete comment [PR112778]

On Dec 11, 2023, Richard Biener wrote: > On Sat, Dec 9, 2023 at 8:05 AM Alexandre Oliva wrote: >> PR target/112778 >> * builtins.cc (can_store_by_multiple_pieces): New. >> (try_store_by_multiple_pieces): Call it. >> +/* Check that store_by_pieces allows BITS + LEN (so that we don't >> +

Re: [Patchv3, rs6000] Correct definition of macro of fixed point efficient unaligned

Hi Haochen, on 2023/12/20 16:51, HAO CHEN GUI wrote: > Hi, > The patch corrects the definition of > TARGET_EFFICIENT_OVERLAPPING_UNALIGNED and replace it with the call of > slow_unaligned_access. > > Compared with last version, >

Re: [PATCH] sel-sched: Verify change before replacing dest in EXPR_INSN_RTX [PR112995]

Hi Jeff, on 2023/12/21 04:30, Jeff Law wrote: > > > On 12/15/23 01:52, Kewen.Lin wrote: >> Hi, >> >> PR112995 exposed one issue in current try_replace_dest_reg >> that the result rtx insn after replace_dest_with_reg_in_expr >> is probably unable to match any constraints.  Although there >> are

Re: PING^1 [PATCH] sched: Remove debug counter sched_block

Hi Jeff, on 2023/12/21 04:43, Jeff Law wrote: > > > On 12/11/23 23:17, Kewen.Lin wrote: >> Hi, >> >> Gentle ping this: >> >> https://gcc.gnu.org/pipermail/gcc-patches/2023-November/636597.html >> >> BR, >> Kewen >> >> on 2023/11/15 17:01, Kewen.Lin wrote: >>> Hi, >>> >>> on 2023/11/10 01:40,

Re: [PATCH v3 4/6] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.

On 12/20/23 15:48, 钟居哲 wrote: >> So rather than looking at the mode, would it make more sense to have an attribute (or re-use an existing attribute) to identify which opcodes are going to need prefixing?  We've got access to the INSN via current_output_insn.  So we can lookup attributes

Re: [External] Re: [PATCH] RISC-V: Fix RISCV_FUSE_ZEXTWS fusion condition

On 12/20/23 20:30, Wang Pengcheng wrote: Yeah, I just found it when I tried to understand the original fusion implementation commit. :-) Ah. If you have any questions, don't hesitate to reach out. While I didn't do the original implementation (that was Philipp T. and his team), the

Re: [PATCH v3 0/6] RISC-V: Support XTheadVector extension

On 12/20/23 20:30, juzhe.zh...@rivai.ai wrote: OK.  Sounds reasonable. But from my side, I used to commit patches after full coverage testing. Understood. And it's appreciated -- the code you're doing hits a wide variety of configurations, so the wider testing is probably applicable.

Re: [PATCH v5 2/3] RISC-V: Add crypto machine descriptions

+ (and:VI + (match_operand:VI 3 "register_operand" "vr, vr, vr, vr") + (not:VI (match_operand:VI 4 "register_operand" "vr, vr, vr, vr"))) This order should be swapped like ARM SVE: (define_expand "@cond_bic" [(set (match_operand:SVE_FULL_I 0 "register_operand")

Re: Re: [PATCH v3 0/6] RISC-V: Support XTheadVector extension

OK. Sounds reasonable. But from my side, I used to commit patches after full coverage testing. juzhe.zh...@rivai.ai From: Jeff Law Date: 2023-12-21 11:28 To: 钟居哲; cooper.joshua; gcc-patches CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; Christoph Müllner; jinma; Cooper Qu Subject:

Re: [External] Re: [PATCH] RISC-V: Fix RISCV_FUSE_ZEXTWS fusion condition

On 2023/12/21 1:08, Jeff Law wrote: > > > On 12/20/23 01:39, Wang Pengcheng wrote: >> From: wangpc >> >> The condition is RISCV_FUSE_ZEXTH, which is a mistake. >> >> gcc/ChangeLog: >> >> * config/riscv/riscv.cc (riscv_macro_fusion_pair_p): Fix condition. > Thanks! As soon as this patch finishes

Re: [PATCH v3 0/6] RISC-V: Support XTheadVector extension

On 12/20/23 16:08, 钟居哲 wrote: Btw, rv32/rv64gc or rv32/rv64 gcv testing is not enough. We need full coverage testing, since we always commit patch after no regression testing on full coverage testing: No. It is unreasonable to require this large of test matrix for the vast majority if

[PATCH v5 2/3] RISC-V: Add crypto machine descriptions

Patch v5: Add vec_duplicate operator. Make report riscv.exp with "riscv-sim/-march=rv64gc/-mabi=lp64d/-mcmodel=medlow" is passed. Patch v4: Add process of SEW=64 in RV32 system. Patch v3: Moidfy constrains for crypto vector. Patch v2: Add crypto vector ins into RATIO attr and use vr as

[PATCH v1] RISC-V: XFail the signbit-5 run test for RVV

From: Pan Li This patch would like to XFail the signbit-5 run test case for the RVV. Given the case has one limitation like "This test does not work when the truth type does not match vector type." in the beginning of the test file. Aka, the RVV vector truth type is not integer type. The

[pushed] c++: computed goto warning [PR37722]

This is one of those patches where I first did the basic thing and then thought "well, or I could do a bit better..." several times... Tested x86_64-pc-linux-gnu, applying to trunk. -- 8< -- PR37722 complains that a computed goto doesn't destroy objects that go out of scope. In the PR we

Re: [PATCH] RISC-V: Fix calculation of max live vregs

Hi Jeff, Thanks for reminding this. Regression test info will be added to commit log in following patches. Demin On 2023/12/20 23:28, Jeff Law wrote: > > > On 12/20/23 04:17, juzhe.zh...@rivai.ai wrote: >> I see. LGTM. Thanks for explanation. >> >> I will ask Li Pan commit it for you. > The

[Patchv3, rs6000] Clean up pre-checkings of expand_block_compare

Hi, This patch cleans up pre-checkings of expand_block_compare. It does 1. Assert only P7 above can enter this function as it's already guard by the expand. 2. Remove P7 processor test as only P7 above can enter this function and P7 LE is excluded by targetm.slow_unaligned_access. On P7 BE, the

Re: [PATCH] c-family: Fix ICE with large column number after restoring a PCH [PR105608]

Hello- May I please ping this PCH patch? Thanks! https://gcc.gnu.org/pipermail/gcc-patches/2023-December/639467.html -Lewis On Tue, Dec 5, 2023 at 8:52 PM Lewis Hyatt wrote: > > Hello- > > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105608 > > There are two related issues here really, a

Re: [PATCH] untyped calls: enable target switching [PR112334]

On Dec 20, 2023, Jeff Law wrote: > Sorry it was meant to be an ACK for the trunk for both patches. Aah, I see. So this is what I installed last night, upon seeing your message. untyped calls: use wrapper class type for implicit plus_one Instead of get and set macros to apply a delta, use a

Re: [PATCH] c++: fix -Wparentheses with boolean-like class types

On Wed, 20 Dec 2023, Jason Merrill wrote: > On 12/20/23 17:54, Patrick Palka wrote: > > On Wed, 20 Dec 2023, Jason Merrill wrote: > > > > > On 12/20/23 17:07, Patrick Palka wrote: > > > > Bootstrap and regtesting in progress on x86_64-pc-linux-gnu, does this > > > > look OK for trunk if

Re: [PATCH RFA] opts: -Werror=foo always implies -Wfoo [PR106213]

On Tue, 19 Dec 2023, Jason Merrill wrote: > Tested x86_64-pc-linux-gnu, OK for trunk? > > -- 8< -- > > -Werror=foo implying -Wfoo wasn't working for -Wdeprecated-copy-dtor, > because it is specified as the value 2 of warn_deprecated_copy, which shows > up as CLVC_EQUAL, which is not one of the

Re: [PATCH] c++: fix -Wparentheses with boolean-like class types

On 12/20/23 17:54, Patrick Palka wrote: On Wed, 20 Dec 2023, Jason Merrill wrote: On 12/20/23 17:07, Patrick Palka wrote: Bootstrap and regtesting in progress on x86_64-pc-linux-gnu, does this look OK for trunk if successful? -- >8 -- Since r14-4977-g0f2e2080685e75 the -Wparentheses warning

Re: [PATCH] c++: Enable -Walloc-size and -Wcalloc-transposed-args warnings for C++

On 12/20/23 18:29, Jakub Jelinek wrote: On Wed, Dec 20, 2023 at 05:45:05PM -0500, Jason Merrill wrote: On 12/20/23 14:20, Jakub Jelinek wrote: + if ((warn_sizeof_pointer_memaccess || alloc_size_attr) && (complain & tf_warning) && !vec_safe_is_empty (*args)

Re: [PATCH] c++: Enable -Walloc-size and -Wcalloc-transposed-args warnings for C++

On Wed, Dec 20, 2023 at 05:45:05PM -0500, Jason Merrill wrote: > On 12/20/23 14:20, Jakub Jelinek wrote: > > + if ((warn_sizeof_pointer_memaccess || alloc_size_attr) > > && (complain & tf_warning) > > && !vec_safe_is_empty (*args) > > && !processing_template_decl)

Re: Ping Re: [PATCH] contrib: add git gcc-style alias

On 12/20/23 02:39, Richard Biener wrote: On Tue, Dec 19, 2023 at 6:41 PM Jason Merrill wrote: On 12/11/23 22:00, Jason Merrill wrote: OK for trunk? Ping. CCing Alex because this could plausibly be considered build machinery, and he's had useful feedback on my sh code before. OK in case

Re: [PATCH v3 0/6] RISC-V: Support XTheadVector extension

Btw, rv32/rv64gc or rv32/rv64 gcv testing is not enough. We need full coverage testing, since we always commit patch after no regression testing on full coverage testing: with these following configurations: -march=rv[32/64]gc_zve32f_zvfh_zfh -march=rv[32/64]gc_zve64d_zvfh_zfh

Re: [PATCH v3 0/6] RISC-V: Support XTheadVector extension

Hi, Joshua. Thanks for working hard on clean up codes and support tons of work on theadvector. After fully review this patch, I understand you have 3 kinds of theadvector intrinsics from the codebase of current RVV1.0 GCC. 1). instructions that can leverage all current codes of RVV1.0

Re: Ping Re: [PATCH] contrib: add git gcc-style alias

On Dec 19, 2023, Jason Merrill wrote: > On 12/11/23 22:00, Jason Merrill wrote: >> OK for trunk? > Ping. CCing Alex because this could plausibly be considered build > machinery, and he's had useful feedback on my sh code before. LGTM, thanks! -- Alexandre Oliva, happy hacker

Re: [PATCH 2/3][RFC] RISC-V: Add vector related reservations

On 12/20/2023 10:57 AM, Jeff Law wrote: On 12/15/23 11:53, Edwin Lu wrote: This patch copies the vector reservations from generic-ooo.md and inserts them into generic.md and sifive.md. The vector pipelines are necessary to avoid an ICE from the assert gcc/ChangeLog: *

Re: [PATCH] c++: fix -Wparentheses with boolean-like class types

On Wed, 20 Dec 2023, Jason Merrill wrote: > On 12/20/23 17:07, Patrick Palka wrote: > > Bootstrap and regtesting in progress on x86_64-pc-linux-gnu, does this > > look OK for trunk if successful? > > > > -- >8 -- > > > > Since r14-4977-g0f2e2080685e75 the -Wparentheses warning now undesirably >

Re: Re: [PATCH v3 4/6] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.

>> So rather than looking at the mode, would it make more sense to have an >> attribute (or re-use an existing attribute) to identify which opcodes >> are going to need prefixing? We've got access to the INSN via >> current_output_insn. So we can lookup attributes trivially. Yes, I totally

Re: [PATCH] c++: Enable -Walloc-size and -Wcalloc-transposed-args warnings for C++

On 12/20/23 14:20, Jakub Jelinek wrote: Hi! The following patch enables the -Walloc-size and -Wcalloc-transposed-args warnings for C++ as well. Ok for trunk if it passes bootstrap/regtest? 2023-12-20 Jakub Jelinek gcc/c-family/ * c.opt (Walloc-size): Enable also for C++ and

Re: Re: [PATCH] RISC-V: Block VLSmodes according to TARGET_MAX_LMUL and BITS_PER_RISCV_VECTOR

I was thinking the commit log is quite clear but I don't mind telling you more details behind this patch. First, This patch is not an optimization patch, is fatal ICE and run-time bug fix patch as commit log said. Before this patch, we enable more aggressive VLSmodes that size larger than

Re: [PATCH] c++: fix -Wparentheses with boolean-like class types

On 12/20/23 17:07, Patrick Palka wrote: Bootstrap and regtesting in progress on x86_64-pc-linux-gnu, does this look OK for trunk if successful? -- >8 -- Since r14-4977-g0f2e2080685e75 the -Wparentheses warning now undesirably warns on the idiom Wparentheses-34.C:9:14: warning: suggest

[PATCH] aarch64: Prevent moving throwing accesses in ldp/stp pass [PR113093]

As the PR shows, there was nothing to prevent the ldp/stp pass from trying to move throwing insns, which lead to an RTL verification failure. This patch fixes that. Bootstrapped/regtested on aarch64-linux-gnu, OK for trunk? Thanks, Alex gcc/ChangeLog: PR target/113093 *

Re: [PATCH 1/3][RFC] RISC-V: Add non-vector types to pipelines

On 12/20/2023 10:50 AM, Jeff Law wrote: On 12/15/23 11:53, Edwin Lu wrote: This patch does not create vector related insn reservations for generic.md and sifive-7.md. It updates/creates insn reservations for all non-vector typed insns gcc/ChangeLog: * config/riscv/generic-ooo.md

[PATCH] c++: fix -Wparentheses with boolean-like class types

Bootstrap and regtesting in progress on x86_64-pc-linux-gnu, does this look OK for trunk if successful? -- >8 -- Since r14-4977-g0f2e2080685e75 the -Wparentheses warning now undesirably warns on the idiom Wparentheses-34.C:9:14: warning: suggest parentheses around assignment used as truth

Re: [PATCH v7 5/5] OpenMP/OpenACC: Reorganise OMP map clause handling in gimplify.cc

Hi Tobias, Thanks for review! Here's a new version of the patch which hopefully addresses this round of comments. On Tue, 19 Dec 2023 16:41:54 +0100 Tobias Burnus wrote: > On 16.12.23 14:25, Julian Brown wrote: > > --- a/gcc/gimplify.cc > > +++ b/gcc/gimplify.cc > > @@ -10107,6 +10114,20 @@

Re: [RFC][V2] RISC-V: Support -mcmodel=large.

On 12/20/23 10:41, Palmer Dabbelt wrote: On Wed, 20 Dec 2023 10:25:00 PST (-0800), jeffreya...@gmail.com wrote: On 12/20/23 11:21, Palmer Dabbelt wrote: Yea, the implementation relies largely on just pushing stuff into the constant pool, so we're largely independent ABI stuff with the

Re: PING^1 [PATCH] sched: Remove debug counter sched_block

On 12/11/23 23:17, Kewen.Lin wrote: Hi, Gentle ping this: https://gcc.gnu.org/pipermail/gcc-patches/2023-November/636597.html BR, Kewen on 2023/11/15 17:01, Kewen.Lin wrote: Hi, on 2023/11/10 01:40, Alexander Monakov wrote: I agree with the concern. I hoped that solving the problem by

Re: [pushed][PR112918][LRA]: Fixing IRA ICE on m68k

On Mon, 18 Dec 2023, Jeff Law wrote: > > > On 12/18/23 15:16, Vladimir Makarov wrote: > > The following patch fixes > > > > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112918 > > > > The patch was successfully bootstrapped and tested on x86-64, aarch64, and > > ppc64. > > > > The patch

Re: [PATCH] sel-sched: Verify change before replacing dest in EXPR_INSN_RTX [PR112995]

On 12/15/23 01:52, Kewen.Lin wrote: Hi, PR112995 exposed one issue in current try_replace_dest_reg that the result rtx insn after replace_dest_with_reg_in_expr is probably unable to match any constraints. Although there are some checks on the changes onto dest or src of orig_insn, none is

Re: Fortran: Use non conflicting file extensions for intermediates [PR81615]

Am 20.12.23 um 05:32 schrieb Rimvydas Jasinskas: Dear all, In the spirit of c/c++ using the .i/.ii extensions for intermediates, use the .fi/.fii intermediate extensions for gfortran fixed/free form sources when -save-temps is invoked to avoid various issues. I checked with Jerry on

[PATCH] c++: Enable -Walloc-size and -Wcalloc-transposed-args warnings for C++

Hi! The following patch enables the -Walloc-size and -Wcalloc-transposed-args warnings for C++ as well. Ok for trunk if it passes bootstrap/regtest? 2023-12-20 Jakub Jelinek gcc/c-family/ * c.opt (Walloc-size): Enable also for C++ and ObjC++. gcc/cp/ * cp-gimplify.cc

[PATCH] testsuite: Remove testsuite_tr1.h

This patch removes the testsuite_tr1.h dependency from g++.dg/ext/is_*.C tests since the header is supposed to be used only by libstdc++, not front-end. This also includes test code consistency fixes. gcc/testsuite/ChangeLog: * g++.dg/ext/is_array.C: Remove testsuite_tr1.h. Add

Re: [PATCH] cse: Fix handling of fake vec_select sets [PR111702]

> Am 20.12.2023 um 19:30 schrieb Richard Sandiford : > > If cse sees: > > (set (reg R) (const_vector [A B ...])) > > it creates fake sets of the form: > > (set R[0] A) > (set R[1] B) > ... > > (with R[n] replaced by appropriate rtl) and then adds them to the tables > in the same way

Re: [PATCH 3/3][RFC] RISC-V: Enable assert for insn_has_dfa_reservation

On 12/15/23 11:53, Edwin Lu wrote: Enables assert that every typed instruction is associated with a dfa reservation gcc/ChangeLog: * config/riscv/riscv.cc (riscv_sched_variable_issue): enable assert Once the prereqs are in, this is fine. jeff

Re: [PATCH 2/3][RFC] RISC-V: Add vector related reservations

On 12/15/23 11:53, Edwin Lu wrote: This patch copies the vector reservations from generic-ooo.md and inserts them into generic.md and sifive.md. The vector pipelines are necessary to avoid an ICE from the assert gcc/ChangeLog: * config/riscv/generic-ooo.md: syntax *

Re: [PATCH 1/3][RFC] RISC-V: Add non-vector types to pipelines

On 12/15/23 11:53, Edwin Lu wrote: This patch does not create vector related insn reservations for generic.md and sifive-7.md. It updates/creates insn reservations for all non-vector typed insns gcc/ChangeLog: * config/riscv/generic-ooo.md (generic_ooo_sfb_alu): create/update

Re: [RFC][V2] RISC-V: Support -mcmodel=large.

On Wed, 20 Dec 2023 10:25:00 PST (-0800), jeffreya...@gmail.com wrote: On 12/20/23 11:21, Palmer Dabbelt wrote: Yea, the implementation relies largely on just pushing stuff into the constant pool, so we're largely independent ABI stuff with the likely exception being relocations. Ya, but I

[PATCH] RISC-V: Add --with-cmodel configure-time argument

I couldn't find another way to set the default code model. gcc/ChangeLog: * config.gcc (RISC-V): Add --with-cmodel * config/riscv/riscv.h (TARGET_DEFAULT_CMODEL): Use TARGET_RISCV_DEFAULT_CMODEL --- I thought we had this already, but I figured I'd double-check my "ya,

[PATCH] cse: Fix handling of fake vec_select sets [PR111702]

If cse sees: (set (reg R) (const_vector [A B ...])) it creates fake sets of the form: (set R[0] A) (set R[1] B) ... (with R[n] replaced by appropriate rtl) and then adds them to the tables in the same way as for normal sets. This allows a sequence like: (set (reg R2) A) ...(reg

Re: [aarch64] PR111702 - ICE in insert_regs after interleave+zip1 vector initialization patch

Prathamesh Kulkarni writes: > Hi Richard, > For the test-case mentioned in PR111702, compiling with -O2 > -frounding-math -fstack-protector-all results in following ICE during > cse2 pass: > > test.c: In function 'foo': > test.c:119:1: internal compiler error: in insert_regs, at cse.cc:1120 >

Re: [RFC][V2] RISC-V: Support -mcmodel=large.

On 12/20/23 11:21, Palmer Dabbelt wrote: Yea, the implementation relies largely on just pushing stuff into the constant pool, so we're largely independent ABI stuff with the likely exception being relocations. Ya, but I think we'd only need the relocations if we were going to try relaxing

Re: [PATCH] RISC-V: Document -mcmodel=large

On Wed, 20 Dec 2023 10:13:06 PST (-0800), jeffreya...@gmail.com wrote: > > > On 12/20/23 11:08, Palmer Dabbelt wrote: >> This slipped through the cracks. Probably also NEWS-worthy. >> >> gcc/ChangeLog: >> >> * doc/invoke.texi (RISC-V): Add -mcmodel=large. > OK. > > And yes, I think we're

Re: [PATCH v3 4/6] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.

On 12/20/23 05:32, Jun Sha (Joshua) wrote: This patch adds th. prefix to all XTheadVector instructions by implementing new assembly output functions. gcc/ChangeLog: * config/riscv/riscv-protos.h (riscv_asm_output_opcode): New function. * config/riscv/riscv.cc

Re: [RFC][V2] RISC-V: Support -mcmodel=large.

On Wed, 20 Dec 2023 10:12:04 PST (-0800), jeffreya...@gmail.com wrote: On 12/20/23 11:05, Palmer Dabbelt wrote: On Wed, 20 Dec 2023 09:55:48 PST (-0800), jeffreya...@gmail.com wrote: On 12/18/23 00:46, KuanLin Chen wrote: Hi Jeff, Sorry for this missing. I've removed

[PATCH, wwwdocs] RISC-V: Add -mcmodel=large for GCC-14

This was just merged. Looks like we forgot to add any other NEWS items, so I've added the header as well. --- htdocs/gcc-14/changes.html | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/htdocs/gcc-14/changes.html b/htdocs/gcc-14/changes.html index 24e6409a..2a7432a7

Re: [PATCH v3 2/6] RISC-V: Split csr_operand in predicates.md for vector patterns.

On 12/20/23 05:27, Jun Sha (Joshua) wrote: This patch splits the definition of csr_operand in predicates.md. The newly defined vector_csr_operand has the same functionality as csr_operand but can only be used in vector patterns, so that changes for vector will not affect scalar patterns in

Re: [PATCH v3 1/6] RISC-V: Refactor riscv-vector-builtins-bases.cc

On 12/20/23 05:25, Jun Sha (Joshua) wrote: This patch moves the definition of the enums lst_type and frm_op_type into riscv-vector-builtins-bases.h and removes the static visibility of fold_fault_load(), so these can be used in other compile units. gcc/ChangeLog: *

Re: [PATCH] RISC-V: Document -mcmodel=large

On 12/20/23 11:08, Palmer Dabbelt wrote: This slipped through the cracks. Probably also NEWS-worthy. gcc/ChangeLog: * doc/invoke.texi (RISC-V): Add -mcmodel=large. OK. And yes, I think we're going to need to to a new/changes update for the port as a whole as part of the gcc-14

Re: [RFC][V2] RISC-V: Support -mcmodel=large.

On 12/20/23 11:05, Palmer Dabbelt wrote: On Wed, 20 Dec 2023 09:55:48 PST (-0800), jeffreya...@gmail.com wrote: On 12/18/23 00:46, KuanLin Chen wrote: Hi Jeff, Sorry for this missing. I've removed riscv_asm_output_pool_epilogue because the pool beginning is always aligned from

[PATCH] RISC-V: Document -mcmodel=large

This slipped through the cracks. Probably also NEWS-worthy. gcc/ChangeLog: * doc/invoke.texi (RISC-V): Add -mcmodel=large. --- gcc/doc/invoke.texi | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index

Re: [RFC][V2] RISC-V: Support -mcmodel=large.

On Wed, 20 Dec 2023 09:55:48 PST (-0800), jeffreya...@gmail.com wrote: On 12/18/23 00:46, KuanLin Chen wrote: Hi Jeff, Sorry for this missing. I've removed riscv_asm_output_pool_epilogue because the pool beginning is always aligned from FUNCTION_BOUNDARY. Please find attached. Thank you.

Re: [RFC][V2] RISC-V: Support -mcmodel=large.

On 12/18/23 00:46, KuanLin Chen wrote: Hi Jeff, Sorry for this missing. I've removed riscv_asm_output_pool_epilogue because the pool beginning is always aligned from FUNCTION_BOUNDARY. Please find attached. Thank you. Thanks. I regression tested this on rv64gc without any issues and fixed

Re: [PATCH] RISC-V: Block VLSmodes according to TARGET_MAX_LMUL and BITS_PER_RISCV_VECTOR

On Tue, 05 Dec 2023 04:57:27 PST (-0800), juzhe.zh...@rivai.ai wrote: This patch fixes ICE mentioned on PR112851 and PR112852. Actually these ICEs happens many times in full coverage testing. The ICE happens on: bug.c:84:1: internal compiler error: in partial_subreg_p, at rtl.h:3187 84 | }

Re: [PATCH] RISC-V: Fix bug of VSETVL fusion

On 12/19/23 23:50, Juzhe-Zhong wrote: This patch fixes bugs in the fusion of this following case: li a5,-1 vmv.s.x v0,a5 -> demand any non-zero AVL vsetvli a5, ... Incorrect fusion after VSETVL PASS: li a5,-1 vsetvli a5... vmv.s.x v0, a5 --> a5 is modified as incorrect value. We disallow

Re: [PATCH] RISC-V: Optimize SELECT_VL codegen when length is known as smaller than VF

On 12/19/23 23:55, Juzhe-Zhong wrote: While trying to fix bugs of PR113097, notice this following situation we generate redundant vsetvli _255 = SELECT_VL (3, POLY_INT_CST [4, 4]); COND_LEN (..., _255) Before this patch: vsetivli a5, 3... ... vadd.vv (use a5) After this patch: ...

Re: [PATCH] RISC-V: Fix RISCV_FUSE_ZEXTWS fusion condition

On 12/20/23 01:39, Wang Pengcheng wrote: The condition is RISCV_FUSE_ZEXTH, which is a mistake. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_macro_fusion_pair_p): Fix condition. I've pushed this to the trunk. Attached is the actual patch committed which also fixes formatting of that code.

[pushed] c++: throwing dtor and empty try [PR113088]

Tested x86_64-pc-linux-gnu, applying to trunk. -- 8< -- maybe_splice_retval_cleanup assumed that the function body can't be empty if there's a throwing cleanup, but when I added cleanups to try blocks in r12-6333-gb10e031458d541 I didn't adjust that assumption. PR c++/113088 PR

[pushed] c++: xvalue array subscript [PR103185]

Tested x86_64-pc-linux-gnu, applying to trunk. -- 8< -- Normally we handle xvalue array subscripting with ARRAY_REF, but in this case we weren't doing that because the operands were reversed. Handle that case better. PR c++/103185 gcc/cp/ChangeLog: * typeck.cc

Re: [PATCH] c++: implicit guides should inherit class constraints [PR104873]

On 12/20/23 12:00, Patrick Palka wrote: On Fri, 1 Apr 2022, Jason Merrill wrote: On 4/1/22 11:17, Patrick Palka wrote: An implicit guide already inherits the (rewritten) constraints of the constructor. Thus it seems natural that the guide must also inherit the constraints of the class

Re: [PATCH] compare_tests: distinguish c-c++-common results by tool

On 12/19/23 23:31, Alexandre Oliva wrote: On Dec 20, 2023, Jeff Law wrote: So the strub tests in c-c++-common are problematical. They get run twice, once for C, once for C++. Yet the name of the test is the same in both runs. (by the name, I mean the name emitted into the dejagnu summary

Re: [PATCH v26 00/23] Optimize type traits compilation performance

On Wed, Dec 20, 2023 at 7:56 AM Patrick Palka wrote: > > On Tue, 19 Dec 2023, Sandra Loosemore wrote: > > > On 12/6/23 22:11, Ken Matsui wrote: > > > This patch series optimizes type traits compilation performance by > > > implementing built-in type traits and using them in libstdc++. > > > > I'm

Re: [PATCH] RISC-V: Fix RISCV_FUSE_ZEXTWS fusion condition

On 12/20/23 01:39, Wang Pengcheng wrote: From: wangpc The condition is RISCV_FUSE_ZEXTH, which is a mistake. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_macro_fusion_pair_p): Fix condition. Thanks! As soon as this patch finishes regression testing I'll push it to the trunk. I'm

Re: [PATCH] c++: implicit guides should inherit class constraints [PR104873]

On Fri, 1 Apr 2022, Jason Merrill wrote: > On 4/1/22 11:17, Patrick Palka wrote: > > An implicit guide already inherits the (rewritten) constraints of the > > constructor. Thus it seems natural that the guide must also inherit > > the constraints of the class template, since a constructor's

Re: [PATCH 2/2] arm: Add support for MVE Tail-Predicated Low Overhead Loops

Squashed the definition and changes to predicated_doloop_end_internal and dlstp*_insn into this patch to make sure the first patch builds independently On 18/12/2023 11:53, Andre Vieira wrote: Reworked Stam's patch after comments in:

Re: [PATCH 1/2] arm: Add define_attr to to create a mapping between MVE predicated and unpredicated insns

Reworked patch after Richard's comments and moved predicated_doloop_end_internal and dlstp*_insn to the next patch in the series to make sure this one builds on its own. On 18/12/2023 11:53, Andre Vieira wrote: Re-sending Stam's first patch, same as:

Re: [PATCH v2 2/3] RISC-V: setmem for RISCV with V extension

On 12/20/23 02:48, Sergei Lewis wrote: Hi, This has been tested with the following configurations: rv64gcv_zvl128b rv64gcv_zvl256b rv32imafd_zve32x1p0 rv32gc_zve64f_zvl128b I'll drop the constraints and add the testing info to the cover email in v3. I'll hold off submitting v3 until gcc-15

Re: [PATCH v26 00/23] Optimize type traits compilation performance

On Tue, 19 Dec 2023, Sandra Loosemore wrote: > On 12/6/23 22:11, Ken Matsui wrote: > > This patch series optimizes type traits compilation performance by > > implementing built-in type traits and using them in libstdc++. > > I'm finding that all the new g++.dg/ext/is_*.C testcases added by this

Re: Re: [PATCH] RISC-V: Fix calculation of max live vregs

Ok. Thanks Jeff reminding me. Will be carefull next time. juzhe.zh...@rivai.ai From: Jeff Law Date: 2023-12-20 23:28 To: juzhe.zh...@rivai.ai; demin.han; gcc-patches CC: pan2.li Subject: Re: [PATCH] RISC-V: Fix calculation of max live vregs On 12/20/23 04:17, juzhe.zh...@rivai.ai wrote: >

Re: [PATCH] RISC-V: Fix calculation of max live vregs

On 12/20/23 04:17, juzhe.zh...@rivai.ai wrote: I see. LGTM. Thanks for explanation. I will ask Li Pan commit it for you. The patch from Demin didn't specify if it had been regression tested. All patches must be regression tested and an indication that the test passed and on what target

omp: Fix simdclone arguments with veclen lower than simdlen [PR113040]

This patch fixes an issue introduced by: commit ea4a3d08f11a59319df7b750a955ac613a3f438a Author: Andre Vieira Date: Wed Nov 1 17:02:41 2023 + omp: Reorder call for TARGET_SIMD_CLONE_ADJUST The problem was that after this patch we no longer added multiple arguments for vector

[PATCH] [OpenACC] Add tests for implied copy of variables in reduction clause.

From: Hafiz Abid Qadeer The OpenACC reduction clause on compute construct implies a copy clause for each reduction variable [1]. This patch adds tests to check if the implied copy is being generated. The check covers various types and operators as described in the specification.

Re: [PATCH] tree-object-size: Clean up unknown propagation

On 2023-12-20 00:23, Jeff Law wrote: On 12/19/23 10:21, Siddhesh Poyarekar wrote: Narrow down scope of the unknowns bitmap so that it is only accessible within the reexamination process.  This also removes any role of unknown propagation from object_sizes_set, thus simplifying that code path

Re: veclower: improve selection of vector mode when lowering [PR 112787]

On Wed, 20 Dec 2023, Andre Vieira (lists) wrote: > Thanks, fully agree with all comments. > > gcc/ChangeLog: > > PR target/112787 > * tree-vect-generic (type_for_widest_vector_mode): Change function > to use original vector type and check widest vector mode has at most >

Re: [PATCH 1/8] OpenMP: lvalue parsing for map/to/from clauses (C++)

On 05.09.23 21:28, Julian Brown wrote: This patch supports "lvalue" parsing (or "locator list item type" parsing) for several OpenMP clause types for C++, as required for OpenMP 5.0 and above. It is based on the version committed to the og13 branch, posted here:

Re: [PATCH] tree-optimization/113073 - amend PR112736 fix

Hi Richard! On 2023-12-20T14:44:29+0100, Richard Biener wrote: > On Wed, 20 Dec 2023, Richard Biener wrote: >> On Wed, 20 Dec 2023, Thomas Schwinge wrote: >> > On 2023-12-19T13:30:58+0100, Richard Biener wrote: >> > > The PR112736 testcase fails on RISC-V because the aligned exception >> > >

Re: veclower: improve selection of vector mode when lowering [PR 112787]

Thanks, fully agree with all comments. gcc/ChangeLog: PR target/112787 * tree-vect-generic (type_for_widest_vector_mode): Change function to use original vector type and check widest vector mode has at most the same number of elements.

No libstdc++ for GCN (was: No libstdc++ for nvptx)

Hi! On 2015-03-11T22:44:27+0100, I wrote: > I committed the following in r221362: > No libstdc++ for nvptx. > > The C++ front end insists to link against libstdc++ -- which we don't > build: > > $ < build-gcc/gcc/testsuite/g++/g++.log grep -o 'error opening > [^[:cntrl:]]*' |

Re: [PATCH] tree-optimization/113073 - amend PR112736 fix

On Wed, 20 Dec 2023, Richard Biener wrote: > On Wed, 20 Dec 2023, Thomas Schwinge wrote: > > > Hi! > > > > On 2023-12-19T13:30:58+0100, Richard Biener wrote: > > > The PR112736 testcase fails on RISC-V because the aligned exception > > > uses the wrong check. The alignment support scheme can

[PATCH] Improve DCE of dead parts of a permute chain

gcc.dg/vect/bb-slp-pr78205.c is reported to have regressed with the PR113073 change and in the end it's due to the DCE performed by vect_transform_slp_perm_load_1 being imperfect. The following enhances it to also cover the CTOR and VIEW_CONVERT operations that might be involved. Bootstrapped

[PATCH v3 6/6] RISC-V: Add support for xtheadvector-specific intrinsics.

This patch only involves the generation of xtheadvector special load/store instructions and vext instructions. gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (class th_loadstore_width): Define new builtin bases. (BASE): Define new builtin bases. *

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