[rtlanal.c][BE][1/2] Fix vector load/stores to not use ld1/st1

of the highest-numbered register. This will apply cleanly by itself and no regressions were seen when testing aarch64 and x86_64 on make check. Changelog: 2014-11-14 Alan Hayward alan.hayw...@arm.com * rtlanal.c (subreg_get_info): Exit early for simple and common cases Alan

[Aarch64][BE][2/2] Fix vector load/stores to not use ld1/st1

. This patch requires part 1 and David Sherwood’s patch: [AArch64] [BE] [1/2] Make large opaque integer modes endianness-safe. When tested with David’s patch and [1/2] of this patch, no regressions were seen when testing aarch64 and x86_64 on make check. Changelog: 2014-11-14 Alan Hayward

FW: [Aarch64][BE][2/2] Fix vector load/stores to not use ld1/st1

On 20/11/2014 18:13, Marcus Shawcroft marcus.shawcr...@gmail.com wrote: On 14 November 2014 16:48, Alan Hayward alan.hayw...@arm.com wrote: This is a new version of my BE patch from a few weeks ago. This is part 2 and covers all the aarch64 changes. When combined with the first patch, It fixes

Re: [rtlanal.c][BE][1/2] Fix vector load/stores to not use ld1/st1

On 14/11/2014 16:48, Alan Hayward alan.hayw...@arm.com wrote: This is a new version of my BE patch from a few weeks ago. This is part 1 and covers rtlanal.c. The second part will be aarch64 specific. When combined with the second patch, It fixes up movoi/ci/xi for Big Endian, so that we end up

[AArch64] [BE] Fix vector load/stores to not use ld1/st1

”. No regressions. ChangeLog: gcc/: 2014-10-10 Alan Hayward alan.hayw...@arm.com * config/aarch64/aarch64.c (aarch64_classify_address): Allow extra addressing modes for BE. (aarch64_print_operand): new operand for printing a q register+1

Re: [AArch64] [BE] Fix vector load/stores to not use ld1/st1

On 06/11/2014 09:09, Yangfei (Felix) felix.y...@huawei.com wrote: On 10 October 2014 16:19, Alan Hayward alan.hayw...@arm.com wrote: This patch is dependant on [AArch64] [BE] [1/2] Make large opaque integer modes endianness-safe.” It fixes up movoi/ci/xi for Big Endian, so that we end

Re: [rtlanal.c][BE][1/2] Fix vector load/stores to not use ld1/st1

On 21/11/2014 14:08, Alan Hayward alan.hayw...@arm.com wrote: On 14/11/2014 16:48, Alan Hayward alan.hayw...@arm.com wrote: This is a new version of my BE patch from a few weeks ago. This is part 1 and covers rtlanal.c. The second part will be aarch64 specific. When combined with the second

Re: [PATCH][rtlanal.c][BE][1/2] Fix vector load/stores to not use ld1/st1

On 02/12/2014 12:36, Alan Hayward alan.hayw...@arm.com wrote: On 21/11/2014 14:08, Alan Hayward alan.hayw...@arm.com wrote: On 14/11/2014 16:48, Alan Hayward alan.hayw...@arm.com wrote: This is a new version of my BE patch from a few weeks ago. This is part 1 and covers rtlanal.c. The second

[PATCH][rtlanal.c][BE][1/2] Fix vector load/stores to not use ld1/st1

. This second part has already been approved. This patch will apply cleanly by itself and no regressions were seen when testing aarch64 and x86_64 on make check. Cheers, Alan Changelog: 2014-11-14 Alan Hayward alan.hayw...@arm.com * rtlanal.c (subreg_get_info): Exit early for simple

[COMMITTED] Add myself to MAINTAINERS (Write After Approval)

Hi All, I've just added myself to Write After Approval maintainers. Committed r229216 Cheers, Alan. Index: ChangeLog === --- ChangeLog (revision 229215) +++ ChangeLog (revision 229216) @@ -1,3 +1,7 @@ +2015-10-23 Alan Hayward

Re: [PATCH] vectorizing conditional expressions (PR tree-optimization/65947)

On 22/10/2015 15:15, "Alan Lawrence" <alan.lawre...@arm.com> wrote: >Just one very small point... > >On 19/10/15 09:17, Alan Hayward wrote: > > > - if (check_reduction > > - && (!commutative_tree_code (code) || !associativ

[PATCH] Fix VEC_COND_EXPR types when vectorizing conditional expressions

VEC_COND_EXPRs have been changed to use boolean vectors for the first argument. This changes the vectorizing conditional expressions to use this new format, fixing the compiler failures for the 65947-*.c tests. 2015-10-26 Alan Hayward <alan.hayw...@arm.com\> gcc/ PR tree-optimi

Re: [Patch] Avoid is_simple_use bug in vectorizable_live_operation

On 27/10/2015 11:36, "Richard Biener" <richard.guent...@gmail.com> wrote: >On Mon, Oct 26, 2015 at 6:15 PM, Alan Hayward <alan.hayw...@arm.com> >wrote: >> >> >> On 26/10/2015 13:35, "Richard Biener" <richard.guent...@gmail.com>

[Patch] Avoid is_simple_use bug in vectorizable_live_operation

that is not clear from the code. The fix is to simply ensure dt is initialized to a default value on each iteration. 2015-09-07 Alan Hayward alan.hayw...@arm.com * tree-vect-looop.c (vectorizable_live_operation): localize variable. Cheers, Alan avoid_issimple.patch Description: Binary

Re: [Patch] Avoid is_simple_use bug in vectorizable_live_operation

On 26/10/2015 13:35, "Richard Biener" <richard.guent...@gmail.com> wrote: >On Mon, Oct 26, 2015 at 1:33 PM, Alan Hayward <alan.hayw...@arm.com> >wrote: >> There is a potential bug in vectorizable_live_operation. >> >> Consider the case where

[Patch] Optimize condition reductions where the result is an integer induction variable

Hi, I hoped to post this in time for Monday’s cut off date, but circumstances delayed me until today. Hoping if possible this patch will still be able to go in. This patch builds upon the change for PR65947, and reduces the amount of code produced in a vectorized condition reduction where

Re: [Patch] Optimize condition reductions where the result is an integer induction variable

On 11/11/2015 13:25, "Richard Biener" <richard.guent...@gmail.com> wrote: >On Wed, Nov 11, 2015 at 1:22 PM, Alan Hayward <alan.hayw...@arm.com> >wrote: >> Hi, >> I hoped to post this in time for Monday’s cut off date, but >>circumstances >> d

Re: [Patch] Optimize condition reductions where the result is an integer induction variable

On 12/11/2015 10:53, "Richard Biener" <richard.guent...@gmail.com> wrote: >On Wed, Nov 11, 2015 at 7:54 PM, Alan Hayward <alan.hayw...@arm.com> >wrote: >> >> >> On 11/11/2015 13:25, "Richard Biener" <richard.guent...@gmail.com>

[PATCH] vectorizing conditional expressions (PR tree-optimization/65947)

s case a lot of the new code can be optimized away. I have run check for aarch64, arm and x86 and have seen no regressions. Changelog: 2015-08-28 Alan Hayward <alan.hayw...@arm.com> PR tree-optimization/65947 * tree-vect-loop.c (vect_is_simple_reduction_

Re: [PATCH] vectorizing conditional expressions (PR tree-optimization/65947)

as >costly in and of itself. Also, the sequence will produce the maximum >value in all positions without a separate broadcast.) > >Thanks, >Bill > >On Thu, 2015-09-10 at 15:51 +0100, Alan Hayward wrote: >> Hi, >> This patch (attached) adds support for vectoriz

Re: [PATCH] vectorizing conditional expressions (PR tree-optimization/65947)

On 15/09/2015 13:09, "Richard Biener" wrote: > >Now comments on the patch itself. > >+ if (code == COND_EXPR) >+ *v_reduc_type = COND_REDUCTION; > >so why not simply use COND_EXPR instead of the new v_reduc_type? v_reduc_type is also dependant on

Re: [PATCH] vectorizing conditional expressions (PR tree-optimization/65947)

On 30/09/2015 13:45, "Richard Biener" <richard.guent...@gmail.com> wrote: >On Wed, Sep 23, 2015 at 5:51 PM, Alan Hayward <alan.hayw...@arm.com> >wrote: >> >> >> On 18/09/2015 14:53, "Alan Hayward" <alan.hayw...@arm.com> wrote:

Re: [PATCH] vectorizing conditional expressions (PR tree-optimization/65947)

On 18/09/2015 14:53, "Alan Hayward" <alan.hayw...@arm.com> wrote: > > >On 18/09/2015 14:26, "Alan Lawrence" <alan.lawre...@arm.com> wrote: > >>On 18/09/15 13:17, Richard Biener wrote: >>> >>> Ok, I see. >>&g

Re: [PATCH] vectorizing conditional expressions (PR tree-optimization/65947)

On 18/09/2015 14:26, "Alan Lawrence" wrote: >On 18/09/15 13:17, Richard Biener wrote: >> >> Ok, I see. >> >> That this case is already vectorized is because it implements MAX_EXPR, >> modifying it slightly to >> >> int foo (int *a) >> { >>int val = 0; >>for (int i

Re: [PATCH] PR tree-optimization/68413 : Only check for integer cond reduction on analysis stage

On 20/11/2015 13:47, "Richard Biener" <richard.guent...@gmail.com> wrote: >On Fri, Nov 20, 2015 at 1:33 PM, Alan Hayward <alan.hayw...@arm.com> >wrote: >> >> >>On 20/11/2015 11:00, "Richard Biener" <richard.guent...@gmail.com&g

Re: [PATCH] PR tree-optimization/68413 : Only check for integer cond reduction on analysis stage

On 20/11/2015 11:00, "Richard Biener" <richard.guent...@gmail.com> wrote: >On Fri, Nov 20, 2015 at 10:24 AM, Alan Hayward <alan.hayw...@arm.com> >wrote: >> When vectorising a integer induction condition reduction, >> is_nonwrapping_integer_inductio

[PATCH] PR tree-optimization/68413 : Only check for integer cond reduction on analysis stage

When vectorising a integer induction condition reduction, is_nonwrapping_integer_induction ends up with different values for base during the analysis and build phases. In the first it is an INTEGER_CST, in the second the loop has been vectorised out and the base is now a variable. This results in

[PATCH] Fix check_GNU_style.sh for BSD / Mac OS X

check_GNU_style.sh fails to detect lines >80 chars on BSD / Mac OS X systems. This is becuase paste is being called with an empty delimiter list. Instead \0 should be used. Tested on Ubuntu 14.04 and OS X 10.9.5 contrib/ * check_GNU_style.sh: Fix paste args for BSD Alan diff --git

[PATCH] Fix PR 71407 : Use correct types for live usage of live operations

This patch fixes PR 71407 by ensuring the BIT_FIELD_REF is created using the given vectype and then casted to the result type. Tested on x86 and aarch64. Note that the test vectorizes on x86 but does not vectorize on aarch64 or power (due to a != statement failing to vectorize) Ok to commit?

Re: [PATCH][2/3] Vectorize inductions that are live after the loop

On 05/06/2016 12:00, "Andreas Schwab" <sch...@linux-m68k.org> wrote: >Alan Hayward <alan.hayw...@arm.com> writes: > >> * gcc.dg/vect/vect-live-2.c: New test. > >This test fails on powerpc64 (with -m64, but not with -m32): > >$ grep 'vector

Re: [PATCH][2/3] Vectorize inductions that are live after the loop

On 03/06/2016 18:45, "Jakub Jelinek" <ja...@redhat.com> wrote: >On Thu, Jun 02, 2016 at 05:11:15PM +0100, Alan Hayward wrote: >> * gcc.dg/vect/vect-live-1.c: New test. >> * gcc.dg/vect/vect-live-2.c: New test. >> * gcc.dg/vect/vect-live-5.c:

Re: [PATCH][vectorizer] Remove blank debug lines after dump_gimple_stmt

On 06/06/2016 18:56, "Jeff Law" <l...@redhat.com> wrote: >On 06/06/2016 06:46 AM, Alan Hayward wrote: >> Lots of code calls dump_gimple_stmt then print a newline, however >> dump_gimple_stmt will print a newline itself. This makes the vectorizer >> debug

[PATCH][vectorizer] Remove blank debug lines after dump_gimple_stmt

Lots of code calls dump_gimple_stmt then print a newline, however dump_gimple_stmt will print a newline itself. This makes the vectorizer debug file messy. I think the confusion is because dump_generic_expr does NOT print a newline. This patch removes all prints of a newline direcly after a

Re: [PATCH][2/3] Vectorize inductions that are live after the loop

On 07/06/2016 10:28, "Rainer Orth" <r...@cebitec.uni-bielefeld.de> wrote: >Alan Hayward <alan.hayw...@arm.com> writes: > >> On 05/06/2016 12:00, "Andreas Schwab" <sch...@linux-m68k.org> wrote: >> >>>Alan Hayward <alan.hayw..

[PATCH] PR 71483 - Fix live SLP operations

In the given testcase, g++ splits a live operation into two scalar statements and four vector statements. _5 = _4 >> 2; _7 = (short int) _5; Is turned into: vect__5.32_80 = vect__4.31_76 >> 2; vect__5.32_81 = vect__4.31_77 >> 2; vect__5.32_82 = vect__4.31_78 >> 2; vect__5.32_83 =

[PATCH] PR 71439 - Only vectorize live PHIs that are inductions

For a PHI to be used outside the loop it needs to be vectorized. However the vectorizer currently will only vectorize PHIs that are an induction. This patch fixes PR 71439 by only allowing a live PHI to be vectorized if it is an induction. In addition, live PHIs need to pass a

[PATCH] PR 71416 - allow more than one use of a live operation

vectorizable_live_operation checks that there is exactly one use of each operation that has been marked live. However, it is possible for the operation is used more than once if the usage PHIs are identical. For example in 71416-1.c, _6 is used twice after the loop in bb 9. : # e.6_21 = PHI

[PATCH][3/3] No need to vectorize simple only-live stmts

Statements which are live but not relevant need marking to ensure they are vectorized. Live statements which are simple and all uses of them are invariant do not need to be vectorized. This patch adds a check to make sure those stmts which pass both the above checks are not vectorized and then

[PATCH][2/3] Vectorize inductions that are live after the loop

This patch is a reworking of the previous vectorize inductions that are live after the loop patch. It now supports SLP and an optimisation has been moved to patch [3/3]. Stmts which are live (ie: defined inside a loop and then used after the loop) are not currently supported by the vectorizer.

[PATCH][1/3] Add loop_vinfo to vect_get_vec_def_for_operand

This patch simply adds loop_vinfo as an extra argument to vect_get_vec_def_for_operand and only generates a stmt_vinfo if required. This is a required cleanup for patch [2/3]. Tested on x86 and aarch64. gcc/ * tree-vectorizer.h (vect_get_vec_def_for_operand): Pass loop_vinfo in. *

Re: [PATCH][2/3] Vectorize inductions that are live after the loop

On 27/05/2016 12:41, "Richard Biener" <richard.guent...@gmail.com> wrote: >On Fri, May 27, 2016 at 11:09 AM, Alan Hayward <alan.hayw...@arm.com> >wrote: >> This patch is a reworking of the previous vectorize inductions that are >> live >>

Remove duplicated GOMP SIMD LANE code

The IFN_GOMP_SIMD_LANE code in vectorizable_call is essentially a duplicate of the code in vectorizable_live_operation. They both replace all uses outside the loop with the constant VF - 1. Note that my patch to vectorize inductions that are live after the loop will also remove the

Re: [PATCH][2/3] Vectorize inductions that are live after the loop

On 01/06/2016 10:51, "Richard Biener" <richard.guent...@gmail.com> wrote: >On Wed, Jun 1, 2016 at 10:46 AM, Alan Hayward <alan.hayw...@arm.com> >wrote: >> >> >> On 30/05/2016 14:22, "Richard Biener" <richard.guent...@gmail.com>

Re: [PATCH][1/3] Add loop_vinfo to vect_get_vec_def_for_operand

> This patch simply adds loop_vinfo as an extra argument to > vect_get_vec_def_for_operand and only generates a stmt_vinfo if required. > This is a required cleanup for patch [2/3]. > Tested on x86 and aarch64. > > gcc/ > * tree-vectorizer.h (vect_get_vec_def_for_operand): Pass loop_vinfo in. > *

Re: [PATCH][3/3] No need to vectorize simple only-live stmts

>Statements which are live but not relevant need marking to ensure they are >vectorized. > >Live statements which are simple and all uses of them are invariant do not >need >to be vectorized. > >This patch adds a check to make sure those stmts which pass both the above >checks are not vectorized

Re: [PATCH][2/3] Vectorize inductions that are live after the loop

On 30/05/2016 14:22, "Richard Biener" <richard.guent...@gmail.com> wrote: >On Fri, May 27, 2016 at 5:12 PM, Alan Hayward <alan.hayw...@arm.com> >wrote: >> >> On 27/05/2016 12:41, "Richard Biener" <richard.guent...@gmail.com> >&

[PATCH] PR 71667 - Handle live operations with DEBUG uses

In vectorizable_live_operation() we always assume uses a of live operation will be PHIs. However, when using -g a use of a live operation might be a DEBUG stmt. This patch avoids adding any DEBUG statments to the worklist in vectorizable_live_operation(). Also fixes comment. Tested on x86 and

[PATCH] Vectorize inductions that are live after the loop.

Vectorize inductions that are live after the loop. Stmts which are live (ie: defined inside a loop and then used after the loop) are not currently supported by the vectorizer. In many cases vectorization can still occur because the SCEV cprop pass will hoist the definition of the stmt outside of

Re: [PATCH] Vectorize inductions that are live after the loop.

Thanks for the review. On 23/05/2016 11:35, "Richard Biener" wrote: > >@@ -6332,79 +6324,81 @@ vectorizable_live_operation (gimple *stmt, > stmt_vec_info stmt_info = vinfo_for_stmt (stmt); > loop_vec_info loop_vinfo = STMT_VINFO_LOOP_VINFO (stmt_info); >

PATCH: PR71818: Don't advance IVs with a variable step

In the given test case, the loop is split into vectorised and non vectorised versions due to peeling. At the end of the loop the IVs are incremented to their latest value. This is achieved by taking the base of the loop (g_21) and adding the iterations (240) multiplied by the step (_6): : #

Re: PATCH: PR71818: Don't advance IVs with a variable step

On 01/08/2016 14:49, "Richard Biener" <richard.guent...@gmail.com> wrote: >On Mon, Aug 1, 2016 at 11:24 AM, Alan Hayward <alan.hayw...@arm.com> >wrote: >> In the given test case, the loop is split into vectorised and non >> vectorised >> versions

[PATCH] PR71752 - SLP: Maintain operand ordering when creating vec defs

The testcase pr71752.c was failing because the SLP code was generating an SLP vector using arguments from the SLP scalar stmts, but was using the wrong argument number. vect_get_slp_defs() is given a vector of operands. When calling down to vect_get_constant_vectors it uses i as op_num - making

PING Re:[PATCH] PR 71667 - Handle live operations with DEBUG uses

Ping. From: Alan Hayward To: "gcc-patches at gcc dot gnu dot org" Date: Wed, 29 Jun 2016 08:49:34 +0100 Subject: [PATCH] PR 71667 - Handle live operations with DEBUG uses Authentication-results: sourceware.org; auth=none In vectorizable_live_operation() we always assume uses

Re: [PATCH], Pr 71667, Fix PowerPC ISA 3.0 DImode Altivec load/store

Hi, This patch references the wrong bug. It should reference 71677 and not 71667 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71677 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71667 Thanks, Alan. As we discussed in the patch review, there were some issues with using %Y for the ISA 3.0

Re: [PATCH] PR71752 - SLP: Maintain operand ordering when creating vec defs

On 15/08/2016 12:17, "Richard Biener" <richard.guent...@gmail.com> wrote: >On Mon, Aug 15, 2016 at 11:48 AM, Alan Hayward <alan.hayw...@arm.com> >wrote: >> The testcase pr71752.c was failing because the SLP code was generating >>an >> SLP >&

Re: [PATCH] PR71752 - SLP: Maintain operand ordering when creating vec defs

On 16/08/2016 10:01, "Alan Hayward" <alan.hayw...@arm.com> wrote: > > >On 16/08/2016 09:33, "Richard Biener" <richard.guent...@gmail.com> wrote: > >>On Mon, Aug 15, 2016 at 4:16 PM, Alan Hayward <alan.hayw...@arm.com> >>wrote: &g

Re: [PATCH] Fix PR81090, properly free niter estimates

> On 19 Jun 2017, at 13:35, Richard Biener wrote: > > On Mon, 19 Jun 2017, Christophe Lyon wrote: > >> Hi Richard, >> >> On 16 June 2017 at 14:18, Richard Biener wrote: >>> On Wed, 14 Jun 2017, Richard Biener wrote: >>> niter estimates are

Re: [PATCH] Implement cond and induction cond reduction w/o REDUC_MAX_EXPR

> On 22 Jun 2017, at 09:52, Richard Biener wrote: > > On Thu, 22 Jun 2017, Richard Biener wrote: > >> On Wed, 21 Jun 2017, Richard Biener wrote: >> >>> >>> During my attempt to refactor reduction vectorization I ran across >>> the special casing of inital values for

Re: [PATCH] Implement cond and induction cond reduction w/o REDUC_MAX_EXPR

> On 22 Jun 2017, at 12:54, Richard Biener <rguent...@suse.de> wrote: > > On Thu, 22 Jun 2017, Alan Hayward wrote: > >> >>> On 22 Jun 2017, at 09:52, Richard Biener <rguent...@suse.de> wrote: >>> >>> On Thu, 22 Jun 2017, Richard Bi

Re: [PATCH 1/7]: SVE: Add CLOBBER_HIGH expression

> On 21 Nov 2017, at 03:13, Jeff Law wrote: >> >>> >>> You might also look at TARGET_HARD_REGNO_CALL_PART_CLOBBERED. I'd >>> totally forgotten about it. And in fact it seems to come pretty close >>> to what you need… >> >> Yes, some of the code is similar to the way >>

Re: [PATCH] Fix result for conditional reductions matching at index 0

> On 22 Nov 2017, at 09:14, Richard Biener wrote: > > On Tue, Nov 21, 2017 at 5:43 PM, Kilian Verhetsel > wrote: >> >>> This is PR81179 I think, please mention that in the changelog. >> >> Correct, my bad for missing that. >> >>>

Re: [PATCH 1/7]: SVE: Add CLOBBER_HIGH expression

> On 22 Nov 2017, at 17:33, Jeff Law <l...@redhat.com> wrote: > > On 11/22/2017 04:31 AM, Alan Hayward wrote: >> >>> On 21 Nov 2017, at 03:13, Jeff Law <l...@redhat.com> wrote: >>>> >>>>> >>>>> You might also loo

Re: [PATCH] Fix result for conditional reductions matching at index 0

> On 22 Nov 2017, at 16:57, Kilian Verhetsel > wrote: > > > Thank you both for your comments. > > I have added the check to ensure the index vector won't cause an > overflow. I also added tests to the testsuite in order to check that the > loop is vectorized

Re: [PATCH 1/7]: SVE: Add CLOBBER_HIGH expression

> On 27 Nov 2017, at 17:29, Jeff Law <l...@redhat.com> wrote: > > On 11/23/2017 04:11 AM, Alan Hayward wrote: >> >>> On 22 Nov 2017, at 17:33, Jeff Law <l...@redhat.com> wrote: >>> >>> On 11/22/2017 04:31 AM, Alan Hayward wrote: >>&

Re: [PATCH 1/7]: SVE: Add CLOBBER_HIGH expression

Ping ping. I think there should be enough information in the first test to show that any "set to self” registers become live. Let me know if there’s anything I’ve missed. Thanks, Alan. > On 12 Dec 2017, at 11:11, Alan Hayward <alan.hayw...@arm.com> wrote: > > Ping. > &

Re: [PATCH 7/7]: Enable clobber high for tls descs on Aarch64

> On 16 Nov 2017, at 19:32, Andrew Pinski <pins...@gmail.com> wrote: > > On Thu, Nov 16, 2017 at 4:35 AM, Alan Hayward <alan.hayw...@arm.com> wrote: >> This final patch adds the clobber high expressions to tls_desc for aarch64. >> It also adds three tests.

[PATCH 5/7]: cse support for clobber_high

This patch simply adds the cse specific changes for clobber_high. Alan. 2017-11-16 Alan Hayward <alan.hayw...@arm.com> * cse.c (invalidate_reg): New function extracted from... (invalidate): ...here. (canonicalize_insn): Check for clobbe

[PATCH 6/7]: Remaining support for clobber high

This patch simply adds the remainder of clobber high checks. Happy to split this into smaller patches if required (there didn't seem anything obvious to split into). Alan. 2017-11-16 Alan Hayward <alan.hayw...@arm.com> * alias.c (record_set): Check for clobbe

[PATCH 2/7] Support >26 operands in generation code.

. 2017-11-16 Alan Hayward <alan.hayw...@arm.com> * emit-rtl.c (verify_rtx_sharing): Check CLOBBER_HIGH. (copy_insn_1): Likewise. (gen_hard_reg_clobber_high): Add function. * genconfig.c (walk_insn_part): Check CLOBBER_HIGH. * genemit.c (gen_exp): Li

[PATCH 4/7]: lra support for clobber_high

This patch simply adds the lra specific changes for clobber_high. Alan. 2017-11-16 Alan Hayward <alan.hayw...@arm.com> * lra-eliminations.c (lra_eliminate_regs_1): Check for clobber high. (mark_not_eliminable): Likewise. * lra-int.h (struct lra_insn_reg): Add c

[PATCH 3/7] Add func to check if register is clobbered by clobber_high

. Alan. 2017-11-16 Alan Hayward <alan.hayw...@arm.com> * rtl.h (reg_is_clobbered_by_clobber_high): Add declarations. * rtlanal.c (reg_is_clobbered_by_clobber_high): Add function. diff --git a/gcc/rtl.h b/gcc/rtl.h index bdb05d00120e7fadeb7f2d29bd67afc7a7

[PATCH 1/7]: SVE: Add CLOBBER_HIGH expression

/sve branch. A simpler alternative to this patch would be to assume all Neon and SVE registers are clobbered across TLS calls, however this would be a performance regression against all Aarch64 targets. Alan. 2017-11-16 Alan Hayward <alan.hayw...@arm.com> * doc/rtl.texi (clobbe

[PATCH 7/7]: Enable clobber high for tls descs on Aarch64

between ASM files before and after the patch. Alan. 2017-11-16 Alan Hayward <alan.hayw...@arm.com> gcc/ * config/aarch64/aarch64.md: Add clobber highs to tls_desc. gcc/testsuite/ * gcc.target/aarch64/sve_tls_preserve_1.c: New test. * gcc.target/a

Re: [PATCH 1/7]: SVE: Add CLOBBER_HIGH expression

> On 17 Nov 2017, at 19:31, Jeff Law <l...@redhat.com> wrote: > > On 11/16/2017 11:50 AM, Alan Hayward wrote: >> >>> On 16 Nov 2017, at 18:24, Richard Biener <richard.guent...@gmail.com> wrote: >>> >>> On November 16, 2017 7:05:30 PM GMT+

Re: [PATCH] Fix result for conditional reductions matching at index 0

> On 21 Nov 2017, at 16:43, Kilian Verhetsel > wrote: > > >> This is PR81179 I think, please mention that in the changelog. > > Correct, my bad for missing that. > >> This unconditionally pessimizes code even if there is no valid index >> zero, right? > >

Re: [PATCH 1/7]: SVE: Add CLOBBER_HIGH expression

> On 16 Nov 2017, at 18:24, Richard Biener <richard.guent...@gmail.com> wrote: > > On November 16, 2017 7:05:30 PM GMT+01:00, Jeff Law <l...@redhat.com> wrote: >> On 11/16/2017 05:34 AM, Alan Hayward wrote: >>> This is a set of patches aimed at supporting a

Re: [PATCH 1/7]: SVE: Add CLOBBER_HIGH expression

Ping. > On 30 Nov 2017, at 11:03, Alan Hayward <alan.hayw...@arm.com> wrote: > > >> On 27 Nov 2017, at 17:29, Jeff Law <l...@redhat.com> wrote: >> >> On 11/23/2017 04:11 AM, Alan Hayward wrote: >>> >>>> On 22 Nov 2017, at 17:33, Jeff

Re: [PATCH 1/7]: SVE: Add CLOBBER_HIGH expression

> On 19 Dec 2017, at 16:27, Jeff Law <l...@redhat.com> wrote: > > On 12/19/2017 03:12 AM, Alan Hayward wrote: >> Ping ping. >> I think there should be enough information in the first test to show that >> any "set to self” >> registers become live.

Re: [PATCH 2/7] Support >26 operands in generation code.

> On 6 Feb 2018, at 17:03, Richard Sandiford <richard.sandif...@linaro.org> > wrote: > > Alan Hayward <alan.hayw...@arm.com> writes: >> This patch adds support for CLOBBER_HIGH in the generation code. >> >> An aarch64 will require 31 clob

[PATCH v2 6/7] Remaining support for clobber high

Add the remainder of clobber high checks. Happy to split this into smaller patches if required (there didn't seem anything obvious to split into). 2018-07-25 Alan Hayward * alias.c (record_set): Check for clobber high. * cfgexpand.c (expand_gimple_stmt): Likewise

[PATCH v2 7/7] Enable clobber high for tls descs on Aarch64

before and after the patch. Alan. 2018-07-25 Alan Hayward gcc/ * config/aarch64/aarch64.md: Add clobber highs to tls_desc. gcc/testsuite/ * gcc.target/aarch64/sve_tls_preserve_1.c: New test. * gcc.target/aarch64/sve_tls_preserve_2.c: New test. * gcc.target

[PATCH v2 3/7] Add func to check if register is clobbered by clobber_high

Given a CLOBBER_HIGH expression and a register, it checks if the register will be clobbered. A second version exists for the cases where the expressions are not available. The function will be used throughout the following patches. 2018-07-25 Alan Hayward * rtl.h

[PATCH v2 4/7] lra support for clobber_high

The lra specific changes for clobber_high. 2018-07-25 Alan Hayward * lra-eliminations.c (lra_eliminate_regs_1): Check for clobber high. (mark_not_eliminable): Likewise. * lra-int.h (struct lra_insn_reg): Add clobber high marker. * lra-lives.c (process_bb_lives

[PATCH v2 2/7] Generation support for CLOBBER_HIGH

Ensure clobber high is a register expression. Info is passed through for the error case. 2018-07-25 Alan Hayward * emit-rtl.c (verify_rtx_sharing): Check for CLOBBER_HIGH. (copy_insn_1): Likewise. (gen_hard_reg_clobber_high): New gen function. * genconfig.c

[PATCH v2 5/7] cse support for clobber_high

The cse specific changes for clobber_high. 2018-07-25 Alan Hayward * cse.c (invalidate_reg): New function extracted from... (invalidate): ...here. (canonicalize_insn): Check for clobber high. (invalidate_from_clobbers): invalidate clobber highs

[PATCH v2 1/7] Add CLOBBER_HIGH expression

Includes documentation. 2018-07-25 Alan Hayward * doc/rtl.texi (clobber_high): Add. (parallel): Add in clobber high * rtl.c (rtl_check_failed_code3): Add function. * rtl.def (CLOBBER_HIGH): Add expression. * rtl.h (RTL_CHECKC3): Add macro

[PATCH v2 0/7] Support partial clobbers around TLS calls on Aarch64 SVE

. The next three patches add clobber high checks to all of the passes. I couldn't think of a better way of splitting this up (maybe needs dividing into smaller patches?). Finally the last patch adds the CLOBBER_HIGHS around a TLS call for aarch64 SVE and some test cases. Alan Hayward (7): Add

PING [PATCH v2 0/7] Support partial clobbers around TLS calls on Aarch64 SVE

> On 26 Jul 2018, at 10:13, Alan Hayward wrote: > > This is rebasing of the patch posted in November. > It's aim is to support aarch64 SVE register preservation around TLS calls > by adding a CLOBBER_HIGH expression. > > Across a TLS call, Aarch64 SVE does not explicit

Re: [PATCH 1/7]: SVE: Add CLOBBER_HIGH expression

, and this can’t go in until stage 1, I’m happy to leave the discussion until stage 1, but would appreciate any suggestions before then. Thanks, Alan. > On 12 Jan 2018, at 11:58, Alan Hayward <alan.hayw...@arm.com> wrote: > > > >> On 19 Dec 2017, at 16:27, Jeff Law <l...@redh

Re: [RFC] [Patch] [Debug] Add new NOTE to be used for debugging.

(Apologies this isn’t using the reply id) FYI, I tried the patch below and I’m happy it fixes the GDB issue in PR debug/88432. In the meantime, GDB HEAD has a workaround to disable stack protection in the GDB testsuite, and a KFAILed test for the exact bug. See: