Segher:
>
> From the GCC manual:
>
> -mmfcrfp4 2.01
> -mpopcntb p5 2.02
> -mfprndp5+ 2.04 ("info gcc" says 2.03, that's wrong? But the
> ISA
> says this is 2.02 even? Now what!)
> -mcmpb p6 2.05
> -mpopcntd p7 2.06
>
> (and there are more,
Bill:
On Wed, 2020-03-11 at 14:12 -0500, Bill Schmidt wrote:
> I believe you need %qs here. Also replace mno-fprnd with %qs and
> put
> "-mno-fprnd" as the associated parameter.
>
> Example from nearby code: error ("%qs requires %qs", "-mdirect-
> move",
> "-mvsx");
Yes. I had originally
GCC maintianers:
The following patch add a check to make sure the user did not specify
-mno_fprnd with the builtins __builtin_vsx_xsrdpim and
__builtin_vsx_xsrdpip. These builtins are incompatible with the
-mno_fprnd command line. The check prevents GCC crashing under these
conditions.
GCC maintainers:
This is a resend of "[PATCH]rs6000, fix vec_first_match_index for
nulls" from earlier today.
Per the received comments the pr number was added to the subject line.
I also tweaked the message to make it clear that the patch fixed issues
with vectors whose elements contain zeros
GCC maintainers:
The following is a trivial patch to fix a comment describing the
intrinsic function _mm_movemask_epi8. The comment was expanded to
clarify the layout of the returned result.
The patch does not make any functional changes.
Please let me know if the patch is OK for mainline
GCC maintainers:
This is a resend of "[PATCH]rs6000, fix vec_first_match_index for
nulls".
Per the received comments the pr number was added to the subject line.
I also tweaked the message to make it clear that the patch fixed issues
with vectors whose elements contain zeros rather then a zero
Segher:
>
> Yes, but only for this fprnd vs. 2.06 (vsx) situation. Like we
> already
> have:
>
> if (TARGET_DIRECT_MOVE && !TARGET_VSX)
> {
> if (rs6000_isa_flags_explicit & OPTION_MASK_DIRECT_MOVE)
> error ("%qs requires %qs", "-mdirect-move", "-mvsx");
>
GCC maintainers:
The following patch fixes PR94833, vec_first_match_index does not
function as described in its description.
The builtin does not handle vector elements which are zero correctly.
The following patch fixes the issue and adds additional test cases to
verify the
Will:
> That looks OK within this context.
>
> Are there any existing tests that use these named variations?
>
> Thanks,
> -Will
I was not able to find any test cases for these named builtins. I
fixed the other issues you mentioned in the message and patch below.
Carl
Will, Segher:
Patch 1, adds the 128-bit sign extension instruction support and
corresponding builtin support.
I updated the change log per the comments from Will.
Patch has been retested on Power 9 LE.
Pet me know if it is ready to commit to mainline.
Carl
Will, Segher:
Patch 4 adds the vector 128-bit integer shift instruction support for
the V1TI type.
The changes from the previous version include:
Fixed up the change log entry issues noted by Will.
Regression tests reran on Power 9 LE with no regression errors.
Please let me know if it looks
Will and Segher:
This is the rest of the second patch which adds the 128-bit integer
support for divide, modulo, shift, compare of 128-bit
integers instructions and builtin support.
In the last round of changes, the flag for the 128-bit operations was
removed. Per Will's comments, the
Will, Segher:
This patch adds support for converting to/from 128-bit integers and
128-bit decimal floating point formats using the new P10 instructions
dcffixqq and dctfixqq. The new instructions are only used on P10 HW,
otherwise the conversions continue to use the existing SW routines.
The
Will, Segher:
Add support for converting to/from 128-bit integers and 128-bit
decimal floating point formats.
The updates from the previous version of the patch:
Just a fix for the change log per Will's comments.
No regression failures were found when run on a P9.
Please let me know if this
Will, Segher:
The following changes were made from the previous version:
Per Will's comments, I split the bug fix from patch 2 into a separate
patch. This patch is the bug fix for the vec_rlnm builtin.
Regression tests reran on Power 9 LE with no regression errors.
Please let me know if it
Will, Segher:
This patch fixes an error in how the vec_rlnm() builtin parameters are
handled. The current test for this builtin are compile only. The
issue was found in the path that adds the 128-bit operands to the
vec_rlnm() builtin. The new test for the 128-bit operands is a compile
and run
Will, Segher:
This patch adds support for converting to/from 128-bit integers and
128-bit decimal floating point formats.
Updated ChangeLog comments. Fixed up comments in the test program.
Re-tested the patch on Power 9 with no regression errors.
Will, Segher:
This patch adds the 128-bit integer support for divide, modulo, shift,
compare of 128-bit integers instructions and builtin support.
Fixed the references to 128-bit in ChangeLog that got missed in the
last go round.
Fixed missing spaces in emit_insn calls.
Re-tested the patch on
Will, Segher:
Patch 4 adds the vector 128-bit integer shift instruction support for
the V1TI type.
This patch also renames and moves the VSX_TI iterator from vsx.md to
VEC_TI in vector.md. The uses of VEC_TI are also updated.
Re-tested the patch on Power 9 with no regression errors.
Will, Segher:
This patch adds support for converting to/from 128-bit integers and
128-bit decimal floating point formats using the new P10 instructions
dcffixqq and dctfixqq. The new instructions are only used on P10 HW,
otherwise the conversions continue to use the existing SW routines.
The
Will, Segher:
Patch 1, adds the 128-bit sign extension instruction support and
corresponding builtin support.
Removed the blank line per Will's latest feedback.
Retested the patch on Power 9 with no regression errors.
Carl
On Mon, 2020-10-12 at 15:43 -0500, Segher Boessenkool wrote:
> Hi!
>
> On Wed, Oct 07, 2020 at 04:08:12PM -0500, will schmidt wrote:
> > On Mon, 2020-10-05 at 11:51 -0700, Carl Love wrote:
> > > +/* Sign extend builtins that work on ISA 3.0, but not defined
> > > until ISA 3.1. */
> >
> > I
Bill:
On Mon, 2020-08-17 at 13:09 -0500, Bill Schmidt wrote:
> >
> > There are three prototypes __builtin_cfuged, __builtin_pdepd,
> > __builtin_pextd defined in the document.
> >
> > The corresponding builtin definitions in GCC are:
> >
> > __builtin_altivec_cfuged,
Segher:
On Wed, 2020-08-19 at 20:29 -0500, Segher Boessenkool wrote:
> Hi!
>
> On Tue, Aug 11, 2020 at 12:22:59PM -0700, Carl Love wrote:
> > +(define_insn "floattitd2"
> > + [(set (match_operand:TD 0 "gpc_reg_operand" "=d")
> > + (float:TD (match_operand:TI 1 "gpc_reg_operand" "v")))]
> > +
GCC maintainers:
The defines for vec_popcnt, bvec_popcnth, vec_popcntw, vec_popcntd in
gcc/config/rs6000/altivec.h are not listed in the Power 64-Bi ELF V2
ABI specification revision 1.4, May 10, 2017. They are not used by any
of the regression tests. They also do not work as reported in:
On Wed, 2020-08-19 at 15:16 -0500, Segher Boessenkool wrote:
> On Wed, Aug 19, 2020 at 02:19:12PM -0500, Peter Bergner wrote:
> > On 8/14/20 7:42 PM, Segher Boessenkool wrote:
> > > I think your current code is fine; I hadn't considered Bill's
> > > upcoming
> > > rewrite. It is more important to
Segher:
On Thu, 2020-08-20 at 16:50 -0500, Segher Boessenkool wrote:
> Hi!
>
> On Tue, Aug 11, 2020 at 12:23:05PM -0700, Carl Love wrote:
> > +;; 128-bit int modes
> > +(define_mode_iterator VEC_I128 [V1TI TI])
>
> We already have VSX_TI for this (in vsx.md). Rename that to
> something
>
GCC maintainers:
The following patch has been updated based on the comments from Will
and Segher.
The patch is a subset of the mainline commit:
commit
07d456bb80a16405723c98c2ab74ccc2a5a23898
Author: Carl Love
Segher:
On Wed, 2020-08-19 at 15:16 -0500, Segher Boessenkool wrote:
> On Wed, Aug 19, 2020 at 02:19:12PM -0500, Peter Bergner wrote:
> > On 8/14/20 7:42 PM, Segher Boessenkool wrote:
> > > I think your current code is fine; I hadn't considered Bill's
> > > upcoming
> > > rewrite. It is more
On Fri, 2020-08-14 at 16:33 -0500, Segher Boessenkool wrote:
> Hi Carl,
>
> On Thu, Aug 13, 2020 at 09:12:48AM -0700, Carl Love wrote:
> > The macro expansion for the bfloat convert intrinsics XVCVBF16SP
> > and
> > XVCVSPBF16 need to be restricted to P10.
> > The following patch creates new
Segher, Bill, Peter:
On Fri, 2020-08-14 at 19:42 -0500, Segher Boessenkool wrote:
> > > Do the names agree with the (future) documentation now?
> >
> > Did not double check on the documentation.
>
> Someone should...
Looking at the box document "Proposed function Prototypes for P10".
There
Segher, Will:
Add support for converting to/from 128-bit integers and 128-bit
decimal floating point formats.
The updates from the previous version of the patch:
Removed stray ";; carll" comment.
Removed #if 1 and #endif in the test case.
Replaced TARGET_TI_VECTOR_OPS with POWER10.
The
Segher, Will:
Patch 1, adds the 128-bit sign extension instruction support and
corresponding builtin support.
No changes from the previous version.
The patch has been tested on
powerpc64le-unknown-linux-gnu (Power 9 LE)
with no regression errors.
Fixed the issues in the ChangeLog noted by
Will, Segher:
Add support for divide, modulo, shift, compare of 128-bit
integers instructions and builtin support.
The following are the changes from the previous version of the patch.
The TARGET_TI_VECTOR_OPS was removed per comments for patch 3. Just
using TARGET_POWER10.
Removed extra
Segher, Will:
Patch 5 adds the 128-bit integer to/from 128-floating point
conversions. This patch has to invoke the routines to use the 128-bit
hardware instructions if on Power 10 or use software routines if
running on a pre Power 10 system via the resolve function.
Add ifunc resolves for
Segher, Will:
Patch 4 adds the vector 128-bit integer shift instruction support for
the V1TI type.
The following changes were made from the previous version.
Renamed VSX_TI to VEC_TI, put def in vector.md. Didn't get it
separated into a different patch.
Reworked the XXSWAPD_V1TI to not use
Will, Segher:
The following is the updated patch set for the 128-bit Binary Integer
Operation. I am reposting the entire set for completeness. I have
noted in each patch the changes made since the previous version.
The patches have been tested on Power 8 and Power 9 to ensure there are
no
GCC maintainers:
I have addressed the following comments on the patch from Will:
- ChangeLog: fixed name/symbol order;
changed reference from rs6000-c.c to rs6000-builtin.def.
- define_expand "vec_mtvsrbm": changed name to vec_mtvsrbm_mtvsrbmi,
updated comment.
-
GCC maintainers:
The following patch adds support for the vec_splati, vec_splatid and
vec_splati_ins builtins.
Note, this patch adds support for instructions that take a 32-bit
immediate
value that represents a floating point value. This support adds new
predicates and a support function to
GCC maintainers:
Move the existing vector extract support in altivec.md to vsx.md
so all of the vector insert and extract support is in the same file.
The patch also updates the name of the builtins and descriptions for the
builtins in the documentation file so they match the approved builtin
GCC maintainers:
The following patch adds support for the vec_blendv and vec_permx
builtins.
The patch has been compiled and tested on
powerpc64le-unknown-linux-gnu (Power 9 LE)
with no regression errors.
The test cases were compiled on a Power 9 system and then tested on
Mambo.
Please
GCC maintainers:
The following patch adds support for the vector shift double builtins
for RFC2609.
The patch has been compiled and tested on
powerpc64le-unknown-linux-gnu (Power 9 LE)
and Mambo with no regression errors.
Please let me know if this patch is acceptable for the mainline
GCC maintainers:
This patch adds support for vec_insertl and vec_inserth builtins.
The patch has been compiled and tested on
powerpc64le-unknown-linux-gnu (Power 9 LE)
and mambo with no regression errors.
Please let me know if this patch is acceptable for the mainline branch.
Thanks.
GCC maintainers:
The following patch adds support for builtins vec_replace_elt and
vec_replace_unaligned.
The patch has been compiled and tested on
powerpc64le-unknown-linux-gnu (Power 9 LE)
and mambo with no regression errors.
Please let me know if this patch is acceptable for the
GCC maintianers:
The following patch set adds builtins for the various Permute Class
Operations specified in IBM RFC 2609.
Based on previous IBM internal reviews of the patch set, the desire is
for all of the vector insert and extract support to be in vsx.md as
there is a longer term plan to
GCC maintainers:
The following patch adds support for builtins vec_genbm(), vec_genhm(),
vec_genwm(), vec_gendm(), vec_genqm(), vec_cntm(), vec_expandm(),
vec_extractm(). Support for instructions mtvsrbm, mtvsrhm, mtvsrwm,
mtvsrdm, mtvsrqm, cntm, vexpandm, vextractm.
The test has been tested
Gcc maintainers:
The following patch adds support for the built-ins listed in Table B.1,
"Binary-Coded Decimal Built-In Functions" of the "64-Bit ELF V2 ABI
Specification", July 30, 2019.
The built-ins adds support the V16QI type for addition, subtraction and
comparison as sepcified in the
GCC maintainers:
The following patch fixes a few issues with the tests. The DEBUG is
defined in each of the files thus the #ifdef DEBUG should just be #if
DEBUG. The other issue is a some of the line lengths for the error
prints exceed 80 characters. The patch fixes the prints.
The patch was
[PATCH 6/6] rs6000 Add vector blend, permute builtin support
--
V5 fixes:
Update ChangeLog
gcc/config/rs6000/rs6000-c.c:
Reworked
else if ((fcode == P10_BUILTIN_VEC_XXEVAL)|| (fcode ==
P10_BUILTIN_VXXPERMX))
to make error printing more
Segher:
I fixed the comments to patch 5 in the series. Patch 6 has yet to be
reviewed. I made all the minor changes to patches 1 to 4 that you and
Will mentioned. Those patches were approved with the minor changes so
I will not bother to repost them. I will just be reposting patches 5
and 6.
On Tue, 2020-07-21 at 10:27 -0700, Carl Love wrote:
>
Patch didn't seem to come thru.
-
>From d2d534d7b4a0caf77d362094ca8e3b53559ce80f Mon Sep 17 00:00:00 2001
From: Carl Love
Date: Wed, 27 May 2020 10:07:44 -0500
Subject: [PATCH 5/6] rs6000, Add vector
Segher:
The following is a five patch series for the 128-bit Binary Integer
Operations (RFC 2608).
The last patch does the 128-bit integer to 128-bit float to/from
conversions. The patch has been reviewed by Michael Meissner to make
sure the Floating point 128-mode handling is correct.
The
Segher, Will:
Patch 4 adds 128-bit integer shift instruction support.
Carl Love
-
Test 128-bit shifts for just the int128 type.
gcc/ChangeLog
2020-08-10 Carl Love
* config/rs6000/altivec.md (altivec_vslq,
Segher, Will:
Patch 5 adds the 128-bit integer to/from 128-floating point
conversions. This patch has to invoke the routines to use the 128-bit
hardware instructions if on Power 10 or use software routines if
running on a pre Power 10 system via the resolve function.
Segher, Will:
Patch 2, adds support for divide, modulo, shift, compare of 128-bit
integers. The support adds the instruction and builtin support.
Carl Love
---
rs6000, 128-bit multiply, divide, shift, compare
gcc/ChangeLog
Segher, Will:
Patch 1, adds the sign extension instruction support and corresponding
builtins.
Carl Love
-
RS6000 Add 128-bit sign extension support
gcc/ChangeLog
2020-08-10 Carl Love
*
Segher, Will:
Path 3 adds support for converting to/from 128-bit integers and 128-bit
decimal floating point formats.
Carl Love
Add TI to TD (128-bit DFP) and TD to TI support
gcc/ChangeLog
2020-08-10 Carl
Segher:
On Thu, 2020-08-13 at 12:36 -0500, Segher Boessenkool wrote:
> Hi!
>
> On Tue, Aug 11, 2020 at 12:22:37PM -0700, Carl Love wrote:
> > +/* Sign extend builtins that work on ISA 3.0, but not defined
> > until ISA 3.1. */
>
> What does this mean? Not defined in GCC before now? Does it
GCC maintainers:
The macro expansion for the bfloat convert intrinsics XVCVBF16SP and
XVCVSPBF16 need to be restricted to P10.
The macro expansions BU_P10V_0, BU_P10V_1, BU_P10V_2, BU_P10V_3 expand
the name field as "__builtin_altivec_". These macro expansions are
being used for both VSX and
Bill:
On Thu, 2020-08-13 at 14:48 -0500, Bill Schmidt wrote:
> OK, but that was just meant as an example. We have a fair number of
> things that changed names, so I was somewhat surprised. It could be
> that all of these are likewise hidden via the overload mechanism.
> Just
> checking to
Bill:
On Thu, 2020-08-13 at 13:38 -0500, Bill Schmidt wrote:
> Hi Carl,
>
> Thanks for cleaning up the consistency issue. The new names and
> related
> adjustments LGTM.
>
> Are there no affected test cases that need adjusting? That
> surprises
> me. For example, didn't
On Wed, 2020-07-01 at 12:00 -0500, Segher Boessenkool wrote:
> Hi!
>
> On Mon, Jun 29, 2020 at 03:31:48PM -0700, Carl Love wrote:
> > On Mon, 2020-06-29 at 16:58 -0500, Segher Boessenkool wrote:
> > > On Mon, Jun 29, 2020 at 02:29:54PM -0700, Carl Love wrote:
> > > > Segher:
> > > >
> > > > On
Segher:
I have fixed the issues you mentioned in version 2. I also rebased the
patch onto the latest mainline. This resulted in having to change
FUTURE to P10 everywhere.
I reran regression testing on Power 9 with no regression issues.
I also ran test cases manually on mambo.
Please let me
Will, Segher:
I fixed up the patch based on Will's comments. I thought I had made
and committed the fixes that Will caught, but no Sorry about
that. I will get this right yet.
Carl Love
---
Version 4
vec_mtvsrbm
[PATCH 4/6] rs6000, Add vector shift double builtin support
--
V4 Fixes:
Rebased on mainline. Changed FUTURE to P10.
Changed SLDB_LR to SLDB_lr
Changed error ("argument 3 must be in the range 0 to 7"); to
error ("argument 3 must be a constant in
[PATCH 3/6] rs6000, Add vector replace builtin support
--
V4 Fixes:
Rebased on mainline. Changed FUTURE to P10 in code and ChangeLog.
Set DEBUG to 0 in vec-replace-word-runnable.c test program.
Fixed too long lines in ChangeLog.
[PATCH 1/6] rs6000, Update support for vec_extract
-
V4 changes
rebased onto mainline 7/2/2020
Add iterator name to Change log
---
V3 changes
Redo ChangeLog for code move.
Replace spaces with tabs in ChangeLog.
Replaced
[PATCH 2/6] rs6000 Add vector insert builtin support
V4 changes
Rebased on mainline. Changed FUTURE to P10 as needed.
V3 changes
Replace spaces with of tabs in ChangeLog
Ditto in gcc/config/rs6000/vsx.md.
Updated
[PATCH 6/6] rs6000 Add vector blend, permute builtin support
--
V4 Fixes:
Rebased on mainline. Changed FUTURE to P10.
-
v3 fixes:
Replace spaces with tabs in ChangeLog description.
Fix implementation comments for define_expand "xxpermx" in file
Segher:
The following is version 4 of the series of patches for the permute
class operations. Per your request, I will send each patch as a reply
to this message so they are all in the same thread in your email box.
Patches 1, 2,3 and 4 just have minor fixes per your earlier comments.
[PATCH 5/6] rs6000, Add vector splat builtin support
--
V4 Fixes:
Rebased on mainline. Changed FUTURE to P10.
define_predicate "s32bit_cint_operand" removed unnecessary cast in
definition.
Changed define_expand "xxsplti32dx_v4si" to use "0" for
On Mon, 2020-06-29 at 16:58 -0500, Segher Boessenkool wrote:
> On Mon, Jun 29, 2020 at 02:29:54PM -0700, Carl Love wrote:
> > Segher:
> >
> > On Thu, 2020-06-25 at 17:39 -0500, Segher Boessenkool wrote:
> > > > +;; Return 1 if op is a constant 32-bit floating point value
> > > >
Segher:
On Thu, 2020-06-25 at 17:39 -0500, Segher Boessenkool wrote:
> > +;; Return 1 if op is a constant 32-bit floating point value
> > +(define_predicate "f32bit_const_operand"
> > + (match_code "const_double")
> > +{
> > + if (GET_MODE (op) == SFmode)
> > +return 1;
> > +
> > + else if
Will:
>
> >
> > @@ -5701,3 +5716,55 @@
> >"TARGET_POWER10"
> >" %x0,%x1"
> >[(set_attr "type" "vecfloat")])
> > +
> > +;; VSX mask manipulation instructions
> > +;;;(define_expand "vec_mtvsrbm"
> > +;;; [(set (match_operand:V16QI 0 "altivec_register_operand" "=v")
> > +;;;
v2 changes
Fix change log entry for config/rs6000/altivec.h
Fix change log entry for config/rs6000/rs6000-builtin.def
Fix change log entry for config/rs6000/rs6000-call.c
vsx.md: Fixed if (BYTES_BIG_ENDIAN) else statements.
Porting error from pu branch.
v2 changes
config/rs6000/altivec.md log entry for move from changed as suggested.
config/rs6000/vsx.md log entro for moved to here changed as suggested.
define_mode_iterator VI2 also moved, included in both change log entries
GCC maintainers:
Version 2. The patches in this series have been updated per the
comments from Segher. I have put at the top of each patch a short
summary of the version 2 changes. Hopefully the summaries will make
the re-review easier and faster. Most of the changes were ChangeLog
fixes with a few
v2 fixes:
change log entries config/rs6000/vsx.md, config/rs6000/rs6000-builtin.def,
config/rs6000/rs6000-call.c.
gcc/config/rs6000/rs6000-call.c: fixed if check for 3rd arg between 0 and 3
fixed if check for 3rd arg between 0 and 12
gcc/config/rs6000/vsx.md:
v2 changes:
Updated ChangeLog per comments.
define_expand "xxpermx", Updated implementation to use XOR
(icode == CODE_FOR_xxpermx, fix comments and check for 3-bit immediate
field.
gcc/doc/extend.texi:
comment "Maybe it should say it is related to vsel/xxsel,
v2 fixes:
change logs redone
gcc/config/rs6000/rs6000-call.c - added spaces before parenthesis around args.
-
GCC maintainers:
The following patch adds support for the vector shift double builtins
for RFC2609.
The patch has
v2 changes:
change log fixes
gcc/config/rs6000/altivec changed name of define_insn and define_expand
for vxxspltiw... to xxspltiw... Fixed spaces in gen_xxsplti32dx_v4sf_inst
(operands[0], GEN_INT
gcc/rs6000-builtin.def propagated name changes above where they are used.
V3 fixes:
Fixed bad word breaks in ChangLog.
Replace spaces with tabs in ChangeLog.
v2 fixes:
change log entries config/rs6000/vsx.md, config/rs6000/rs6000-builtin.def,
config/rs6000/rs6000-call.c.
gcc/config/rs6000/rs6000-call.c: fixed if check for
V3 Fixes
Replace spaces with tabs in ChangeLog.
Minor edits to ChangeLog entry.
Minor edits to vec_sldb description in gcc/doc/extend.texi.
v2 fixes:
change logs redone
gcc/config/rs6000/rs6000-call.c - added spaces
V3 changes
Replace spaces with of tabs in ChangeLog
Ditto in gcc/config/rs6000/vsx.md.
Updated description for vec_insertl() builtin.
Cleaned up vec_insert description.
-
v2 changes
Fix change log entry for
Version 3. Updated the patches based on the comments from Will. The
changes were primarily formatting and cleaning up comments and the
documentation.
-
Version 2. The patches in this series have been updated per the
comments from Segher. I have put at the top of
V3 changes
Redo ChangeLog for code move.
Replace spaces with tabs in ChangeLog.
Replaced intruction names using * with the actual list of names. For
example vextdu*vrx with the explicit instruction names vextdubvrx,
vextduhvrx, etc.
-
v2 changes
v3 fixes:
Replace spaces with tabs in ChangeLog description.
Fix implementation comments for define_expand "xxpermx" in file
gcc/config/rs6000/alitvec.md.
Fix minor typos in the comments for the changes in
gcc/config/rs6000/rs6000-call.c.
v2 changes:
v3 fixes:
Minor cleanup in the ChangeLog description.
-
v2 fixes:
change log fixes
gcc/config/rs6000/altivec changed name of define_insn and define_expand
for vxxspltiw... to xxspltiw... Fixed spaces in gen_xxsplti32dx_v4sf_inst
Segher:
So I have been looking at the predicate definitions that I had created.
On Fri, 2020-06-05 at 16:28 -0500, Segher Boessenkool wrote:
> > +;; Return 1 if op is a 32-bit constant signed integer
> > +(define_predicate "s32bit_cint_operand"
> > + (and (match_code "const_int")
> > +
Segher, Bill:
I committed this patch to mainline and backported to GCC 9.
I have looked at GCC 8. The functional issue is there, i.e. the
vcmpnez is used instead of vcmpne. However the test case
builtins-8-p9-runnable.c does not exist in GCC 8. The patch consists
of the functional fix:
On Wed, 2020-06-10 at 10:46 -0500, will schmidt wrote:
> > On Fri, 2020-06-05 at 16:28 -0500, Segher Boessenkool wrote:
> > > > +;; Return 1 if op is a 32-bit constant signed integer
> > > > +(define_predicate "s32bit_cint_operand"
> > > > + (and (match_code "const_int")
> > > > +
Segher, Pat:
I have updated the patch to address the comments below.
On Wed, 2020-11-25 at 20:30 -0600, Segher Boessenkool wrote:
> On Tue, Nov 24, 2020 at 08:34:51PM -0600, Pat Haugen wrote:
> > On 11/24/20 8:17 PM, Pat Haugen via Gcc-patches wrote:
> > > On 11/24/20 12:59 PM,
Will:
I have addressed you comments with regards to the Change Log entries.
The extra define vec_div was removed.
Added the missing entries for DIVU_V2DI DIVS_V2DI in rs6000-call.c.
The extra MULLD_V2DI case statement entry was removed.
Added comment in rs6000.md about size for vector
Segher:
I have addressed the various issues you and Pat mentioned.
Specifically:
- Added parenthesis around the macro arguments in altivec.h.
- Removed VIlong_char, using instead.
- Reimplemented define_insn "vmulhs_" and define_insn
"vmulhs_" to not use an UNSPEC. Also changed the
David:
>
> Hi, Carl
>
> I thought that vector.md was a transfer vector for the patterns and
> instructions were defined in vsx.md. Why are the new insn patterns
> defined in vector.md?
I am a bit of a newbie here. I wasn't aware of any specific guide
lines on the vector instructions. I put
David:
On Sat, 2020-10-24 at 11:29 -0400, David Edelsohn wrote:
> Hi, Carl
>
> Not commenting on the implementation.
>
> Please stop using powerpc*-*-* in the test cases. The test cases
> already are in the gcc.target/powerpc directory.
>
> Do the test cases really need lp64, or should this
David:
On Wed, 2020-10-28 at 20:43 -0400, David Edelsohn wrote:
> Better, but please use
>
> /* { dg-require-effective-target int128 } */
>
> not "target int128" in the selector. Segher and I both agree that
> it's cleaner and more readable. The selector (the target part on the
> dg-do line)
On Fri, 2020-10-30 at 17:05 -0400, David Edelsohn wrote:
> On Fri, Oct 30, 2020 at 4:07 PM Carl Love wrote:
>
> > diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-1-p10-
> > runnable.c b/gcc/testsuite/gcc.target/powerpc/builtins-1-p10-
> > runnable.c
> > new file mode 100644
> > index
GCC maintainers:
The following patch adds new builtins for the vector integer multiply,
divide and modulo operations. The builtins are:
vec_mulh(), vec_div(), vec_dive(), vec_mod() for signed and unsigned
integers and long long integers. Support for signed and unsigned long
long integers the
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