Michael,
Thanks for reviewing the patch and all the suggestions.
I have some questions / comments bellow.
Regards,
Edmar
On 05/17/2012 06:16 PM, Michael Meissner wrote:
In the patch I minimized the number of changes, while not adding
any new mask to target_flags.
While we may get some bits
will hold until we have a formal
ISA-2.07 document, and we are sure there is no conflict with the patch.
- The rest that will be kept by Freescale.
Thanks,
Edmar
On 05/21/2012 02:51 PM, David Edelsohn wrote:
Regarding the implementation of popcntb, popcntd, and cmpb. Gcc has
dedicated masks
I have just committed the patch below to add myself to the
write-after-approval section of the MAINTAINERS file.
Thanks,
Edmar
ChangeLog:
2012-05-29 Edmar Wienskoskied...@freescale.com
* MAINTAINERS (Write After Approval): Add myself.
Index: MAINTAINERS
was regression tested for ppc64 target under these conditions:
--enable-checking --disable-decimal-float --enable-languages=all
svn revision number: 187734
We thank in advance for your time to review this patch.
Regards,
Edmar
2012-06-01 Edmar Wienskoskied...@freescale.com
* config/rs6000
for powerpc64 target.
Thanks
Edmar
The patch I submitted had an omission. I failed to regenerate
rs6000-tables.opt
(Sorry, I misunderstood gcc_update --touch instructions)
OK to commit the update ?
2012-06-05 Edmar Wienskoski ed...@freescale.com
* config/rs6000/rs6000-tables.opt: Regenerated.
On 06/04/2012 08:45 PM
.
- power6.md has different style. Created a separate reservation.
I used instruction latency of 1. Please confirm.
I did not added a store bypass either. Let me know if I should.
Thanks,
Edmar
2012-06-05 Edmar Wienskoski ed...@freescale.com
* config/rs6000/rs6000.md (define_attr type
parts exclusively.
I am posting it as Michael manifested interest to have popcnt
scheduling control for those IBM parts, and this happened while he was
reviewing my E5500/E6500 patch.
I understand if this patch still not right. I just don't want
to leave a wrong impression.
Thanks,
Edmar
simplification possible, and the compiler always
produces
a nand instruction.
The formula is equal to y (y-1) , maybe the testcase is testing that?
Segher
Ah, yes
A neg/nand/and should be optimized into a sub -1/and.
I will check why this is not happening.
Thanks
Edmar
of the solution is acceptable, I would like to
have it re-tested with the latest in 4.4/4.5/4.6/4.7 and get it committed
in all branches.
Thanks
Edmar
2010-06-21 Edmar Wienskoski ed...@freescale.com
* rs6000.md (save_gpregs_mode): Replaced pattern with a set
of similar patterns
This time I put them in a tar file, to make sure the mail client don't
mess with them.
(ChangeLog is already inside the patch as well)
After I complete the regression tests, I will post a new version against
latest
subversion revision. Will post it here and on bugzilla.
Thanks,
Edmar
On 05
The patch gcc.fix_rnreg4 applies directly to 4.6, 4.7 (1 line offset),
and 4.5 (-632 lines offset)
Thanks,
Edmar
2011-05-23 Edmar Wienskoski ed...@freescale.com
* gcc.target/powerpc/outofline_rnreg.c: New testcase.
2011-05-23 Edmar Wienskoski ed...@freescale.com
* rs6000.md
I am pinging this post:
http://gcc.gnu.org/ml/gcc-patches/2012-03/msg00430.html
Thanks
Edmar
Committed on trunk, revision 213596
Committed on 4.9 branch, revision 213597
I made an omission on the first commit. I did not add
the test case and corresponding ChangeLog entry.
Committed as obvious on trunk, revision 213598
Thanks
Edmar
On 08/04/2014 05:25 AM, Ulrich Weigand wrote:
David
Jackub,
Thanks for point this up.
I apologize for the sloppiness.
I fixed and committed the ChangeLogs on the branch, revision 213639
Also fixed the libgcc ChangeLog on trunk. Revision 213640
Edmar
On 08/05/2014 03:11 AM, Jakub Jelinek wrote:
On Mon, Aug 04, 2014 at 11:51:34AM -0500, Edmar
Alan,
The first hunk will match powerpc64 as well.
Edmar
On Thu, May 9, 2013 at 2:27 AM, Alan Modra amo...@gmail.com wrote:
Another tweak for little-endian powerpc. Committed revision 198734.
* configure.ac (HAVE_AS_TLS): Enable tests for powerpcle and
powerpc64le
The e500v2 (SPE) hardware is such that if the address of vector (double world
load / stores) are not double world aligned the instruction will trap.
So this alignment is not optional.
Edmar
On Fri, Jun 7, 2013 at 3:43 PM, Richard Henderson r...@redhat.com wrote:
On 06/07/2013 12:25 PM, Jakub
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