On Thu, Jul 28, 2022 at 9:31 AM H.J. Lu wrote:
>
> On Thu, Jul 28, 2022 at 1:26 AM Alexandre Oliva wrote:
> >
> > On Jul 27, 2022, "H.J. Lu" wrote:
> >
> > > On Tue, Jul 26, 2022 at 10:14 PM Alexandre Oliva
> > > wrote:
> >
> >
therefore requires additional (unexpected) tweaking. Many
> thanks to H.J. Lu for pointing out timode_remove_non_convertible_regs
> needs to be extended to handle XOR (and other new operations).
>
> Unhelpfully the comment above this function states that it's the TImode
> versio
On Thu, Jul 28, 2022 at 1:26 AM Alexandre Oliva wrote:
>
> On Jul 27, 2022, "H.J. Lu" wrote:
>
> > On Tue, Jul 26, 2022 at 10:14 PM Alexandre Oliva wrote:
>
> >> The use of @GOTOFF for locally-bound but externally-visible symbols
> >> (e.g. prot
On Thu, Jul 21, 2022 at 11:53 AM H.J. Lu wrote:
>
> We can't always use the PLT entry as the function address for local IFUNC
> functions. When the PIC register is needed for PLT call, indirect call
> via the PLT entry will fail since the PIC register may not be set up
> proper
On Tue, Jul 26, 2022 at 10:14 PM Alexandre Oliva wrote:
>
>
> g++.dg/ext/attr-ifunc-3.C and gcc.target/i386/mvc10.c, not changed,
> have made it clear that there were problems in the optimizations to
> use @GOTOFF to refer to locally-bound ifuncs. GNU ld as recently as
> May 2018 would reject
On Fri, Jul 1, 2022 at 8:31 AM Uros Bizjak wrote:
>
> On Thu, Jun 30, 2022 at 4:50 PM H.J. Lu wrote:
> >
> > 1. Add a predicate for constant vectors which can be converted to integer
> > constants suitable for constant integer stores. For a 8-byte constant
> >
On Fri, Jul 22, 2022 at 11:10 PM Richard Biener via Gcc-patches
wrote:
>
>
>
> > Am 22.07.2022 um 22:17 schrieb H.J. Lu via Gcc-patches
> > :
> >
> > On Thu, Jul 21, 2022 at 4:24 AM Richard Biener via Gcc-patches
> > wrote:
> >>
> >
On Thu, Jul 21, 2022 at 4:24 AM Richard Biener via Gcc-patches
wrote:
>
> The following makes sure to fold ~(a ^ b) to a == b for truth
> values (but not vectors, we'd have to check for vector support of
> equality). That turns the PR106379 testcase into a ranger one.
>
> Note that while we
We can't always use the PLT entry as the function address for local IFUNC
functions. When the PIC register is needed for PLT call, indirect call
via the PLT entry will fail since the PIC register may not be set up
properly for indirect call. Add ix86_ifunc_ref_local_ok to return false
when the
Check stack canary for noreturn function to catch stack corruption
before calling noreturn function. For C++, check stack canary when
throwing exception or resuming stack unwind to avoid corrupted stack.
gcc/
PR middle-end/58245
* calls.cc (expand_call): Check stack canary for
On Wed, Jul 13, 2022 at 11:42 PM Richard Biener
wrote:
>
> On Wed, Jul 13, 2022 at 6:50 PM H.J. Lu wrote:
> >
> > When memchr is applied on a constant string of no more than the bytes of
> > a word, simplify memchr by checking each byte in the constant st
When shadow stack is enabled, function with indirect_return attribute
may return via indirect jump. In this case, we need to disable sibcall
if caller doesn't have indirect_return attribute and indirect branch
tracking is enabled since compiler won't generate ENDBR when calling the
caller.
gcc/
On Wed, Jul 13, 2022 at 5:35 AM Richard Biener
wrote:
>
> On Tue, Jul 12, 2022 at 6:59 PM H.J. Lu wrote:
> >
> > On Fri, Jul 8, 2022 at 5:54 AM Richard Biener
> > wrote:
> > >
> > > On Thu, Jul 7, 2022 at 6:45 PM H.J. Lu wrote:
> > > &g
When memchr is applied on a constant string of no more than the bytes of
a word, simplify memchr by checking each byte in the constant string.
int f (int a)
{
return __builtin_memchr ("AE", a, 2) != 0;
}
is simplified to
int f (int a)
{
return ((char) a == 'A' || (char) a == 'E') != 0;
}
On Fri, Jul 8, 2022 at 5:54 AM Richard Biener
wrote:
>
> On Thu, Jul 7, 2022 at 6:45 PM H.J. Lu wrote:
> >
> > When memchr is applied on a constant string of no more than the bytes of
> > a word, simplify memchr by checking each byte in the constant st
(mostly).
You are probably right. If there are no regressions in GCC testsuite,
my original motivation is no longer valid.
Thanks.
> Cheers,
> Roger
> --
>
> > -Original Message-
> > From: H.J. Lu
> > Sent: 10 July 2022 20:15
> > To: Roger Sayle
>
On Sun, Jul 10, 2022 at 11:36 AM Roger Sayle wrote:
>
>
> Hi Uros,
> Yes, I agree. I think it makes sense to have a single STV pass (after
> combine and before reload). Let's hear what HJ thinks, but I'm
> happy to investigate a follow-up patch that unifies the STV passes.
> But it'll be easier
On Thu, Jun 23, 2022 at 9:26 AM H.J. Lu wrote:
>
> On Wed, Jun 22, 2022 at 11:03 PM Richard Biener
> wrote:
> >
> > On Wed, Jun 22, 2022 at 7:13 PM H.J. Lu wrote:
> > >
> > > On Wed, Jun 22, 2022 at 4:39 AM Richard Biener
> > > wrote:
> >
When memchr is applied on a constant string of no more than the bytes of
a word, simplify memchr by checking each byte in the constant string.
int f (int a)
{
return __builtin_memchr ("AE", a, 2) != 0;
}
is simplified to
int f (int a)
{
return ((char) a == 'A' || (char) a == 'E') != 0;
}
On Fri, Jul 1, 2022 at 12:51 AM Richard Biener
wrote:
>
> On Mon, Jun 20, 2022 at 5:44 PM H.J. Lu wrote:
> >
> > extern int __memcmpeq (const void *, const void *, size_t);
> >
> > was was added to GLIBC 2.35. Expand BUILT_IN_MEMCMP_EQ to __memcmpeq
> > after
extern int __memcmpeq (const void *, const void *, size_t);
was was added to GLIBC 2.35. Expand BUILT_IN_MEMCMP_EQ to __memcmpeq
after seeing __memcmpeq prototype
gcc/
* builtins.cc (expand_builtin): Issue an error for
BUILT_IN___MEMCMPEQ if there is no __memcmpeq prototype.
1. Add a predicate for constant vectors which can be converted to integer
constants suitable for constant integer stores. For a 8-byte constant
vector, the converted 64-bit integer must be valid for store with 64-bit
immediate, which is a 64-bit integer sign-extended from a 32-bit integer.
2. Add
On Sun, Jun 26, 2022 at 10:50 PM Hongtao Liu wrote:
>
> On Tue, Jun 21, 2022 at 3:50 AM Uros Bizjak via Gcc-patches
> wrote:
> >
> > On Mon, Jun 20, 2022 at 8:14 PM H.J. Lu wrote:
> > >
> > > On Tue, May 10, 2022 at 9:25 AM H.J. Lu
On Wed, Jun 22, 2022 at 11:03 PM Richard Biener
wrote:
>
> On Wed, Jun 22, 2022 at 7:13 PM H.J. Lu wrote:
> >
> > On Wed, Jun 22, 2022 at 4:39 AM Richard Biener
> > wrote:
> > >
> > > On Tue, Jun 21, 2022 at 11:03 PM H.J. Lu via Gcc-patches
> >
On Wed, Jun 22, 2022 at 4:39 AM Richard Biener
wrote:
>
> On Tue, Jun 21, 2022 at 11:03 PM H.J. Lu via Gcc-patches
> wrote:
> >
> > When memchr is applied on a constant string of no more than the bytes of
> > a word, inline memchr by checking each byte in the constant
When memchr is applied on a constant string of no more than the bytes of
a word, inline memchr by checking each byte in the constant string.
int f (int a)
{
return __builtin_memchr ("eE", a, 2) != 0;
}
is simplified to
int f (int a)
{
return (char) a == 'e' || (char) a == 'E';
}
gcc/
On Mon, Jun 20, 2022 at 7:51 AM Uros Bizjak wrote:
>
> On Mon, Jun 20, 2022 at 4:03 PM H.J. Lu wrote:
> >
> > On Tue, Jun 14, 2022 at 12:25 PM H.J. Lu wrote:
> > >
> > > Disallow siball when calling ifunc functions with PIC register so that
> > >
On Tue, May 10, 2022 at 9:25 AM H.J. Lu wrote:
>
> Mark a function with SYMBOL_FLAG_FUNCTION_ENDBR when inserting ENDBR at
> function entry. Skip the 4-byte ENDBR when emitting a direct call/jmp
> to a local function with ENDBR at function entry.
>
> This has been tested on Lin
On Mon, Jun 20, 2022 at 10:29 AM Jakub Jelinek wrote:
>
> On Mon, Jun 20, 2022 at 09:35:36AM -0700, Noah Goldstein via Gcc-patches
> wrote:
> > This patch allows for strchr(x, c) to the replace with memchr(x, c,
> > strlen(x) + 1) if strlen(x) has already been computed earlier in the
> > tree.
>
On Mon, Jun 20, 2022 at 2:39 AM Richard Biener
wrote:
>
> On Thu, Jun 16, 2022 at 1:38 AM Fangrui Song wrote:
> >
> > On Wed, Jun 15, 2022 at 2:44 PM H.J. Lu via Gcc-patches
> > wrote:
> > >
> > > On Mon, Jun 13, 2022 at 9:01 AM Richard Biener
> >
extern int __memcmpeq (const void *, const void *, size_t);
was was added to GLIBC 2.35. Expand BUILT_IN_MEMCMP_EQ to __memcmpeq
after seeing __memcmpeq prototype
gcc/
* builtins.cc (have_memcmpeq_prototype): New.
(expand_builtin): Issue an error for BUILT_IN___MEMCMPEQ if
On Tue, Jun 14, 2022 at 12:25 PM H.J. Lu wrote:
>
> Disallow siball when calling ifunc functions with PIC register so that
> PIC register can be restored.
>
> gcc/
>
> PR target/105960
> * config/i386/i386.cc (ix86_function_ok_for_sibcall): Return
>
On Mon, Jun 13, 2022 at 9:01 AM Richard Biener
wrote:
>
>
>
> > Am 13.06.2022 um 16:36 schrieb H.J. Lu :
> >
> > On Mon, Jun 13, 2022 at 3:11 AM Richard Biener
> > wrote:
> >>
> >>> On Tue, Jun 7, 2022 at 9:02 PM H.J. Lu via Gcc-patch
Disallow siball when calling ifunc functions with PIC register so that
PIC register can be restored.
gcc/
PR target/105960
* config/i386/i386.cc (ix86_function_ok_for_sibcall): Return
false if PIC register is used when calling ifunc functions.
gcc/testsuite/
PR
On Mon, Jun 13, 2022 at 3:11 AM Richard Biener
wrote:
>
> On Tue, Jun 7, 2022 at 9:02 PM H.J. Lu via Gcc-patches
> wrote:
> >
> > Add -fextra-libc-function=memcmpeq to map
> >
> > extern int __memcmpeq (const void *, const void *, size_t);
>
Since F16C and VAES are only usable with AVX, require AVX for F16C and
VAES.
OK for master and release branches?
Thanks.
H.J.
---
libgcc/105920
* common/config/i386/cpuinfo.h (get_available_features): Require
AVX for F16C and VAES.
---
gcc/common/config/i386/cpuinfo.h |
On Fri, Jun 10, 2022 at 7:44 AM H.J. Lu wrote:
>
> On Fri, Jun 10, 2022 at 2:38 AM Florian Weimer wrote:
> >
> > * liuhongt via Libc-alpha:
> >
> > > +\subsubsection{Special Types}
> > > +
> > > +The \code{__Bfloat16} type uses a 8-bit expon
On Fri, Jun 10, 2022 at 2:38 AM Florian Weimer wrote:
>
> * liuhongt via Libc-alpha:
>
> > +\subsubsection{Special Types}
> > +
> > +The \code{__Bfloat16} type uses a 8-bit exponent and 7-bit mantissa.
> > +It is used for \code{BF16} related intrinsics, it cannot be
Please mention that this is
Add -fextra-libc-function=memcmpeq to map
extern int __memcmpeq (const void *, const void *, size_t);
which was added to GLIBC 2.35, to __builtin_memcmp_eq.
gcc/
* builtins.cc: Include "opts.h".
(expand_builtin): Generate BUILT_IN_MEMCMP_EQ if __memcmpeq is
available.
On Sun, Jun 5, 2022 at 7:27 PM Hongtao Liu via Gcc-patches
wrote:
>
> On Mon, Jun 6, 2022 at 3:17 AM Uros Bizjak via Gcc-patches
> wrote:
> >
> > On Thu, Jun 2, 2022 at 5:04 PM Jan Beulich wrote:
> > >
> > > The 64-bit, 128-bit, and 512-bit variants have VDI return type, in
> > > line with
On Fri, May 13, 2022 at 1:17 PM Philipp Tomsich
wrote:
>
> The Zbb support has introduced ctz and clz to the backend, but some
> transformations in GCC need to know what the value of c[lt]z at zero
> is. This affects how the optab is generated and may suppress use of
> CLZ/CTZ in tree passes.
>
>
On Wed, Jun 1, 2022 at 12:20 AM Richard Sandiford
wrote:
>
> "H.J. Lu" writes:
> > On Mon, May 30, 2022 at 09:35:43AM +0100, Richard Sandiford wrote:
> >> "H.J. Lu" writes:
> >> > ---
> >> > RTL DSE tracks redundant constant st
On Tue, May 31, 2022 at 10:06 PM Cui,Lili wrote:
>
> This patch is to update {skylake,icelake,alderlake}_cost to add a bit
> preference to vector store.
> Since the interger vector construction cost has changed, we need to adjust
> the load and store costs for intel processers.
>
> With the
On Mon, May 30, 2022 at 09:35:43AM +0100, Richard Sandiford wrote:
> "H.J. Lu" writes:
> > ---
> > RTL DSE tracks redundant constant stores within a basic block. When RTL
> > loop invariant motion hoists a constant initialization out of the loop
> > into
On Sat, May 28, 2022 at 11:37 AM Jeff Law via Gcc-patches
wrote:
>
>
>
> On 5/26/2022 2:43 PM, H.J. Lu via Gcc-patches wrote:
> > On Thu, May 26, 2022 at 04:14:17PM +0100, Richard Sandiford wrote:
> >> "H.J. Lu" writes:
> >>> On Wed, May 25
On Thu, May 26, 2022 at 04:14:17PM +0100, Richard Sandiford wrote:
> "H.J. Lu" writes:
> > On Wed, May 25, 2022 at 12:30 AM Richard Sandiford
> > wrote:
> >>
> >> "H.J. Lu via Gcc-patches" writes:
> >> > On Mon, May 23, 2022
On Wed, May 25, 2022 at 2:30 AM Richard Sandiford
wrote:
>
> Richard Biener via Gcc-patches writes:
> > On Tue, May 24, 2022 at 10:11 PM H.J. Lu wrote:
> >>
> >> On Mon, May 23, 2022 at 11:42 PM Richard Biener
> >> wrote:
> >> >
&g
On Wed, May 25, 2022 at 12:30 AM Richard Sandiford
wrote:
>
> "H.J. Lu via Gcc-patches" writes:
> > On Mon, May 23, 2022 at 12:38:06PM +0200, Richard Biener wrote:
> >> On Sat, May 21, 2022 at 5:02 AM H.J. Lu via Gcc-patches
> >> wrote:
> >>
On Mon, May 23, 2022 at 11:42 PM Richard Biener
wrote:
>
> On Mon, May 23, 2022 at 8:34 PM H.J. Lu wrote:
> >
> > On Mon, May 23, 2022 at 12:38:06PM +0200, Richard Biener wrote:
> > > On Sat, May 21, 2022 at 5:02 AM H.J. Lu via Gcc-patches
> > > wrote:
On Mon, May 23, 2022 at 12:38:06PM +0200, Richard Biener wrote:
> On Sat, May 21, 2022 at 5:02 AM H.J. Lu via Gcc-patches
> wrote:
> >
> > When recording store for RTL dead store elimination, check if the source
> > register is set only once to a constant. If
PR target/104441
* gcc.target/i386/pr104441-1a.c (load8bit_4x4_avx2): Initialize
src23.
---
gcc/testsuite/gcc.target/i386/pr104441-1a.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.target/i386/pr104441-1a.c
When -fcf-protection=branch is used, the compiler will generate jump
tables for switch statements where the indirect jump is prefixed with
the NOTRACK prefix, so it can jump to non-ENDBR targets. Since the
indirect jump targets are generated by the compiler and stored in
read-only memory, this
When recording store for RTL dead store elimination, check if the source
register is set only once to a constant. If yes, record the constant
as the store source. It eliminates unrolled zero stores after memset 0
in a loop where a vector register is used as the zero store source.
gcc/
On Thu, May 19, 2022 at 1:49 PM Florian Weimer wrote:
>
> * H. J. Lu:
>
> > How about this?
> >
> > @item -mcet-switch
> > @opindex mcet-switch
> > By default, CET instrumentation is turned off on switch statements that
> > use a jump table and indirect branch track is disabled.
>
> Maybe add
On Wed, May 18, 2022 at 11:02 PM Richard Biener
wrote:
>
> On Wed, May 18, 2022 at 7:32 PM H.J. Lu via Gcc-patches
> wrote:
> >
> > On Wed, May 11, 2022 at 1:52 PM H.J. Lu wrote:
> > >
> > > When -fcf-protection=branch is used, the compiler will generate
On Wed, May 11, 2022 at 1:52 PM H.J. Lu wrote:
>
> When -fcf-protection=branch is used, the compiler will generate jump
> tables for switch statements where the indirect jump is prefixed with
> the NOTRACK prefix, so it can jump to non-ENDBR targets. Since the
> indire
On Thu, May 12, 2022 at 12:15 AM Richard Biener
wrote:
>
> On Wed, May 11, 2022 at 9:03 PM Florian Weimer via Gcc-patches
> wrote:
> >
> > * H. J. Lu:
> >
> > > On Wed, May 11, 2022 at 11:45 AM Florian Weimer
> > > wrote:
> > >>
> > >> * H. J. Lu:
> > >>
> > >> >> NOTRACK avoids the need for
When -fcf-protection=branch is used, the compiler will generate jump
tables for switch statements where the indirect jump is prefixed with
the NOTRACK prefix, so it can jump to non-ENDBR targets. Since the
indirect jump targets are generated by the compiler, they are always
valid.
Document
On Wed, May 11, 2022 at 12:02 PM Florian Weimer wrote:
>
> * H. J. Lu:
>
> > On Wed, May 11, 2022 at 11:45 AM Florian Weimer wrote:
> >>
> >> * H. J. Lu:
> >>
> >> >> NOTRACK avoids the need for ENDBR instructions, right? That's a
> >> >> hardening improvement, so it should be used by default.
On Wed, May 11, 2022 at 11:45 AM Florian Weimer wrote:
>
> * H. J. Lu:
>
> >> NOTRACK avoids the need for ENDBR instructions, right? That's a
> >> hardening improvement, so it should be used by default.
> >
> > NOTRACK weakens IBT since it disables IBT on the indirect jump instruction.
> > GCC
On Wed, May 11, 2022 at 11:22 AM Florian Weimer wrote:
>
> * H. J. Lu:
>
> >> >> > Generate jump tables with ENDBR and skip the NOTRACK prefix for
> >> >> > indirect
> >> >> > jump. Document -mno-cet-switch to turn off CET instrumentation on
> >> >> > jump
> >> >> > tables for switch
On Wed, May 11, 2022 at 8:58 AM Florian Weimer wrote:
>
> * H. J. Lu:
>
> > On Wed, May 11, 2022 at 1:12 AM Florian Weimer wrote:
> >>
> >> * H. J. Lu via Gcc-patches:
> >>
> >> > When -fcf-protection=branch is used, the compiler will generate jump
> >> > tables where the indirect jump is
On Tue, May 10, 2022 at 11:39 PM Richard Biener wrote:
>
> On Tue, 10 May 2022, H.J. Lu wrote:
>
> > When compiling Linux kernel with -fcf-protection=branch to enable x86
> > Indiret Branch Tracking (IBT), ENDBR is added to all global functions.
> > This creates more
On Wed, May 11, 2022 at 1:12 AM Florian Weimer wrote:
>
> * H. J. Lu via Gcc-patches:
>
> > When -fcf-protection=branch is used, the compiler will generate jump
> > tables where the indirect jump is prefixed with the NOTRACK prefix, so
> > it can jump to non-ENDBR targets. Yet, for NOTRACK
On Thu, Apr 28, 2022 at 11:52 PM Richard Biener
wrote:
>
> On Thu, Apr 28, 2022 at 7:54 PM H.J. Lu wrote:
> >
> > On Thu, Apr 28, 2022 at 9:59 AM Jeff Law wrote:
> > >
> > >
> > >
> > > On 4/28/2022 10:27 AM, H.J. Lu wrote:
> >
When compiling Linux kernel with -fcf-protection=branch to enable x86
Indiret Branch Tracking (IBT), ENDBR is added to all global functions.
This creates more "legal" forward edges than necessary. -mmanual-endbr
provides a way to insert ENDBR instruction at function entry only via
the 'cf_check'
Mark a function with SYMBOL_FLAG_FUNCTION_ENDBR when inserting ENDBR at
function entry. Skip the 4-byte ENDBR when emitting a direct call/jmp
to a local function with ENDBR at function entry.
This has been tested on Linux kernel.
gcc/
PR target/102953
*
When -fcf-protection=branch is used, the compiler will generate jump
tables where the indirect jump is prefixed with the NOTRACK prefix, so
it can jump to non-ENDBR targets. Yet, for NOTRACK prefixes to work, the
NOTRACK specific enable bit must be set, what renders the binary broken
on any
On Mon, May 9, 2022 at 7:51 AM H.J. Lu wrote:
>
> Add .note.GNU-stack section only for Linux since it may not be supported
> on non-Linux OSes. __ELF__ isn't checked since these tests can only run
> on Linux/x86 ELF systems.
>
> PR target/105472
> * gcc.
Add .note.GNU-stack section only for Linux since it may not be supported
on non-Linux OSes. __ELF__ isn't checked since these tests can only run
on Linux/x86 ELF systems.
PR target/105472
* gcc.target/i386/iamcu/asm-support.S: Add .note.GNU-stack section
only for Linux.
On Mon, May 2, 2022 at 11:37 AM H.J. Lu wrote:
>
> On Fri, Apr 29, 2022 at 10:38 AM H.J. Lu wrote:
> >
> > Add .note.GNU-stack assembly source to avoid linker warning:
> >
> > ld: warning: /tmp/ccPZSZ7Z.o: missing .note.GNU-stack section implies
> > executabl
On Thu, May 5, 2022 at 2:02 PM H.J. Lu wrote:
>
> cherry-pick:
>
> b226894d475b [sanitizer] [sanitizer] Correct GetTls for x32
> ---
> libsanitizer/sanitizer_common/sanitizer_linux_libcdep.cpp | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/li
cherry-pick:
b226894d475b [sanitizer] [sanitizer] Correct GetTls for x32
---
libsanitizer/sanitizer_common/sanitizer_linux_libcdep.cpp | 4
1 file changed, 4 insertions(+)
diff --git a/libsanitizer/sanitizer_common/sanitizer_linux_libcdep.cpp
On Thu, May 5, 2022 at 11:28 AM Martin Liška wrote:
>
> On 5/5/22 18:21, H.J. Lu wrote:
> > On Thu, May 5, 2022 at 4:24 AM Martin Liška wrote:
> >>
> >> On 5/5/22 01:07, H.J. Lu wrote:
> >>> On Wed, May 4, 2022 at 1:59 AM Martin Liška wrote:
> >
On Thu, May 5, 2022 at 4:24 AM Martin Liška wrote:
>
> On 5/5/22 01:07, H.J. Lu wrote:
> > On Wed, May 4, 2022 at 1:59 AM Martin Liška wrote:
> >>
> >> Hello.
> >>
> >> I'm going to do merge from upstream.
> >>
> >> Patch can boot
x32
to restore x32 build.
--
H.J.
From ae90c2d0f9bcc30af98c730f91544efa01cb897c Mon Sep 17 00:00:00 2001
From: "H.J. Lu"
Date: Wed, 4 May 2022 15:59:49 -0700
Subject: [PATCH] libsanitizer: cherry-pick commit f52e365092aa from upstream
cherry-pick:
f52e365092aa [sanitizer] Use newfstatat for x32
---
libsaniti
On Fri, Apr 29, 2022 at 10:38 AM H.J. Lu wrote:
>
> Add .note.GNU-stack assembly source to avoid linker warning:
>
> ld: warning: /tmp/ccPZSZ7Z.o: missing .note.GNU-stack section implies
> executable stack
> ld: NOTE: This behaviour is deprecated and will be removed in a
Add .note.GNU-stack assembly source to avoid linker warning:
ld: warning: /tmp/ccPZSZ7Z.o: missing .note.GNU-stack section implies
executable stack
ld: NOTE: This behaviour is deprecated and will be removed in a future version
of the linker
FAIL:
On Thu, Apr 28, 2022 at 9:59 AM Jeff Law wrote:
>
>
>
> On 4/28/2022 10:27 AM, H.J. Lu wrote:
> > On Thu, Apr 28, 2022 at 9:10 AM Jeff Law via Gcc-patches
> > wrote:
> >> As I mentioned in the original thread, my change to pr94157_0 was an
> >> attempt
On Thu, Apr 28, 2022 at 9:10 AM Jeff Law via Gcc-patches
wrote:
>
> As I mentioned in the original thread, my change to pr94157_0 was an
> attempt to avoid these warnings by passing a magic flag to the linker.
> Of course we may not be using GNU ld. Or we may be on a non-elf target
> where the
On Mon, Mar 28, 2022 at 9:37 AM H.J. Lu wrote:
>
> PR target/105068
> * config/i386/sse.md (*ssse3_pshufbv8qi3): Also replace "Yv" with
> "Yw" in clobber.
> ---
> gcc/config/i386/sse.md | 2 +-
> 1 file changed, 1 insertion(+),
PR target/105068
* config/i386/sse.md (*ssse3_pshufbv8qi3): Also replace "Yv" with
"Yw" in clobber.
---
gcc/config/i386/sse.md | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 01543afd111..1f9c496e7c0
On Sun, Mar 27, 2022 at 11:35 AM Uros Bizjak wrote:
>
> On Sun, Mar 27, 2022 at 8:14 PM H.J. Lu wrote:
> >
> > Since AVX512VL and AVX512BW are required for AVX512 VPSHUFB, replace the
> > "Yv" register constraint with the "Yw" register constraint.
Since AVX512VL and AVX512BW are required for AVX512 VPSHUFB, replace the
"Yv" register constraint with the "Yw" register constraint.
gcc/
PR target/105068
* config/i386/sse.md (*ssse3_pshufbv8qi3): Replace "Yv" with
"Yw".
gcc/testsuite/
PR target/105068
test for this PR that produces xmm16-31?
> And the -ffix-xmmN is an option for assembler or compiler? I didn't
> find it in document.
You can add -march=skylake-avx512 -ffix-xmm0 ... -ffix-xmm15 to force
XMM16-XMM31.
> H.J. Lu 于2022年3月26日周六 09:22写道：
> >
> > On Fri, Mar 25, 2022 at 6:08
On Fri, Mar 25, 2022 at 6:08 PM Hongyu Wang wrote:
>
> Is it possible to create a test case that gas would throw an error for
> invalid operands?
You can use -ffix-xmmN to disable XMM0-15.
> H.J. Lu via Gcc-patches 于2022年3月26日周六 04:50写道：
> >
> > Since KL instruction
Replace -msse with -msse2 since requires SSE2.
PR testsuite/105055
* gcc.target/i386/pr95483-1.c: Replace -msse with -msse2.
---
gcc/testsuite/gcc.target/i386/pr95483-1.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Since KL instructions have no AVX512 version, replace the "v" register
constraint with the "x" register constraint.
PR target/105058
* config/i386/sse.md (loadiwkey): Replace "v" with "x".
(aesu8): Likewise.
---
gcc/config/i386/sse.md | 6 +++---
1 file changed, 3
Since PHADDW/PHADDD/PHADDSW/PHSUBW/PHSUBD/PHSUBSW/PSIGNB/PSIGNW/PSIGND
have no AVX512 version, replace the "Yv" register constraint with the
"x" register constraint.
PR target/105052
* config/i386/sse.md (ssse3_phwv4hi3):
Replace "Yv" with "x".
(ssse3_phdv2si3):
On Thu, Mar 17, 2022 at 8:05 AM H.J. Lu wrote:
>
> On Mon, Mar 14, 2022 at 7:31 AM H.J. Lu wrote:
> >
> > Push target("general-regs-only") in if x87 is enabled.
> >
> > gcc/
> >
> > PR target/104890
> > *
On Mon, Mar 21, 2022 at 2:59 PM Uros Bizjak wrote:
>
> On Mon, Mar 21, 2022 at 10:57 PM H.J. Lu wrote:
> >
> > On Mon, Mar 21, 2022 at 10:50:11PM +0100, Uros Bizjak wrote:
> > > On Mon, Mar 21, 2022 at 10:47 PM H.J. Lu wrote:
> > > >
> > > > On
On Mon, Mar 14, 2022 at 8:44 AM Richard Sandiford
wrote:
>
> Richard Biener writes:
> > On Wed, Mar 9, 2022 at 7:04 PM Richard Sandiford
> > wrote:
> >>
> >> Richard Biener via Gcc-patches writes:
> >> > On Wed, Mar 2, 2022 at 10:18 PM H.J. Lu w
On Mon, Mar 21, 2022 at 10:50:11PM +0100, Uros Bizjak wrote:
> On Mon, Mar 21, 2022 at 10:47 PM H.J. Lu wrote:
> >
> > On Mon, Mar 21, 2022 at 10:23:59PM +0100, Uros Bizjak wrote:
> > > On Mon, Mar 21, 2022 at 10:10 PM H.J. Lu wrote:
> > > >
> > >
On Mon, Mar 21, 2022 at 2:29 PM Uros Bizjak wrote:
>
> On Mon, Mar 21, 2022 at 2:56 PM H.J. Lu wrote:
> >
> > 1. Pass 0x19 to __cpuid for bit_AESKLE.
> > 2. Enable FEATURE_AESKLE only if bit_AESKLE is set.
> >
> > PR target/104998
> &
On Mon, Mar 21, 2022 at 10:23:59PM +0100, Uros Bizjak wrote:
> On Mon, Mar 21, 2022 at 10:10 PM H.J. Lu wrote:
> >
> > SSE and AVX ISAs in ISA2 should be disabled for -mgeneral-regs-only.
> >
> > gcc/
> >
> > PR target/105000
> >
SSE and AVX ISAs in ISA2 should be disabled for -mgeneral-regs-only.
gcc/
PR target/105000
* common/config/i386/i386-common.cc
(OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET): Also disable SSE
and AVX.
gcc/testsuite/
PR target/105000
*
x{-m32\
> -march=cascadelake}'"
> $ cd {build_dir}/gcc && make check
> RUNTESTFLAGS="i386.exp=gcc.target/i386/pr90356.c --target_board='unix{-m64\
> -march=cascadelake}'"
>
I am checking in this testcase fix.
--
H.J.
From 24722f23a9d6ac4fbc3694b92585db61
1. Pass 0x19 to __cpuid for bit_AESKLE.
2. Enable FEATURE_AESKLE only if bit_AESKLE is set.
PR target/104998
* common/config/i386/cpuinfo.h (get_available_features): Pass
0x19 to __cpuid for bit_AESKLE. Enable FEATURE_AESKLE only if
bit_AESKLE is set.
---
On Mon, Mar 14, 2022 at 7:31 AM H.J. Lu wrote:
>
> Push target("general-regs-only") in if x87 is enabled.
>
> gcc/
>
> PR target/104890
> * config/i386/x86gprintrin.h: Also check _SOFT_FLOAT before
> pushing target("general-regs-on
On Tue, Mar 15, 2022 at 6:57 PM Hongtao Liu wrote:
>
> On Tue, Mar 15, 2022 at 10:40 PM H.J. Lu wrote:
> >
> > On Mon, Mar 14, 2022 at 7:31 AM H.J. Lu wrote:
> > >
> > > Push target("general-regs-only") in if x87 is enabled.
> &g
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