[PATCH] [i386]Add combine splitter to transform vpcmpeqd/vpxor/vblendvps to vblendvps for ~op0

This patch adds combine splitter to transform vpcmpeqd/vpxor/vblendvps to vblendvps for ~op0. OK for trunk? BRs, Haochen gcc/ChangeLog: PR target/100738 * config/i386/sse.md (*_blendv_not_ltint): Add new define_insn_and_split. gcc/testsuite/ChangeLog: PR

[PATCH] [i386]Add missing BMI function to align with clang

Hi all, This patch adds missing BMI function _tzcnt_u16, _andn_u32, _andn_u64 to align with clang. Regtested on x86_64-pc-linux-gnu. Ok for trunk? BRs, Haochen gcc/ChangeLog: * config/i386/bmiintrin.h (_tzcnt_u16): New define function. (_andn_u32): Ditto. (_andn_u64):

[PATCH] [i386]Fix tdpbf16ps testcase

Hi all, This patch fix the testcase of amxbf16-dpbf16ps-2.c. Previously the type convert has some issue. Ok for trunk? BRs, Haochen gcc/testsuite/ChangeLog: * gcc.target/i386/amx-check.h (check_float_tile_register): New check function for float to prevent precision loss.

[PATCH] [i386]Add combine splitter to transform vashr/vlshr/vashl_optab to ashr/lshr/ashl_optab for const vector duplicate operand.

Hi, This patch add combine splitter to transform vashr/vlshr/vashl_optab to ashr/lshr/ashl_optab for const vector duplicate operand. Regtested on x86_64-pc-linux-gnu. Ok for trunk? BRs, Haochen gcc/ChangeLog: PR target/101796 * config/i386/predicates.md

[PATCH] [i386][avx512]Add combine splitter to transform vpternlogd/vpcmpeqd/vpxor/vblendvps to vblendvps for ~op0

Hi all, This patch fix the regression previously reported on the combine splitter under '-m32 -march=cascadelake' options. Regtested on x86_64-pc-linux-gnu. BRs, Haochen gcc/ChangeLog: PR target/100738 * config/i386/sse.md (*avx_cmp3_lt, *avx_cmp3_ltint): Remove MEM_P

[PATCH] [i386] Remove register restriction on operands for andnot insn

Hi all, This patch removes the register restriction on operands for andnot insn so that it can be used from memory. Regtested on x86_64-pc-linux-gnu. Ok for trunk? BRs, Haochen gcc/ChangeLog: PR target/53652 * config/i386/sse.md (*andnot3): Remove register restriction.

[PATCH] [i386] Optimize a ^ ((a ^ b) & mask) to (~mask & a) | (b & mask).

Hi all, This patch targets PR94790, which change the instruction selection under the following circumstance. Regtested on x86_64-pc-linux-gnu. Ok for trunk? BRs, Haochen >From the perspective of the pipeline, `andn + and + ior` version take 2 cycles(AND and ANDN doesn't have dependence), but

[PATCH 2/2] [PATCH 2/2] Support AVX10.1 for AVX512DQ intrins

gcc/testsuite/ChangeLog: * gcc.target/i386/avx10_1-kaddb-1.c: New test. * gcc.target/i386/avx10_1-kaddw-1.c: Ditto. * gcc.target/i386/avx10_1-kandb-1.c: Ditto. * gcc.target/i386/avx10_1-kandnb-1.c: Ditto. * gcc.target/i386/avx10_1-kmovb-1.c: Ditto.

[PATCH 0/2] Support AVX10.1 for AVX512DQ intrins

Hi all, I have just checked in the first nine patches for AVX10.1 after one day waiting since Hongtao said ok. These two patches aimed to add AVX512DQ scalar intrins to AVX10.1. Regtested on on x86_64-pc-linux-gnu. Ok for trunk? Also, We proposed to commit the patches step by step in the

[PATCH 1/2] [PATCH 1/2] Support AVX10.1 for AVX512DQ intrins

gcc/ChangeLog: * config.gcc: Add avx512dqavx10_1intrin.h. * config/i386/avx512dqintrin.h: Move avx10_1 related intrins to new intrin file. * config/i386/i386-builtin.def (BDESC): Add OPTION_MASK_ISA2_AVX10_1. * config/i386/i386.md (x64_avx512dq):

[PATCH] i386: Add AVX2 pragma wrapper for AVX512DQVL intrins

Hi all, This patch aims to fix PR111051, which actually make sure that AVX2 intrins are visible to AVX512/AVX10 intrins under any circumstances. I will also apply the same fix on AVX512DQ scalar intrins. Regtested on on x86_64-pc-linux-gnu. Ok for trunk? Thx, Haochen PR target/111051

[PATCH] Add myself for write after approval

Hi all, I want to add myself in MAINTAINERS for write after approval. Ok for trunk? BRs, Haochen ChangeLog: * MAINTAINERS (Write After Approval): Add myself. --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 151770f59f4..3c448ba9eb6

[PATCH] i386: Add AVX512BW to AVX512F in MASK_ISA2

Hi all, I just found in MASK_ISA2_UNSET part, since AVX512BW is based on AVX512F, we should add OPTION_MASK_ISA2_AVX512BW_UNSET to AVX512F for maintainence convenience and logic correctness, or we will need to add all future ISAs based on AVX512BW in both AVX512F and AVX512BW. This will be easily

[PATCH] i386: Handle memory operand for direct call to cvtps2pd in unpack

Hi all, This patch aim to fix the ICE for vec unpack using for memory after the commit r13-1418 on inproper insn of cvtps2pd. Regtested on x86_64-pc-linux-gnu. Ok for trunk? BRs, Haochen gcc/ChangeLog: PR target/106180 * config/i386/sse.md (sse2_cvtps2pd_1): Rename

[PATCH] i386: Add syscall to enable AMX for latest kernels

From: "Jiang, Haochen" Hi all, We need syscall to enable AMX for kernels>=5.4. It is missing in current amx tests, which will cause test fail. This patch aims to add them to fix this bug. BRs, Haochen gcc/testsuite/ChangeLog: * gcc.target/i386/amx-check.h (request_perm_xtile_data):

[PATCH] i386: Extend cvtps2pd to memory

Hi all, This patch aims to fix the cvtps2pd insn, which should also work on memory operand but currently does not. After this fix, when loop == 2, it will eliminate movq instruction. Regtested on x86_64-pc-linux-gnu. Ok for trunk? BRs, Haochen gcc/ChangeLog: PR target/43618 *

[PATCH] Reconstruct i386 testsuite with __builtin_cpu_supports

Hi all, There are some check files in i386 testsuite are written before the function __builtin_cpu_supports is introduced. All of them are using __get_cpuid_count. This patch aims to reconstruct the i386 testsuite with __builtin_cpu_supports so that we can have a much clearer code. Regtested

[PATCH] [i386]Add combine splitter to transform pxor/pcmpeqb/pmovmskb/cmp 0xffff to ptest.

Hi all, This patch aims to add a combine splitter to transform pxor/pcmpeqb/pmovmskb/cmp 0x to ptest. Regtested on x86_64-pc-linux-gnu. Ok for trunk? BRs, Haochen gcc/ChangeLog: PR target/104371 * config/i386/sse.md: Add new define_mode_attr and define_split.

[PATCH] Add __m128bf16/__m256bf16/__m512bf16 type for bf16 abi test

Hi all, This patch added __m128bf16/__m256bf16/__m512bf16 type in testcases. BRs, Haochen gcc/testsuite/ChangeLog: * gcc.target/x86_64/abi/bf16/bf16-helper.h: Add _m128bf16/m256bf16/_m512bf16. * gcc.target/x86_64/abi/bf16/m512bf16/bf16-zmm-check.h: Include

[PATCH v2] Add a parameter for the builtin function of prefetch to align with LLVM

Hi Richard, This is my new patch and changes the warning message on aarch64/arm. Ok for trunk? BRs, Haochen gcc/ChangeLog: * builtins.cc (expand_builtin_prefetch): Handle the fourth parameter in expand function. * config/aarch64/aarch64-sve.md: Add default parameter

[PATCH] i386: Auto vectorize sdot_prod, udot_prod with VNNIINT8 instruction.

Hi all, We would like to add one more patch to enhance the codegen with avxvnniint8. Also renamed two awkward named mode_attr to make them more aligned with others. Regtested on x86_64-pc-linux-gnu. Ok for trunk? BRs, Haochen gcc/ChangeLog: * config/i386/sse.md (ssedvecmode): Rename

[PATCH v2] Support Intel AVX-VNNI-INT8

From: Kong Lingling Hi all, This is our v2 patch on AVX-VNNI-INT8. This main change in this patch is to rename the previous UNSPEC_VPMADDxxx things to new vnni style. Ok for trunk? BRs, Haochen gcc/ChangeLog * common/config/i386/cpuinfo.h (get_available_features): Detect

[PATCH] Support Intel CMPccXADD

Hi all, I just refined CMPccXADD patch to make the enum in order intrin file aligned with how opcode does. Ok for trunk? BRs, Haochen gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Detect cmpccxadd. * common/config/i386/i386-common.cc

[PATCH 2/6] Support Intel AVX-VNNI-INT8

From: Kong Lingling gcc/ChangeLog * common/config/i386/cpuinfo.h (get_available_features): Detect avxvnniint8. * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_AVXVNNIINT8_SET): New. (OPTION_MASK_ISA2_AVXVNNIINT8_UNSET): Ditto.

[PATCH 6/6] Initial Sierra Forest Support

gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_intel_cpu): Add Sierra Forest. * common/config/i386/i386-common.cc (processor_names): Add Sierra Forest. (processor_alias_table): Ditto. * common/config/i386/i386-cpuinfo.h (enum

[PATCH 1/3] Add a parameter for the builtin function of prefetch to align with LLVM

gcc/ChangeLog: * builtins.cc (expand_builtin_prefetch): Handle the fourth parameter in expand function. * config/aarch64/aarch64-sve.md: Add default parameter value. * config/aarch64/aarch64.md (prefetch): New define_expand. (*prefetch): Add default

[PATCH 2/3] Support Intel prefetchit0/t1

gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Detect PREFETCHI. * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_PREFETCHI_SET, OPTION_MASK_ISA2_PREFETCHI_UNSET): New. (ix86_handle_option): Handle -mprefetchi.

[PATCH 1/2] Initial Raptorlake Support

gcc/ChangeLog: * common/config/i386/cpuinfo.h: (get_intel_cpu): Handle Raptorlake. * common/config/i386/i386-common.cc: (processor_alias_table): Add Raptorlake. --- gcc/common/config/i386/cpuinfo.h | 2 ++ gcc/common/config/i386/i386-common.cc | 2 ++ 2 files

[PATCH 2/2] Initial Meteorlake Support

From: "Hu, Lin1" gcc/ChangeLog: * common/config/i386/cpuinfo.h: (get_intel_cpu): Handle Meteorlake. * common/config/i386/i386-common.cc: (processor_alias_table): Add Meteorlake. --- gcc/common/config/i386/cpuinfo.h | 4

[PATCH 0/2] Add new Intel Architecture

Hi all, These two patches aimed to add new Intel processors according to newly released Intel Architecture Instruction Set Extensions and Future Features. The document comes following:

[PATCH 1/6] Support Intel AVX-IFMA

From: Hongyu Wang gcc/ * common/config/i386/i386-common.cc (OPTION_MASK_ISA_AVXIFMA_SET, OPTION_MASK_ISA2_AVXIFMA_UNSET, OPTION_MASK_ISA2_AVX2_UNSET): New macro. (ix86_handle_option): Handle -mavxifma. * commmon/config/i386/i386-cpuinfo.h

[PATCH 3/6] i386: Add intrinsic for vector __bf16

From: konglin1 gcc/ChangeLog: * config/i386/avx512fp16intrin.h : New intrinsic. (_mm_load_sbf16): Ditto. (_mm_mask_load_sbf16): Ditto. (_mm_maskz_load_sbf16): Ditto. (_mm_mask_store_sbf16): Ditto. (_mm_mask_move_sbf16): Ditto.

[PATCH 0/6] Add Intel Sierra Forest Instructions

Hi all, These six patches aimed to add Intel Sierra Forest instructions, including AVX-IFMA, AVX-VNNI0INT8, AVX-NE-CONVERT, CMPccXADD. We also added intrinsic for vector __bf16 in this series of patch and Sierra Forest Support. The information is based on newly released Intel Architecture

[PATCH 2/2] Support Intel prefetchit0/t1

gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Detect PREFETCHI. * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_PREFETCHI_SET, OPTION_MASK_ISA2_PREFETCHI_UNSET): New. (ix86_handle_option): Handle -mprefetchi.

[PATCH 4/6] Support Intel AVX-NE-CONVERT

From: Kong Lingling gcc/ChangeLog: * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_AVXNECONVERT_SET, OPTION_MASK_ISA2_AVXNECONVERT_UNSET): New. (ix86_handle_option): Handle -mavxneconvert, unset avxneconvert when avx2 is disabled. *

[PATCH 5/6] Support Intel CMPccXADD

gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Detect cmpccxadd. * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_CMPCCXADD_SET, OPTION_MASK_ISA2_CMPCCXADD_UNSET): New. (ix86_handle_option): Handle -mcmpccxadd, unset

[PATCH 1/2] Add a parameter for the builtin function of prefetch to align with LLVM

gcc/ChangeLog: * builtins.cc (expand_builtin_prefetch): Handle the fourth parameter in expand function. * config/aarch64/aarch64-sve.md: Add default parameter value. * config/aarch64/aarch64.md (prefetch): New define_expand. (*prefetch): Add default

[PATCH] Support Intel AMX-FP16 ISA

From: Hongyu Wang Hi all, This patch aimed to add Intel AMX-FP16 ISA according to newly released Intel Architecture Instruction Set Extensions and Future Features. The document comes following:

[PATCH 0/2] Add a Fourth parameter for prefetch and Support Intel PREFETCHI

Hi all, Sorry for the previous cover-letter stucking and disturbance and this is the right cover letter. These two patches aimed to add Intel PREFETCHI. The information is based on newly released Intel Architecture Instruction Set Extensions and Future Features. The document comes following:

[PATCH] Add ABI test for __bf16 type

Hi all, This patch aims to add bf16 abi test after the whole __bf16 type is added. Regtested on x86_64-pc-linux-gnu. Ok for trunk? BRs, Haochen gcc/testsuite/ChangeLog: * gcc.target/x86_64/abi/bf16/abi-bf16.exp: New test. * gcc.target/x86_64/abi/bf16/args.h: Ditto. *

[PATCH] Fix intrin name in Intel CMPccXADD

Hi all, We usually use only one "_" but not two "__" as prefix in intrin. This patch aims to fix the intrin name for CMPccXADD. Bootstrapped and regtested on x86_64-pc-linux-gnu. Ok for trunk? BRs, Haochen gcc/ChangeLog: * config/i386/cmpccxaddintrin.h (__cmpccxadd_epi32):

[PATCH] i386: Add ISA check for newly introduced prefetch builtins.

Hi all, As Hongtao said, the fail on pentiumpro is caused by missing ISA check since we are using emit_insn () through new builtins and it won't check if the TARGET matches. Previously, the builtin in middle-end will check that. On pentiumpro, we won't have anything that supports any prefetch so

[PATCH] i386: Add AMX-TILE dependency for AMX related ISAs

Hi all, For all AMX related ISAs, we have a potential dependency on AMX-TILE or we even won't have the basic support on AMX. This patch added those dependency. Ok for trunk? BRs, Haochen gcc/ChangeLog: * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_AMX_INT8_SET): Add

[PATCH 2/2] Add m_CORE_ATOM for atom cores

gcc/ChangeLog: * config/i386/i386-options.cc (m_CORE_ATOM): New. * config/i386/x86-tune.def (X86_TUNE_SCHEDULE): Initial tune for CORE_ATOM. (X86_TUNE_PARTIAL_REG_DEPENDENCY): Ditto. (X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY): Ditto.

[PATCH 0/2] Intel Grand Ridge Support

Hi all, These patches aimed to add initial Granite Rapids support for GCC. Also we added a new m_CORE_ATOM for future atom core tune. They need to be checked in after RAO-INT patch. The information for Granite Rapids comes following:

[PATCH 1/2] Initial Grand Ridge support

gcc/ChangeLog: * common/config/i386/i386-common.cc (processor_names): Add grandridge. (processor_alias_table): Ditto. * common/config/i386/i386-cpuinfo.h: (enum processor_types): Add INTEL_GRANDRIDGE. * config.gcc: Add -march=grandridge. *

[PATCH] Initial Granite Rapids support

From: "Hu, Lin1" Hi all, This patch aimed to add initial Granite Rapids support for GCC. It needs to be checked in after prefetchit0/t1 patch. The information for Granite Rapids comes following:

[PATCH] Support Intel prefetchit0/t1

Hi all, We will take back the patches which add a new parameter on original builtin_prefetch and implement instruction prefetch on that. Also we consider that since we will only do that on specific backend, no need to add a new rtl for that. This patch will only support instructions prefetch

[wwwdocs] gcc-13: Mention Intel new ISA and march support.

Hi all, This patch aims to mention newly added Intel ISA and march support. Ok for trunk? BRs, Haochen --- htdocs/gcc-13/changes.html | 50 ++ 1 file changed, 50 insertions(+) diff --git a/htdocs/gcc-13/changes.html b/htdocs/gcc-13/changes.html index

[PATCH] Support Intel CMPccXADD

Hi all, I just revised the patch according to review. The changes comparing to previous version is mentioned below. Ok for trunk? BRs, Haochen gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Detect cmpccxadd. * common/config/i386/i386-common.cc

[PATCH] i386: Share AES xmm intrin with VAES

Hi all, Currently in GCC, the 128 bit intrin for instruction vaes{end,dec}{last,} is under AES ISA. Because there is no dependency between ISA set AES and VAES, The 128 bit intrin is not available when we use compiler flag -mvaes -mavx512vl and there is no other way to use that intrin. But it

[PATCH] i386: Use macro to wrap up share builtin exceptions in builtin isa check

Hi all, Currently in i386, we have several ISAs share builtin between each other which is handled in ix86_check_builtin_isa_match with if condition clauses. The patterns for these clauses are quite similar so it will be more friendly for developers if we rewrite them as a macro. This patch adds

[PATCH 2/2] i386: Add AVX512BW dependency to AVX512VBMI2

gcc/ChangeLog: * common/config/i386/i386-common.cc (OPTION_MASK_ISA_AVX512VBMI2_SET): Change OPTION_MASK_ISA_AVX512F_SET to OPTION_MASK_ISA_AVX512BW_SET. (OPTION_MASK_ISA_AVX512F_UNSET): Remove OPTION_MASK_ISA_AVX512VBMI2_UNSET.

[PATCH 1/2] i386: Add AVX512BW dependency to AVX512BITALG

gcc/ChangeLog: * common/config/i386/i386-common.cc (OPTION_MASK_ISA_AVX512BITALG_SET): Change OPTION_MASK_ISA_AVX512F_SET to OPTION_MASK_ISA_AVX512BW_SET. (OPTION_MASK_ISA_AVX512F_UNSET): Remove OPTION_MASK_ISA_AVX512BITALG_SET.

[PATCH 0/2] i386: Add missing AVX512BW dependency for ISAs using 32/64 bit mask

Hi all, 32/64 bit mask are introduced in AVX512BW. Therefore, when we are using them, we should imply AVX512BW. The two patches added the dependency and removed the redundant AVX512BW usage for AVX512BITALG and AVX512VBMI2. Tested on x86_64-pc-linux-gnu. Ok for trunk? BRs, Haochen

[PATCH] i386: Share AES xmm intrin with VAES

Hi all, I realized that I attached a old version of my patch. We should change the error message of pr109117-1.c but not pr84335.c. Please review this patch. Thx, Haochen gcc/ChangeLog: * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_AVX_UNSET): Add

[PATCH] i386: Fix vpblendm{b,w} intrins and insns

Hi all, For vpblendm{b,w}, they actually do not have constant parameters. Therefore, there is no need for them been wrapped in __OPTIMIZE__. Also, we should check TARGET_AVX512VL for 128/256 bit vectors in patterns. This patch did the fixes mentioned above. Tested on x86_64-pc-linux-gnu. Ok for

[PATCH] i386: Add PCLMUL dependency for VPCLMULQDQ

Hi all, Currently in GCC, the 128 bit intrin for instruction vpclmulqdq is under PCLMUL ISA. Because there is no dependency between ISA set PCLMUL and VPCLMULQDQ, The 128 bit intrin is not available when we just use compiler flag -mvpclmulqdq. But it should according to Intel SDM. Since

[PATCH 1/2] Support Intel AMX-COMPLEX

gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Detect AMX-COMPLEX. * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_AMX_COMPLEX_SET, OPTION_MASK_ISA2_AMX_COMPLEX_UNSET): New. (ix86_handle_option): Handle -mamx-complex.

[PATCH 2/2] i386: Add AMX-COMPLEX to Granite Rapids

gcc/Changelog: * config/gcc/i386.h (PTA_GRANITERAPIDS): Add PTA_AMX_COMPLEX. --- gcc/config/i386/i386.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index dd9391c492b..1da6dce8e0b 100644 --- a/gcc/config/i386/i386.h

[PATCH 0/2] Support Intel AMX-COMPLEX

Hi all, These patch aims to add Intel AMX-COMPLEX instructions. Also we added AMX-COMPLEX to -march=graniterapids. The information is based on newly released Intel Architecture Instruction Set Extensions and Future Features. The document comes following:

[PATCH] gcc-13: Mention Intel AMX-COMPLEX ISA support and revise march support

Hi all, This patch mentions Intel AMX-COMPLEX ISA support in GCC 13. Also it revises the march support according to newly released Intel Architecture Instruction Set Extensions and Future Features. Ok for trunk? BRs, Haochen --- htdocs/gcc-13/changes.html | 10 +- 1 file changed, 9

[PATCH] i386: Guard 128 bit VAES builtins with AVX512VL

Hi all, Currently on trunk, both usage of intrin and builtin for 128 bit VAES ISA will result in ICE since we did not check AVX512VL until pattern, which is not user expected. This patch aims to fix that ICE and throw an error under this scenario. Regtested on x86-64-linux-gnu{-m32,}. Ok for

[PATCH 1/4] Support Intel AVX-VNNI-INT16

From: Kong Lingling gcc/ChangeLog * common/config/i386/cpuinfo.h (get_available_features): Detect avxvnniint16. * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_AVXVNNIINT16_SET): New. (OPTION_MASK_ISA2_AVXVNNIINT16_UNSET): Ditto.

[PATCH 3/4] Support Intel SHA512

gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Detect SHA512. * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_SHA512_SET, OPTION_MASK_ISA2_SHA512_UNSET): New. (OPTION_MASK_ISA2_AVX_UNSET): Add SHA512.

[PATCH 2/4] Support Intel SM3

gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Detect SM3. * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_SM3_SET, OPTION_MASK_ISA2_SM3_UNSET): New. (OPTION_MASK_ISA2_AVX_UNSET): Add SM3. (ix86_handle_option): Handle

[PATCH 4/4] Support Intel SM4

gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Detech SM4. * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_SM4_SET, OPTION_MASK_ISA2_SM4_UNSET): New. (OPTION_MASK_ISA2_AVX_UNSET): Add SM4. (ix86_handle_option): Handle

[PATCH 0/4] Support Intel Arrow Lake/Lunar Lake ISAs

Hi all, These four patches aimed to add Intel Arrow Lake/Lunar Lake instructions, including AVX-VNNI-INT16, SM3, SHA512 and SM4. The information is based on newly released Intel Architecture Instruction Set Extensions and Future Features. The document comes following:

[PATCH] i386: Auto vectorize usdot_prod, udot_prod with AVXVNNIINT16 instruction.

Hi all, This patch aims to auto vectorize usdot_prod and udot_prod with newly introduced AVX-VNNI-INT16. Also I refined the redundant mode iterator in the patch. Regtested on x86_64-pc-linux-gnu. Ok for trunk after AVX-VNNI-INT16 patch checked in? BRs, Haochen gcc/ChangeLog: *

[PATCH] [gcc-wwwdocs]gcc-13/14: Mention Intel new ISA and march support

Hi all, This patch adds documentation to wwwdocs to mention the recent introduction of Intel new ISA and march. Ok for trunk? BRs, Haochen --- htdocs/gcc-13/changes.html | 4 htdocs/gcc-14/changes.html | 34 +- 2 files changed, 37 insertions(+), 1

[PATCH] Correct Granite Rapids{, D} documentation

Hi all, This patch will fix the documentation error in invoke.texi where includes AVX512VP2INTERSECT in GNR and GNR-D previously. Commit ad obvious change and backport to GCC 13 branch. Thx, Haochen gcc/Changelog: * doc/invoke.texi: Remove AVX512VP2INTERSECT in Granite

[PATCH] Fix a typo

Hi all, This patch fix a typo which will not cause any behavior difference. Commited as obvious change. Thx, Haochen gcc/ChangeLog: * config/i386/i386.opt: Fix a typo. --- gcc/config/i386/i386.opt | 5 - 1 file changed, 5 deletions(-) diff --git a/gcc/config/i386/i386.opt

[PATCH 1/3] Initial support for AVX10.1

gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Add avx10_set and version and detect avx10.1. (cpu_indicator_init): Handle avx10.1-512. * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_AVX10_512BIT_SET): New.

[PATCH 4/6] Support AVX10.1 for AVX512DQ+AVX512VL intrins

gcc/testsuite/ChangeLog: * gcc.target/i386/avx10_1-abs-copysign-1.c: New test. * gcc.target/i386/avx10_1-vandpd-1.c: Ditto. * gcc.target/i386/avx10_1-vandps-1.c: Ditto. * gcc.target/i386/avx10_1-vcvtps2qq-1.c: Ditto. *

[PATCH 6/6] Support AVX10.1 for AVX512DQ+AVX512VL intrins

gcc/testsuite/ChangeLog: * gcc.target/i386/avx10_1-vextractf64x2-1.c: New test. * gcc.target/i386/avx10_1-vextracti64x2-1.c: Ditto. * gcc.target/i386/avx10_1-vfpclasspd-1.c: Ditto. * gcc.target/i386/avx10_1-vfpclassps-1.c: Ditto. *

[PATCH 5/6] Support AVX10.1 for AVX512DQ+AVX512VL intrins

gcc/ChangeLog: * config/i386/avx512vldqintrin.h: Remove target attribute. * config/i386/i386-builtin.def (BDESC): Add OPTION_MASK_ISA2_AVX10_1. * config/i386/sse.md (VF_AVX512VLDQ_AVX10_1): New. (VFH_AVX512VLDQ_AVX10_1): Ditto.

[PATCH 3/6] Support AVX10.1 for AVX512DQ+AVX512VL intrins

gcc/ChangeLog: * config/i386/avx512vldqintrin.h: Remove target attribute. * config/i386/i386-builtin.def (BDESC): Add OPTION_MASK_ISA2_AVX10_1. * config/i386/i386.cc (standard_sse_constant_opcode): Add TARGET_AVX10_1. * config/i386/i386.md: Add new isa

[PATCH 2/6] Support AVX10.1 for AVX512DQ+AVX512VL intrins

gcc/testsuite/ChangeLog: * gcc.target/i386/avx10_1-vandnpd-1.c: New test. * gcc.target/i386/avx10_1-vandnps-1.c: Ditto. * gcc.target/i386/avx10_1-vbroadcastf32x2-1.c: Ditto. * gcc.target/i386/avx10_1-vbroadcastf64x2-1.c: Ditto. *

[PATCH 1/6] Support AVX10.1 for AVX512DQ+AVX512VL intrins

gcc/ChangeLog: * config/i386/avx512vldqintrin.h: Remove target attribute. * config/i386/i386-builtin.def (BDESC): Add OPTION_MASK_ISA2_AVX10_1. * config/i386/i386-builtins.cc (def_builtin): Handle AVX10_1. * config/i386/i386-expand.cc

[PATCH 2/3] Emit a warning when disabling AVX512 with AVX10 enabled or disabling AVX10 with AVX512 enabled

gcc/ChangeLog: * config/i386/driver-i386.cc (host_detect_local_cpu): Do not append -mno-avx10.1 for -march=native. * config/i386/i386-options.cc (ix86_check_avx10): New function to check isa_flags and isa_flags_explicit to emit warning when AVX10 is enabled

[PATCH 3/3] Emit a warning when AVX10 options conflict in vector width

gcc/ChangeLog: * config/i386/driver-i386.cc (host_detect_local_cpu): Do not append -mno-avx10-max-512bit for -march=native. * common/config/i386/i386-common.cc (ix86_check_avx10_vector_width): New function to check isa_flags to emit a warning when there is