[Patch, MIPS] Add Octeon3 support

Hi, This patch adds Cavium octeon3 support in mips. Please review the patch and let us know if there should be any modifications. Submitting the patch on behalf of Andrew Pinski. Thanks, 2014-10-07 Andrew Pinski apin...@cavium.com * config/mips/mips-cpus.def (octeon3): New cpu.

Re: [Patch, MIPS] Add Octeon3 support

Hi, Patches adding new -march= values need to update invoke.texi. Thanks for reviewing the patch and suggestion. Please find attached the modified patch which updates octeon3 in invoke.texi Please review the patch and let us know if there should be any further modifications. Thanks,

Re: [Patch, MIPS] Add Octeon3 support

Hi, Thanks for the review and your comments. Is it intentional that you have not updated driver-native.c to detect an Octeon 3 CPU? We have not yet looked into that part yet and will be looking at it later. Could you confirm what testing the patch has had? Run the regression in build

Re: [Patch, MIPS] Add Octeon3 support

Hi Catherine, Would you please add some testcases and resubmit your patch? Thanks for the review and suggestions. Added the testcase gcc.target/mips/octeon3-pipe-1.c Please review the modified patch and let us know if its good. Thanks, Naveen 2014-10-31 Andrew Pinski apin...@cavium.com

[Patch] Ignore Invalid Memory operands in constraint 'X'

Hi, The definition of constraint 'X' allows all operands. `X' - Any operand whatsoever is allowed. However, invalid memory operands should not be valid input for 'X'. Please find attached the patch X_constraint.patch which ignores invalid memory operands in constraint 'X'. Fixes the ICE

[AARCH64] Remove %r from asm_printf

Hi, ASM_FPRINTF_EXTENSIONS was copied from the arm back-end and is not needed. Please find attached the patch that replaces %r in asm_fprintf with reg_names. The definition of ASM_FPRINTF_EXTENSIONS is removed as it is no longer needed. Please review the patch and let me know if there should be

[Patch, AARCH64] Define REVERSIBLE_CC_MODE

Hi, AARCH64 back-end defines REVERSE_CONDITION but not REVERSIBLE_CC_MODE. REVERSE_CONDITION is used only in case REVERSIBLE_CC_MODE (mode) is nonzero. Please find attached the patch that defines REVERSIBLE_CC_MODE for aarch64 back-end. Please review the patch and let me know if there should be

[PING^1] [Patch] Ignore Invalid Memory operands in constraint 'X'

Hi, Please consider this as a reminder to review the patch posted at following link:- http://gcc.gnu.org/ml/gcc-patches/2012-12/msg00765.html Please review the patch and let me know if its okay? Thanks Regards, Naveen.H.S

[Patch, AARCH64] Remove REGISTER_PREFIX

Hi, AARCH64 back-end defines REGISTER_PREFIX to empty string. Hence, it can be removed as the default value of REGISTER_PREFIX is . Please find attached the patch that removes REGISTER_PREFIX and all its occurrence in aarch64 back-end. Please review the patch and let me know if there should be

RE: [Patch, AARCH64] Define REVERSIBLE_CC_MODE

Hi Marcus, Thanks for reviewing the patch. Given the comment about SELECT_CC_MODE and the implementation of aarch64_select_cc_mode this definition of REVERSIBLE_CC_MODE looks broken to me. Please find attached the modified patch that does not allow floating point inequality comparisons in

[Patch, AArch64-4.7] Remove %r from asm_printf

Hi, It would be much appreciated if you would handle the back port to ARM/aarch64-4.7-branch Thanks for reviewing the patch and your comments. Please find attached the backported patch to ARM/aarch64-4.7-branch. Regressed for aarch64-elf on aarch64-4.7-branch. Thanks, Naveen.H.S 2013-01-09

[Patch] FYI: Update my e-mail address in MAINTAINERS

Hi, Update my e-mail address in MAINTAINERS file. Committed: 2013-01-10 Naveen H.S naveen.hurugalaw...@caviumnetworks.com * MAINTAINERS (Write After Approval): Update e-mail address.--- gcc/MAINTAINERS 2013-01-10 11:46:59.886102413 +0530 +++ gcc/MAINTAINERS 2013-01-10

Allow widening multiplication in tree-ssa/slsr-*.c

Hi, The slsr-*.c testsuite failures are due to not matching widening add (or multiply-add) in AARCH64. The LP64 targets generates WIDEN_MULT_PLUS_EXPR which is correct and even better code generation will be produced. However, the testcase expects +OP2 in these cases and hence FAIL's. Please

[PING^2] [Patch] Ignore Invalid Memory operands in constraint 'X'

Hi, Please consider this as a reminder to review the patch posted at following link:- http://gcc.gnu.org/ml/gcc-patches/2012-12/msg00765.html Please review the patch and let me know if its okay? Thanks Regards, Naveen.H.S

[PING^1] [Patch, AARCH64] Define REVERSIBLE_CC_MODE

Hi, Please consider this as a reminder to review the patch posted at following link:- http://gcc.gnu.org/ml/gcc-patches/2013-01/msg00463.html Please review the patch and let me know if its okay? Thanks Regards, Naveen.H.S

[PING^1] [Patch, AARCH64] Remove REGISTER_PREFIX

Hi, Please consider this as a reminder to review the patch posted at following link:- http://gcc.gnu.org/ml/gcc-patches/2013-01/msg00388.html Please review the patch and let me know if its okay? Thanks Regards, Naveen.H.S

[Patch, AARCH64] Fix warning: TARGET_FIXED_CONDITION_CODE_REGS redefined

Hi, Please find attached the patch that fixes following warning in aarch64:- warning: TARGET_FIXED_CONDITION_CODE_REGS redefined Thanks, Naveen.H.S 2013-01-25 Naveen H.S naveen.hurugalaw...@caviumnetworks.com * config/aarch64/aarch64.c (TARGET_FIXED_CONDITION_CODE_REGS):

[AArch64] Implement Bitwise AND and Set Flags

Hi, Please find attached the patch that implements Bitwise AND and Set Flags instruction for aarch64 target. The patch adds a testcase ands.c which is similar to the adds.c. Please review the patch and let me know if there should be any modifications? Build and tested on aarch64-thunder-elf

[Patch, AArch64, AArch64-4.7] Implement Bitwise AND and Set Flags

Hi, Please find attached the patch that implements Bitwise AND and Set Flags instruction for aarch64 target. The patch adds a testcase ands.c which is similar to the adds.c. Please review the patch and let me know if there should be any modifications? Regressed for aarch64-elf on

[Patch, AArch64] Implement SIMD Absolute Difference Instructions

Hi, Please find attached the patch that implements absolute difference instructions for aarch64 target. The patch modifies the testcase vect.c and vect-fp.c to check the generated instructions and also their functionality. Please review the patch and let me know if there should be any

[Patch, AArch64, AArch64-4.7] Implement SIMD Absolute Difference Instructions

Hi, Please find attached the patch that implements absolute difference instructions for aarch64 target. The patch modifies the testcase vect.c and vect-fp.c to check the generated instructions and also their functionality. Please review the patch and let me know if there should be any

[PING^1] Allow widening multiplication in tree-ssa/slsr-*.c

Hi, Please consider this as a reminder to review the patch posted at following link:- http://gcc.gnu.org/ml/gcc-patches/2013-01/msg00823.html Please review the patch and let me know if its okay? Thanks Regards, Naveen.H.S

[PING^1] [AArch64] Implement Bitwise AND and Set Flags

Hi, Please consider this as a reminder to review the patch posted at following link:- http://gcc.gnu.org/ml/gcc-patches/2013-01/msg01374.html The patch is slightly modified to use CC_NZ mode instead of CC. Please review the patch and let me know if its okay? Thanks Regards, Naveen.H.S ---

[PING^1] [Patch, AArch64] Implement SIMD Absolute Difference Instructions

Hi, Please consider this as a gentle reminder to review the patch posted at following link:- http://gcc.gnu.org/ml/gcc-patches/2013-01/msg01412.html Please review the patch and let me know if its okay? Thanks Regards, Naveen.H.S

[PING^2] Allow widening multiplication in tree-ssa/slsr-*.c

Hi, Please consider this as a gentle reminder to review the patch posted at following link:- http://gcc.gnu.org/ml/gcc-patches/2013-01/msg00823.html Please review the patch and let me know if its okay? Thanks Regards, Naveen.H.S

[PING] [AArch64] Peepholes to generate ldp and stp instructions

Hi, Please consider this as a reminder to review the ldp and stp peephole implementation for AArch64 target. The patch was originally posted at:- http://gcc.gnu.org/ml/gcc-patches/2013-03/msg01051.html Please review the same and let me know if its okay. Build and tested on aarch64-thunder-elf

RE: [PING] [AArch64] Peepholes to generate ldp and stp instructions

Hi, You are better off CCing the maintainers for such reviews. Let me do that for you. I cannot approve or reject this patch but I have a few comments as below. Thanks for the quick review and comments. Please find attached the modified patch as per review comments. Please review the same

[Patch] [aarch64] Fix asm-subreg-1.c ICE

Hi, Please find attached the patch “asm-subreg.patch” for aarch64 which fixes ICE for /gcc.dg/torture/asm-subreg-1.c testcase. The error was the result of reload problems in “aarch64_load_symref_appropriately” function. The higher part of symbol_ref moved to temporary RTX “tmp_reg” does not

[Patch] [aarch64] Fix asm-subreg-1.c ICE

Hi, Please find attached the patch “asm-subreg.patch” for aarch64 which fixes ICE for /gcc.dg/torture/asm-subreg-1.c testcase. The error was the result of reload problems in “aarch64_load_symref_appropriately” function. The higher part of symbol_ref moved to temporary RTX “tmp_reg” does not

RE: [Patch] [aarch64] Fix asm-subreg-1.c ICE

Hi, Not to mention the ChangeLog entry. Sorry about the missed patch and ChangeLog Entry. Please review the patch and let me know if its OK. Regression Tested on aarch64-elf. No new Regressions. 2012-11-28 Naveen H.S naveen.hurugalaw...@caviumnetworks.com * aarch64.c

[AArch64] Restrict the shift value in compare extended shift operation

Hi, Please find attached the patch that restricts the shift value in comparison operation between 0-4. Please review the patch and let me know if its okay? 2013-05-07 Naveen H.S naveen.hurugalaw...@caviumnetworks.com * config/aarch64/aarch64.md

RE: [Patch, AArch64] Implement SIMD Absolute Difference Instructions

Hi Marcus, Thanks for reviewing the patch and your comments. Please drop the trailing white space, here and on the following patterns. The trailing white spaces are observed only in the patch. When the patch is applied on sources, there are no trailing white spaces. GNU style, spaces around

RE: [Patch, AArch64] Implement SIMD Absolute Difference Instructions

From: Marcus Shawcroft [marcus.shawcr...@arm.com] Sent: Wednesday, February 27, 2013 3:32 PM To: Hurugalawadi, Naveen Cc: gcc-patches@gcc.gnu.org Subject: Re: [Patch, AArch64] Implement SIMD Absolute Difference Instructions On 27/02/13 05:15, Hurugalawadi, Naveen

RE: [Patch, AArch64] Implement SIMD Absolute Difference Instructions

Hi Marcus, The use of TAB there is fine. The issue is that you have trail white space at the end of the line, which is still present in the latest patch. Sorry. I confused it with spaces at the start of pattern instead of trailing space. I have modified it as per your suggestion. Please

[PING^2] [AArch64] Implement Bitwise AND and Set Flags

Hi, Please consider this as a reminder to review the patch posted at following link:- http://gcc.gnu.org/ml/gcc-patches/2013-02/msg00678.html Please review the patch and let me know if its okay? Thanks Regards, Naveen.H.S

RE: [PING^1] [AArch64] Implement Bitwise AND and Set Flags

Hi, Thanks for reviewing the patch and testcase. There were some doubts regarding the addressing modes supported by these instructions. The only source that could be referred was the AARCH64 assembler. Hence, these modifications are implemented as per the assembler. Please let me know if there

[AArch64] Peepholes to generate ldp and stp instructions

Hi, Please find attached the patch that implements load pair(ldp) and store pair(stp) peephole for aarch64 target. Please review the same and let me know if its okay. Build and tested on aarch64-thunder-elf (using Cavium's internal simulator). No new regressions. Thanks, Naveen gcc/

RE: [PING^1] [AArch64] Implement Bitwise AND and Set Flags

Hi, Can we split them into two different patches. Just and in one Thanks for reviewing the patch. I have split the patches for and separately as per your suggestion. There were some doubts regarding the addressing modes supported by these instructions. The only source that could be referred

[AArch64] Bitwise adds and subs instructions with shift

Hi, Please find attached the patch that implements adds and subs instructions with shift for aarch64 target. Testcase have been added for adds and subs instructions similar to the and testcase provided by Ian. Please review the same and let me know if there should be any modifications in the

RE: [AArch64] Bitwise adds and subs instructions with shift

Hi Marcus, Thanks for reviewing the patch and your comments. I'm not sure how good the coverage is from these test cases The shift instructions are not generated with the test case since multiply patterns are generated for the same. Its the same case with other add and sub instructions which

[PATCH, AArch64] Negate and set flags in shift mode

Hi, Please find attached the patch that implements negs instruction with shift for aarch64 target. Testcase have been added for negs instruction. Please review the same and let me know if there should be any modifications in the patch. Build and tested on aarch64-thunder-elf (using Cavium's

[PATCH, AArch64] Compare Negative instruction in shift and extend mode

Hi, Please find attached the patch that implements compare negative instruction with shift and extend mode for aarch64 target. Testcase have been added for compare and compare negative instruction. Please review the same and let me know if there should be any modifications in the patch. Build

[PATCH, AArch64] Add/Sub and set flags instructions in extend and shift_extend mode

Hi, Please find attached the patch that implements addition and Subtraction by setting flags instructions in extend and shift_extend mode for aarch64 target. The patch for Add/Sub instructions by setting flags in shift mode is already posted. Testcase have been added for these instructions.

[PATCH, AArch64] Compare instruction in shift_extend mode

Hi, Please find attached the patch that implements compare instruction in shift_extend mode for aarch64 target. Testcase has been added for compare instructions. Please review the same and let me know if there should be any modifications in the patch. Build and tested on aarch64-thunder-elf

RE: [PATCH, AArch64] Add/Sub and set flags instructions in extend and shift_extend mode

If you're going to do it in one file you'll need to use scan-assembler-times. Hi, Thanks for the suggestion. Please find attached the modified patch as per your suggestions. Please review the same and let me know if there should be any further modifications in it. Thanks, Naveen ---

RE: [PATCH, AArch64] Compare instruction in shift_extend mode

Hi, Same issue as my previous reply applies here. Thanks for the suggestion. Please find attached the modified patch as per your suggestions. Please review the same and let me know if there should be any further modifications in it. Thanks, Naveen --- gcc/config/aarch64/aarch64.md

[PING ^1] [AArch64] Bitwise adds and subs instructions with shift

Hi, Please consider this as a reminder to review the patch posted at following link:- http://gcc.gnu.org/ml/gcc-patches/2013-04/msg00045.html Please review the patch and let me know if its okay? Thanks Regards, Naveen.H.S

RE: [PATCH, AArch64] Compare instruction in shift_extend mode

Hi, I suggest for this one test case either making it compile only and dropping main() such that the pattern match only looks in the assembled output of the cmp_* functions The testcase will check only for assembly pattern of the instruction as per your suggestion. Please find attached the

[PATCH, AArch64] Negate with Compare instruction

Hi, Please find attached the patch that implements Negate with Carry instruction for aarch64 target. Please review the same and let me know if there should be any modifications in the patch. Build and tested on aarch64-thunder-elf (using Cavium's internal simulator). No new regressions.

Re: [PATCH, AArch64] Negate with Compare instruction

Hi, This and the preceding scan are the same pattern. So if either passes you'll fail to detect a failure in the other. Thanks for the suggestion. Please find attached the modified patch as per your suggestions. Please review the same and let me know if there should be any further

Re: [PATCH, AArch64] Handle SYMBOL_SMALL_TPREL appropriately

Hi Marcus, Thanks for the review. OK, but fix the trailing white space in the patch Done. Committed with the modification. Can you prepare a backport into 4.9 ILP32 support is not completely added in 4.9 and hence the patch is not needed. Thanks, Naveen

Re: [PATCH, AArch64] [4.9] Handle SYMBOL_SMALL_TPREL appropriately

Hi Marcus, The handling of SYMBOL_SMALL_TPREL is present in 4.9 and very clearly has exactly the same issue. Please find attached the patch ported for gcc-4.9. Please review the patch and let us know if its okay? Regression tested on aarch64-elf. Thanks, Naveen 2015-02-20 Andrew Pinski

[PATCH, AArch64] Handle SYMBOL_SMALL_TPREL appropriately

Hi, Please find attached the patch that handles the operations on SYMBOL_SMALL_TPREL appropriately. It fixes gcc.dg/tls/opt-11.c regression on ilp32. Please review the patch and let us know if its okay? Regression tested on aarch64-elf. Thanks, Naveen 2015-02-02 Andrew Pinski

Re: [PATCH] Fix enum operands exchange in ipa-inline.c

Hi Richard, Thanks for the quick review and comments. Please find attached the modified patch as per your suggestion. Thanks, Naveen From: Richard Biener richard.guent...@gmail.com Sent: Monday, January 12, 2015 2:48 PM To: Hurugalawadi, Naveen Cc: gcc

Re: [PATCH] Fix enum operands exchange in ipa-inline.c

Hi, Sorry, Had forgot the ChangeLog. ChangeLog 2015-01-12 Naveen H.S naveen.hurugalaw...@caviumnetworks.com * ipa-inline.c (inline_small_functions): Swap the operands in enum. Thanks, Naveen

[PATCH] Fix enum operands exchange in ipa-inline.c

Hi, Please find attached the patch that fixes swap of operands to enum in ipa-inline.c. This issue popped up when running dhrystone with -fdump-ipa-all. Please review the patch and let me know it its okay? Regression tested on aarch64-elf. Thanks, Naveen--- a/gcc/ipa-inline.c 2015-01-12

[PATCH, AArch64] Fix abitest for ilp32

Hi, Please find attached the patch that fixes abitest for ilp32. testfunc_ptr is a 32bit pointer in ILP32 but is being loaded as 64bit. Hence some of the func-ret testcases FAIL's for ILP32. Please review the patch and let us know if its okay? Regression tested on aarch64-elf. Thanks, Naveen

[PR23664] Fold (a C1) + (b C2) to (a C1) | (b C2) iff (C1 C2) == 0

Hi, Please find attached the patch PR23664.patch that converts the pattern:- (a C1) + (b C2) into (a C1) | (b C2) iff (C1 C2) == 0. Please review and let me know if its okay. Regression tested on AARH64 and x86_64. Thanks, Naveen gcc/testsuite/ChangeLog: 2015-07-07 Naveen H.S

[PR25529] Convert (unsigned t * 2)/2 into unsigned (t 0x7FFFFFFF)

Hi, Please find attached the patch PR25529.patch that converts the pattern:- (unsigned * 2)/2 is into unsigned 0x7FFF Please review and let me know if its okay. Regression tested on AARH64 and x86_64. Thanks, Naveen gcc/testsuite/ChangeLog: 2015-07-07 Naveen H.S

[PR25530] Convert (unsigned t / 2) * 2 into (unsigned t ~1)

Hi, Please find attached the patch PR25530.patch that converts the pattern:- (unsigned / 2) * 2 is into (unsigned ~1). Please review and let me know if its okay. Regression tested on AARH64 and x86_64. Thanks, Naveen gcc/testsuite/ChangeLog: 2015-07-07 Naveen H.S

Re: Move some flag_unsafe_math_optimizations using simplify and match

Hi Richard, Thanks very much for your review and comments. Can you point me to which patterns exhibit this behavior? root(x)*root(y) as root(x*y) expN(x)*expN(y) as expN(x+y) pow(x,y)*pow(x,z) as pow(x,y+z) x/expN(y) into x*expN(-y) Long Double and Float variants FAIL with segmentation

Re: Move some flag_unsafe_math_optimizations using simplify and match

Hi, Works for me if you specify -fno-math-errno. I think that's a regression we can accept. Modified the pattern with fno-math-errno as a condition. Can you re-post with the typo fix and the missing :s? Please find attached the modified patch as per the review comments. Please suggest if

Move some flag_unsafe_math_optimizations using simplify and match

Hi, Please find attached the modified patch as per the comments. Tested the patch on AArch64 and X86 without any regressions. The other hunks of the earlier patch have been removed as per the earlier comments due to failure in regressions. Investigated those issues and found that its because of

Re: [PR16107] Convert cos (-x) into cos (x)

, Naveen From: Marc Glisse marc.gli...@inria.fr Sent: Monday, August 17, 2015 10:35 AM To: Hurugalawadi, Naveen Cc: gcc-patches@gcc.gnu.org Subject: Re: [PR16107] Convert cos (-x) into cos (x) On Fri, 7 Aug 2015, Hurugalawadi, Naveen wrote: gcc

Re: Move some flag_unsafe_math_optimizations using simplify and match

Hi, Thanks again for your review and useful comments. I see. But I can't really help without a testcase that I can use to have a look (same for the above issue with the segfaults). The following testcase does not generate x as needed. double t (double x) { x = sqrt

Re: [PR25529] Convert (unsigned t * 2)/2 into unsigned (t 0x7FFFFFFF)

Hi, extend it - it should also work for non-INTEGER_CST divisors and it should work for any kind of division, not just exact_div. Please find attached the patch pr25529.patch that implements the pattern for all divisors Please review and let me know if its okay. Regression tested on

[PR16107] Convert cos (-x) into cos (x)

Hi, Please find attached the patch pr16107.patch that converts the pattern:- cos (-x) - cos (x) Please review and let me know if its okay. Regression tested on AARH64 and x86_64. Thanks, Naveen 2015-08-07 Naveen H.S naveen.hurugalaw...@caviumnetworks.com PR middle-end/16107

Re: [PR25530] Convert (unsigned t / 2) * 2 into (unsigned t ~1)

Your previous patch correctly restricted this to unsigned types. Thanks for your review and comments. Please find attached the modified patch as per your comments. Please let me know if this version is okay? Thanks, Naveen 2015-07-22 Naveen H.S naveen.hurugalaw...@caviumnetworks.com

Re: [PR25529] Convert (unsigned t * 2)/2 into unsigned (t 0x7FFFFFFF)

so using wi::mask is prefered here. Thanks for your review and comments. Please find attached the modified patch as per your comments. Please let me know if this version is okay? Thanks, Naveen 2015-07-22 Naveen H.S naveen.hurugalaw...@caviumnetworks.com gcc/testsuite/ChangeLog:

Fold some equal to and not equal to patterns in match.pd

Hi, Please find attached the patch which performs following patterns folding in match.pd:- a ==/!= a p+ b to b ==/!= 0. a N ==/!= 0 to a(-1N) ==/!= 0. a * N ==/!= 0 where N is a power of 2 to a (-1N2) ==/!= 0 where N2 is log2 of N. Please review the same and let us know if its okay?

Re: [PR25529] Convert (unsigned t * 2)/2 into unsigned (t 0x7FFFFFFF)

Hi, For signed types with TYPE_OVERFLOW_UNDEFINED you can simply cancel the operation (even for non-power-of-two multipliers). Thanks for the review and comments. Please find attached the modified patch as per your comments. Please review the same and let me know if any further modifications

Re: [PR25530] Convert (unsigned t / 2) * 2 into (unsigned t ~1)

Hi, handle exact_div differently, like fold-const.c does. Then expressing ~1 with the result expression is really excessive - you should simply build this with @1 - 1 if @1 is a power of two. Thanks for the review and comments. Please find attached the modified patch as per your comments.

Multiply Optimization in match and Simplify

Hi, Please find attached the patch that moves some multiply optimizations from fold-const using simplify and match. Please review the patch and let me know if any modifications are required. Tested the patch on X86. Observing following failures:- >> FAIL: gcc.dg/fold-plusmult.c

Re: Move some bit and binary optimizations in simplify and match

Hi, >> So I suggest to modify your patch to do Done. Please find attached the modified patch. Regression tested successfully on X86_64. Thanks, Naveendiff --git a/gcc/fold-const.c b/gcc/fold-const.c index 1e7fbb4..23c6fa9 100644 --- a/gcc/fold-const.c +++ b/gcc/fold-const.c @@ -9692,28 +9692,6

More Division optimization using match and simplify

Hi, Please find attached the patch that moves some more division optimizations from fold-const using match and simplify. Please review the patch and let me know if any modifications are required. Hopefully got the converts right this time :-) Regression tested the patch on X86 without any

Re: Multiply Optimization in match and Simplify

Hi, Thanks for the review and suggestions. >> Please do not drop A - B -> A + (-B) from fold-const as match.pd >> doesn't implement all of fold-const.c negate_expr_p support. Done. >> which is more expensive. This means that we miss a >> (bit_and (bit_not @0) INTEGER_CST@1) Should we have

Re: Division Optimization in match and simplify

Hi, Please find attached the modified patch as per review comments. >> use :s on both inner rdiv in both patterns. With that the two patterns are >> ok. Done. >> Omit the parens around REAL_CST@0 Done. Regression tested on X86_64. Thanks, Naveendiff --git a/gcc/fold-const.c

Division Optimization in match and simplify

Hi, Please find attached the patch that moves some division optimizations from fold-const using match and simplify. Please review the patch and let me know if any modifications are required. Regression tested the patch on X86 without any issues. Thanks, Naveen ChangeLog 2015-11-04 Naveen

Re: Division Optimization in match and simplify

Hi, >> it probably works for all integer divisions (floor_div, etc) >> since it is exact and thus does not depend on the rounding. Please find attached the modified patch as per comments. Thanks, Naveendiff --git a/gcc/fold-const.c b/gcc/fold-const.c index ee9b349..88dbbdd 100644 ---

Re: Division Optimization in match and simplify

Hi, Thanks for the review and comments. >> I thought we were mostly using the 'convert?' >> and tree_nop_conversion_p on integers Done. Cleared all instances of convert which are not required. However, I am still confused about the use of "convert" in match and simplify. >> So all patterns

Re: Move some bit and binary optimizations in simplify and match

Hi, Please find attached the modified patch of duplicate patterns which were posted in the earlier part. Please review them and let me know if any further modifications are required. Thanks, Naveendiff --git a/gcc/fold-const.c b/gcc/fold-const.c index de45a2c..b36e2f5 100644 ---

Re: Move some bit and binary optimizations in simplify and match

Hi, >> That's not what Richard meant. We already have: Done. As per the comments. Please find attached the modified patch as per your comments. Please review them and let me know if any further modifications are required. Thanks, Naveendiff --git a/gcc/fold-const.c b/gcc/fold-const.c index

Re: Move some bit and binary optimizations in simplify and match

Hi, Thanks for all the suggestions. Please find attached the modified patch as per your suggestions. I had missed a mail as pointed by Marc Glisse. Now I have implemented everything suggested. Please review the patch and let me know if any further modifications are required. I have some

Re: Move some bit and binary optimizations in simplify and match

Hi. >> please adjust also according to these comments. Adjusted the patch as per your comments. Please find attached the patch as per your comments. Please review the patch and let me know if any further modifications are required. Thanks, Naveendiff --git a/gcc/fold-const.c b/gcc/fold-const.c

Re: Move some bit and binary optimizations in simplify and match

Hi, Thanks very much for your detailed explanation regarding the queries. >> you are missing the convert? on the lshift now, without it the >> tree_nop_conversion_p check always evaluates to true. Done. >> fold-const.c which handles TRUTH_NOT_EXPR but logical_inverted_value >> does not handle

Re: Move some bit and binary optimizations in simplify and match

Hi, >> +/* Fold X + (X / CST) * -CST to X % CST. */ >> This one is still wrong Removed. >> I don't understand the point of the FLOAT_TYPE_P check. The check was there in fold-const. So, just had the same check. >> Will we also simplify (A & B) - (A & ~B) into B - (A ^ B) ? Done. >> or maybe

Re: Move some bit and binary optimizations in simplify and match

Hi, >> use if (wi::bit_and (@2, @1) == 0) Done. >> and instead of the 2nd group >> place a :c on the minus of the one not matching INTEGER_CSTs. Done. Just curious to know whether ":c" act as commutative operation in the input as well as output in this case? Regression tested without any extra

Re: Move some bit and binary optimizations in simplify and match

Hi Richard, Thanks for your review and useful comments. I will move the future optimization patterns with all the conditions present in fold-const or builtins file as per your suggestions. Please find attached the patch as per your comments. Please review the patch and let me know if any

Move some bit and binary optimizations in simplify and match

Hi, Please find attached the patch that moves some more patterns from fold-const using simplify and match. Please review the patch and let me know if any modifications are required. Tested the patch on X86 without any regressions. Thanks, Naveen ChangeLog 2015-10-07 Naveen H.S

Re: Move some bit and binary optimizations in simplify and match

Hi Richard, Thanks for the comments. Sorry, I was confused with handling the const and variable together part. Have modified them. Also, considered that both (X & Y) can be const or variable in those cases for which match patterns have been added. Please let me know whether its correct or only

Move remaining flag_unsafe_math_optimizations using simplify and match

Hi, Please find attached the remaining part of patch. Tested the patch on AArch64 and X86 without any regressions. Please review the patch and let me know if any modifications are required. Thanks, Naveen ChangeLog 2015-08-25 Naveen H.S naveen.hurugalaw...@caviumnetworks.com *

[Patch] PR67351 Implement << N & >> N optimizers

Hi, Please find attached the patch "pr67351.patch" that implements the pattern << N & >> N optimizers. Please review and let me know if its okay. Regression tested on AARH64 and x86_64. Thanks, Naveen 2015-09-01 Naveen H.S gcc/ChangeLog:

Re: [Patch] PR67351 Implement << N & >> N optimizers

Hi, Thanks for all the review and comments. >> replace the precision test with wi::ltu_p (@1, TYPE_PRECISION (type) >> use element_precision instead of TYPE_PRECISION Please find attached the modified patch as per review comments. Please review the same and let me know if the patch is okay?

Re: [AArch64] Fix Prefetch ICE

Hi Marcus, Thanks for the review and comments. >> OK and can you back port to 5 ? Please find attached the backported patch on gcc-5-branch. Regression tested on AArch64 without any issues. 2015-09-28 Andrew Pinski ChangeLog * config/aarch64/aarch64.md

[AArch64] Fix Prefetch ICE

Hi, Please find attached the patch that fixes an ICE for prefetch. The predicate is too lose for the constraints. Hence, the patch tightens up the predicate to be exactly as constraint allows, avoids a “reload” and allows better code generation.   Submitted on behalf of Andrew Pinski. Thanks,

PATCH] Fix PR 31531: A microoptimization of isnegative of signed integer

Hi, Please find attached the patch that performs optimization on unsigned values. Original fold-const part implemented in match.pd. Please review the patch and let us know if it's OK? Regression Tested on X86_64 with no regressions. Thanks, Naveen ChangeLog: * match.pd (cmp (convert (bit_not

Re: PATCH] Fix PR 31531: A microoptimization of isnegative of signed integer

Hi, >> I'm also failing to see why you can't enhance the existing Please find attached the patch that enhances the existing pattern. Please review the patch and let me know if any further modifications are required. Thanks, Naveendiff --git a/gcc/match.pd b/gcc/match.pd index 6c8ebd5..bd47a91

[PATCH] Fix PR23471

Hi, Please find attached the patch that fixes the tree optimization 23471. Please review the patch and let me know if its okay? Regression tested on X86_64. Thanks, Naveen 2016-03-31 Naveen H.S * fold-const.c

[PATCH] Fix PR31096

Hi, Please find attached the patch that fixes the PR31096. Should the optimization be extended to addition and other operations as well? Please review the patch and let me know if its okay? Regression tested on X86_64. Thanks, Naveen 2016-03-31 Naveen H.S

Re: [PATCH] Fix PR31096

Hi, >> type is the return type of the comparison. The relevant type here is TREE_TYPE (@0). Done. >>Maybe add a testcase with unsigned, to check that it does not transform? Added the testcase >> you could probably use tree_expr_nonzero_p Done. I had !wi::eq_p (@1, 0) for INTEGER_CST, but when

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